JPS5952546B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5952546B2 JPS5952546B2 JP51133484A JP13348476A JPS5952546B2 JP S5952546 B2 JPS5952546 B2 JP S5952546B2 JP 51133484 A JP51133484 A JP 51133484A JP 13348476 A JP13348476 A JP 13348476A JP S5952546 B2 JPS5952546 B2 JP S5952546B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- base
- type
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
Description
【発明の詳細な説明】
この発明は、ｐ叩トランジスタと叩ｎトランジスタの複
合構造から成るバイポーラ型電流注入ロジック（Ｉｎｔ
ｅｇｒａｔｅｄＩｎｊｅｃｔｉｏｎＬｏｇｉｃ、以下Ｉ
２Ｌと略す）構造の半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a bipolar current injection logic (Int
egratedInjectionLogic, hereinafter I
2L) structure.
従来、バイポーラ型集積回路装置においては、拡散工程
の複雑さ、写真製板回数の多さなどから高密度化、ひい
ては低電力化に一定の限界がみられていた。ところが近
年、Ｉ″Ｌが発明されるにおよんで、バイポーラ型集積
回路装置においても、大幅な高密度化、低電力化が可能
になつてきている。そこで、この発明では上述のような
Ｉ″Ｌの性能をさらに向上させることを目的としてなさ
れたものである。Conventionally, in bipolar integrated circuit devices, there has been a certain limit to achieving higher density and lowering power consumption due to the complexity of the diffusion process and the large number of photolithographic processes. However, in recent years, with the invention of I''L, it has become possible to significantly increase density and reduce power consumption even in bipolar integrated circuit devices. This was done with the aim of further improving the performance of L.
以下図面によつてまず従来例について説明し、次いでこ
の発明の実施例について説明する。第１図は従来の半導
体装置を示す断面図で、マルチ・コレクタタイプのＩ２
Ｌの一例である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A conventional example will be described below with reference to the drawings, and then an embodiment of the present invention will be described. Figure 1 is a cross-sectional view of a conventional semiconductor device, showing a multi-collector type I2.
This is an example of L.
Ｉ２Ｌの動作においては、ｐ形領域４が電流供給源（イ
ンジェクタと呼ばれる）となり、ｎ゛基板１は接地され
、ｐ形領域２が入力部、ｎ形領域部３１、３２、３３が
出力部となる。第１図において、ｐ形領域４、ｎ”基板
１、Ｐ形領域２をＩ″Ｌにおけるｐ叩トランジスタ（以
下ｐｎｐＴｒという）部とし、ｎ゛基板１、Ｐ形領域２
、ｎ形領域３１、３２、３３を叩ｎトランジスタ（以下
叩ｎＴｒという）部と考えることにする。Ｉ２Ｌの叩ｎ
Ｔｒ部において、ｎｆ基板１をエミッタ領域、ｐ形領域
２をベース領域、ｎ形領域３１、３２、３３をコレクタ
領域とする。In the operation of I2L, the p-type region 4 serves as a current supply source (called an injector), the n'substrate 1 is grounded, the p-type region 2 serves as an input section, and the n-type regions 31, 32, and 33 serve as output sections. Become. In FIG. 1, a p-type region 4, an n'' substrate 1, and a p-type region 2 are used as a p-type transistor (hereinafter referred to as pnpTr) in I''L, and an n'' substrate 1, a p-type region 2
, n-type regions 31, 32, and 33 are considered to be a double-n transistor (hereinafter referred to as double-nTr) section. I2L's slap n
In the Tr section, the nf substrate 1 is used as an emitter region, the p-type region 2 is used as a base region, and the n-type regions 31, 32, and 33 are used as collector regions.
エミッタ接地動作は、Ｉ’Ｌの動作時とバイアス関係が
同じであるから叩ｎＴｒ部のエミッタ接地特性は、Ｉ″
Ｌの出力特性を近景することになる。第２図は叩ｎＴｒ
部のエミッタ接地電流増幅率（以下βｕと略す）とコレ
クタ電流の関係を、各コレクタ領域３１、３２、３３に
ついてそれぞれＣｓ、、Ｃ３２、Ｃ。In the emitter grounding operation, the bias relationship is the same as in the I'L operation, so the emitter grounding characteristic of the nTr section is I''
This will give a closer look at the output characteristics of L. Figure 2 is Tr
The relationship between the emitter ground current amplification factor (hereinafter abbreviated as βu) and the collector current for each collector region 31, 32, and 33 is shown as Cs, C32, and C, respectively.
。として示したグラフである。ｎｐｎＴｒ部のコレクタ
電流に対するβｕの関係は、マルチ・コレクタを有する
場合、ベース電極から遠い所に位置するコレクタほど高
電流領域でのβｕの低下が著しい。これは、ベース電極
とコレクタ領域３１、３２、３３が離れるに従つて、実
効的ベース抵抗が上昇し、それがベース領域２内での再
結合電流を増加させ、βｕを低下させ、さらにトランジ
スタの高速動作を阻害する。. This is a graph shown as . Regarding the relationship between βu and the collector current of the npnTr section, when the npnTr section has a multi-collector, βu decreases more significantly in the high current region as the collector is located farther from the base electrode. This is because as the base electrode and the collector regions 31, 32, 33 are separated, the effective base resistance increases, which increases the recombination current in the base region 2, lowers βu, and further increases the resistance of the transistor. Obstructs high-speed operation.
このように従来のＩ２Ｌにおいては、特にマルチ・コレ
クタを有する構造の場合、ベース電極からのコレクタ領
域３１，３２，３３の距離によつて出力特性が大幅に変
化するとともに、そのための出力数にも制限が加えられ
てくる。In this way, in the conventional I2L, especially in the case of a structure having a multi-collector, the output characteristics vary greatly depending on the distance of the collector regions 31, 32, 33 from the base electrode, and the number of outputs also varies. Restrictions will be added.
またベース電極の位置を変えて多出力構造にすれば、回
路設計上制限が加えられることになる。特にマルチ・コ
レクタ構造では、それぞれのコレタタ領域３１，３２，
３３によつて出力特性が違つており、従つて出力数も多
く取ることが困難で゛あつた。この発明は、上述の点に
鑑みなされたもので、マルチ・コレクタ構造を有するＩ
２Ｌにおいて、各コレクタ領域の出力特性の違いが、実
効的ベース抵抗によるものであることから、各コレクタ
領域に対する実効的ベース抵抗領域を各コレクタ領域に
対して同一にする構造を提供することによつて、Ｉ２Ｌ
の各コレクタの出力特性の均一化と、高速化等の特性向
上、さらに、出力数の増加をはかつたものである。以下
この発明の実施例について説明する。第３図はこの発明
の一実施例を示すもので、１２Ｌ（７）ＮＰｎＴｒ部の
ベース領域２内へ、高不純物濃度のｐ＋形領域５を設け
たものである。Furthermore, if the position of the base electrode is changed to create a multi-output structure, restrictions will be imposed on circuit design. In particular, in a multi-collector structure, each collector region 31, 32,
Since the output characteristics differ depending on the type of 33, it has been difficult to obtain a large number of outputs. The present invention has been made in view of the above points, and is based on an integrated circuit having a multi-collector structure.
In 2L, the difference in the output characteristics of each collector region is due to the effective base resistance, so by providing a structure in which the effective base resistance region for each collector region is the same for each collector region. Well, I2L
The aim is to equalize the output characteristics of each collector, improve characteristics such as speeding up, and increase the number of outputs. Examples of the present invention will be described below. FIG. 3 shows an embodiment of the present invention, in which a p+ type region 5 with a high impurity concentration is provided in the base region 2 of a 12L(7)NPnTr section.
このｐ＋形領域５は、コレクタ領域３１，３，２，３３
のいずれかに近接していればよいが、必要によりコレク
タ領域３１，３２，３３の周囲をすべて囲むことも有効
である。This p+ type region 5 includes collector regions 31, 3, 2, 33
Although it is sufficient to be close to any one of the collector regions 31, 32, and 33, it is also effective to surround all the collector regions 31, 32, and 33 if necessary.
またこのｐ＋形領域５は不純物濃度が高くそのため抵抗
率が非常に低く、従つてこのｐ＋形領域５を電流が通過
して．も、抵抗による電圧降下をほとんど無視できる。
そのため、マルチ・コレクタ構造の場合、コレクタ領域
３１，３２，３３とベース電極の距離に関係なく、同じ
実効的ベース抵抗および再結合電流を有することになり
、Ｉ２Ｌ（１７）ＮｐｎＴｒ部のβ。は同一の特性をも
つ。またこの発明によれば、コレクタ領域３１，３２，
３３直下のベース領域２の不純物濃度は、実効的ベース
抵抗および再結合電流低減のためｐ＋形領域５の濃度と
は別個に形成されるものであるから、ＮｐｎＴｒ部の他
の特性に悪影響・をおよぼすことなく、有効にベース抵
抗および再結合電流のみを低減させ得る。第４図はこの
発明の他の実施例を示すもので、１２Ｌ（７）ＮＰｎＴ
ｒ部がース領域２内部に、理込み形にｐ＋形領域６を設
けたものである。Also, this p+ type region 5 has a high impurity concentration and therefore has a very low resistivity, so that current passes through this p+ type region 5. Also, the voltage drop due to resistance can be almost ignored.
Therefore, in the case of a multi-collector structure, regardless of the distance between the collector regions 31, 32, 33 and the base electrode, it will have the same effective base resistance and recombination current, and β of the I2L(17)NpnTr portion. have the same properties. Further, according to the present invention, the collector regions 31, 32,
Since the impurity concentration of the base region 2 directly under the base region 33 is formed separately from the concentration of the p+ type region 5 in order to reduce the effective base resistance and recombination current, it has an adverse effect on other characteristics of the NpnTr section. It is possible to effectively reduce only the base resistance and recombination current without causing any adverse effects. FIG. 4 shows another embodiment of the present invention, in which 12L(7)NPnT
In the r section, a p+ type region 6 is provided inside the earth region 2 in a well-structured manner.
この実施例の場合、埋込み形のゲ領域６の形成には、高
加速エネルギーによるｐ形不純物のイオン注入法等が考
えられる。またゲ形領域６の高濃度化にやや難点がある
場合は、コレクタ領域３１，３２，３３の全周囲を取り
囲むように埋込み形のｐ＋形領域６を設け、それによつ
て実効的ベース抵抗および再結合電流を低下させるよう
にしてもよい。これらの実施例にみられるＩ２Ｌ（７）
ＮＰｎＴｒ部のベース領域２内に設けられたｐ＋形領域
６の不純物濃度は、ベース領域２の不純物濃度の数倍〜
数１００倍程度であり、Ｉ２Ｌの形状、希望する特性等
によつて、最適値が決定される。以上説明したようにこ
の発明は、Ｉ２Ｌ（７）ＮＰｎＴｒ部のベース領域内に
不純物濃度の高いｐ＋形領域を形成することによつて、
実効的ベース抵抗および再結合電流を減少させ、マルチ
・コレクタ構造のコレクタ領域相互間の特性差を少なく
すると共にコレクタ数を増加させることも可能になる。In the case of this embodiment, a method such as ion implantation of p-type impurities using high acceleration energy may be used to form the buried type region 6. If there is some difficulty in increasing the concentration of the Ge-type region 6, a buried p+-type region 6 may be provided to surround the entire periphery of the collector regions 31, 32, and 33, thereby increasing the effective base resistance and re-concentration. The coupling current may also be reduced. I2L (7) found in these examples
The impurity concentration of the p+ type region 6 provided in the base region 2 of the NPnTr section is several times the impurity concentration of the base region 2.
It is approximately several hundred times larger, and the optimum value is determined depending on the shape of I2L, desired characteristics, etc. As explained above, the present invention has the following advantages: By forming a p+ type region with a high impurity concentration in the base region of the I2L(7)NPnTr section,
It is also possible to reduce the effective base resistance and recombination current, reduce the difference in characteristics between the collector regions of the multi-collector structure, and increase the number of collectors.
かようにこの発明によれば、バイポーラ型電流注入ロジ
ツクの特性の向上と出力数の増加が可能となり、バイポ
ーラ型電流注入ロジツクの特徴である高密度化、低電力
化に対してさらに大幅な発展が期待されるものである。Thus, according to this invention, it is possible to improve the characteristics of bipolar current injection logic and increase the number of outputs, resulting in further significant progress in achieving high density and low power consumption, which are the characteristics of bipolar current injection logic. is expected.
第１図は従来のＩ２Ｌにおけるマルチ・コレクタ構造の
断面図、第２図は第］図に示したＩ２ＬのＮｐｎＴｒ部
のエミツタ接地電流増幅率と、コレクタ電流との関係を
示す図、第３図はこの発明の一実施例を示す断面図、第
４図はこの発明の他の実施例を示す断面図である。
図中、１はｎ＋基板、２はベース領域、３１，３２，３
３はコレクタ領域、４はｐ形領域、５，６はｐ＋形領域
である。Figure 1 is a cross-sectional view of a multi-collector structure in a conventional I2L, Figure 2 is a diagram showing the relationship between the common emitter current amplification factor and collector current of the NpnTr section of the I2L shown in Figure 3, and Figure 3. 4 is a sectional view showing one embodiment of the invention, and FIG. 4 is a sectional view showing another embodiment of the invention. In the figure, 1 is an n+ substrate, 2 is a base region, 31, 32, 3
3 is a collector region, 4 is a p-type region, and 5 and 6 are p+-type regions.
Claims (1)
造から成り、前記ｐｎｐトランジスタのベース領域及び
コレクタ領域をそれぞれ前記ｎｐｎトランジスタのエミ
ッタ領域及びベース領域と共有したバイポーラ型電流注
入ロジックの半導体装置において、前記ｎｐｎトランジ
スタのベース領域の不純物濃度よりも高い領域を前記ｎ
ｐｎトランジスタのベース領域の内側に設けたことを特
徴とする半導体装置。1. In a bipolar current injection logic semiconductor device comprising a composite structure of a pnp transistor and an npn transistor, in which a base region and a collector region of the pnp transistor are shared with an emitter region and a base region of the npn transistor, respectively, the base of the npn transistor is The region where the impurity concentration is higher than that of the region n
A semiconductor device characterized in that it is provided inside a base region of a pn transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51133484A JPS5952546B2 (en) | 1976-11-06 | 1976-11-06 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51133484A JPS5952546B2 (en) | 1976-11-06 | 1976-11-06 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5357980A JPS5357980A (en) | 1978-05-25 |
| JPS5952546B2 true JPS5952546B2 (en) | 1984-12-20 |
Family
ID=15105840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51133484A Expired JPS5952546B2 (en) | 1976-11-06 | 1976-11-06 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952546B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55163913A (en) * | 1979-06-08 | 1980-12-20 | Sony Corp | Flip-flop circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5160177A (en) * | 1974-09-03 | 1976-05-25 | Western Electric Co | Handotaisochi oyobi sonoseizohoho |
| JPS5173886A (en) * | 1974-12-23 | 1976-06-26 | Tokyo Shibaura Electric Co | Handotaisochitosono seizohoho |
-
1976
- 1976-11-06 JP JP51133484A patent/JPS5952546B2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5160177A (en) * | 1974-09-03 | 1976-05-25 | Western Electric Co | Handotaisochi oyobi sonoseizohoho |
| JPS5173886A (en) * | 1974-12-23 | 1976-06-26 | Tokyo Shibaura Electric Co | Handotaisochitosono seizohoho |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5357980A (en) | 1978-05-25 |
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