JPS5952386B2 - signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing circuit for processing distance information in a radar.

In a radar system or the like that detects the distance of an approaching target and determines its speed, if another target gets between the target and the target, the speed of that target is mistakenly recognized as being abnormally high.

However, based on the expected maximum speed of the target and the minimum distance that can be intercepted, the maximum distance that can be approached during the transmission repetition time can be set.

This creates an interrupt malfunction prevention circuit.

A conventional signal processing device is shown in FIG. 1 and will be described.

In FIG. 1, flip-flop 1 is operated by the transmission trigger and radar video, and gate circuit 2 is thereby activated.
, the tally of the tally generator 3 is sent to the counter circuit 4.
The value is counted as the distance to the target and is stored in register 5, the distance due to the next transmission is stored in register 6, the value is subtracted by logical subtractor 7, and logical comparator 8
The presence or absence of an interrupt was detected by comparing the setting value and the size.

However, such a conventional circuit configuration has the disadvantage that it is complicated and requires a large number of elements, wires, etc.

The present invention has been made to eliminate these drawbacks, and provides a signal processing circuit that uses a simple circuit to detect when another target has come between the radar and the target.

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, this embodiment uses a shift register 9 as a storage element and will be described.

The shift register 9 is provided with a tarock so that it can be rotated exactly once in each transmission cycle, and is used to store the distance information of the radar video 14 for only one transmission repetition time.

10 is a flip-flop which is set by the radar video 14 and reset by the output of the shift register 9.

Reference numeral 11 denotes a monostable multi-oscillator operated by the radar video signal, which is output as a pulse with a constant time width from the radar video signal.

12 is a pulse width comparator that compares the outputs of the flip-flop 10 and the monostable multi-oscillator 11, and if the input to the flip-flop 10 is longer than that of the monostable multi-oscillator 11, the output is adjusted accordingly. This is a detector with a

This circuit diagram operates according to the time relationship shown in FIG.

In other words, the trigger 13 to the transmission 1 corresponding to the radar transmission wave
Radar video 14 is obtained from the approaching target by a transmitted pulse such as .

This time relationship is maintained by the shift register 9, and the shift register output 15 is output at a time an elapsed time from tn+1.

At this time, there is input to an+1 as radar video.

The flip-flop and monostable multi-oscillator 11 are thereby output, but the flip-flop is reset.

The monostable multi-oscillator 11 is set to be larger than the time corresponding to the maximum approach distance expected during the transmission repetition period and smaller than the time corresponding to the minimum distance that can be interrupted, and the output 17 of the monostable multi-oscillator is output after a time τ. It turns out.

Now, if there is an interrupt at tn+2, then an+2
is abnormally short compared to an+1, so that the flip-flop 10 has an output longer than the pulse from the monostable multi-oscillator 11.

In such a state, the pulse width comparator 12 generates an interrupt signal such as the pulse width comparator output 18, so that it is possible to detect that an interrupt has occurred.

In this way, by using the shift register and pulse-like processing, it becomes possible to process interrupt detection without using a logic operation circuit, and the circuit is simplified.

In the detailed description of this invention here, as a storage element)
- Although the description has been made assuming that a register is used, it is clear that for example, a RAM (Random Access Memory), etc. can be used as the storage element without being limited to this.

As explained above, according to the signal processing device of the present invention,
It is possible to detect that another new target has come between the target and the radar device with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional signal processing device, FIG. 2 is a block diagram showing a signal processing device according to an embodiment of the present invention, and FIG. 3 is a waveform showing the operation of the signal processing device shown in FIG. It is a diagram. In the figure, 9 is a shift I register which is a storage element;
0 is a flip-flop, 11 is a monostable multi-oscillator, 1
2 is a pulse width comparator which is a detector. Note that the numbers in the middle of the figure indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a device that detects the interruption of a new target between the target and the radar, the reception signal that is received in response to the distance between the target and the radar is manually generated for each repeated transmission signal of the radar at a certain period. a memory element that stores and outputs data during a predetermined repetition period of the transmitted signal; a flip-flop that is set by the received signal and set by the output signal of the memory element; and a flip-flop that is activated by the received signal and generates a pulse of a predetermined time width. A signal processing device comprising: a monostable multi-oscillator that outputs an output; and a pulse width comparator that compares the output pulse width of the flip-flop with the output pulse width of the monostable multi-oscillator to detect an interruption of a new target.