JPS5952347A - Console device - Google Patents

Abstract

PURPOSE:To share a system console typewriter with plural central arithmetic processors (CPU), by connecting these processors to the typewriter via a switch mechanism part. CONSTITUTION:The output data sent from CPUs 10-13 through signal lines L0-L3 are stored temporarily in data buffers 50-53. A control part 6 controls integrally a switch control part 2 and delivers successively the data stored in a data buffer 5 to a system console typewriter 3. The part 6 also has a function which adds a header showing one of plural units of CPU 1 that delivers the data under output to the beginning part of the output data to be applied to the typewriter 3. Then the data stored in the buffer 5 is transmitted to the typewriter 3 via an interface 7 in accordance with a command given from the part 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a console device in which one system console typewriter is shared by a plurality of central processing units.

[Technical background of the invention]

Conventionally, one system console typewriter has been connected to each central processing unit M (hereinafter referred to as C'PU). System console typewriter with
It was mainly used for error debugging and maintenance of computer systems, and from the user's perspective, it was a device that was used infrequently and was not necessarily needed.

[Problems with background technology]

By the way, in large-scale complex computing systems such as dual and duplex systems that increase system safety,
The number of system console typewriters required is equal to the number of CPUs constituting the system, which increases the cost of the system and increases the installation space for the plurality of system console typewriters.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to address the above-mentioned drawbacks and provide a console device in which one system console typewriter is shared by a plurality of CPUs.

(Summary of the Invention) In a computer device having a plurality of central processing units, data is transmitted between the plurality of central processing units and one system console typewriter from the plurality of central processing units. A function for transmitting the data to the system console typewriter in sequence after receiving the data to be sent to the system console typewriter, and a function for transmitting the data transmitted from the system console typewriter to the central processing unit among the plurality of central processing units. The above object is achieved by providing a switching mechanism section having a function of selecting one of these and transmitting data to the central processing unit.

(Embodiment of the Invention) An embodiment of the computer device of the present invention will be described below with reference to all the drawings.

FIG. 1 is a configuration diagram showing an embodiment of a computer device of the present invention. A plurality of CPUs 3 are connected to a switching mechanism section 2, which is connected to a system console typewriter 3 and a changeover switch 4. The switching mechanism section 2 includes a plurality of CPUs.

After receiving the data from ~13, it is sent to the system console typewriter 3, and the data from the system console typewriter 3 is transmitted to multiple CPUs,
It has a function of selecting any one of 13 to 13 and transmitting the data to the CPU. Also, selector switch 4
is multiple CPUs 1. It has a switch for specifying which CPU to select among the CPUs 1 to 13, and has a CPU selection function.

Furthermore, in addition to this function, the changeover switch 4 can also be provided with functions such as offline 1 online designation and test mode designation.

FIG. 2 shows a detailed configuration example of the switching mechanism section 2. As shown in FIG. Respective signal lines M-L3 connected to the plurality of CPUs 1s-13 shown in FIG. 1 are connected to data buffers 5o-53 corresponding to the CPUs. These data buffers 5 are connected to a common bus 11 connected to the control section 6.
This common bus 11 has an interface 7 connected to it.
and input designation decoding section 8 are connected. This input designation decoding section 8 is connected to a switching section 9 into which a signal from the changeover switch 4 is input.

Further, a signal from the switching section 9 is input manually to the switching section 10.

Next, the present invention will be explained in detail. The output data sent from each CPU 1o to 13 through each signal line M to L3 is temporarily stored in each data buffer 5o" 5a. The control section 6 controls the entire switching mechanism section 2. ,
The data stored in the data buffer 5 is output to the next system console typewriter 3, and a header (CPU identification A function is provided to add a symbol) to the beginning of the output data to the typewriter 3. ? The data stored in the data buffer 5 according to the commands of the JII E1 section 6 is transmitted to the system console typewriter 3 via the interface 7. This interface'l, AL CPU
An interface circuit equivalent to the I side interface circuit can be used. Note that regardless of the transfer control by the control unit 6,
Depending on the state specified by changeover switch 4, the corresponding C
Data from the data buffer of the PU can be output to the console typewriter 3 unconditionally. In this case, the input/output of the data buffer is controlled by the switching unit 9.10. C
There are various ways to control the order of output data from the PU, but for example, if a terminal character is attached to each character set, and this terminal character is determined by the control unit 6, it will be determined whether this terminal character is included or not. Output the contents of the data buffer 5 to the system console typewriter 3. After this output is completed,
A simple control method is to similarly output the contents of the data buffer 5 containing the next terminal character to the system console typewriter 3. It is assumed that the terminal character is defined by the system.

Next, select the specific CP from the system console typewriter 3.
The case of inputting data to the UI will be explained. First of all,
Select which CPU 1 you want to input data to by using the changeover switch 4. In this case, the signal from the changeover switch 4 is supplied to the input designation decoder 8 via the changeover section 9. Therefore, the CPUI specified by the changeover switch 4 is sent to the control section 6 via the input specification decoding section 8, and the control section 6 determines which CPUI is specified. The data from the system console typewriter 3 is transmitted via the data buffer 5 to the header.

During this holiday, in the case of input mode, the switching section 10f! :No intervention.

〔Effect of the invention〕

As described above, according to the computer device of the present invention, it is possible to connect a plurality of central processing units to one system console typewriter via the switching mechanism, thereby constructing an economical system console. I can do it.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing one embodiment of the present invention, and Figure 2 is a diagram showing the configuration of one embodiment of the present invention.
It is a detailed block diagram of the switching mechanism part shown in the figure. 1...CPU 2...Switching mechanism section 3...
・System console typewriter 4... Selector switch 5... Data buffer 6... Control section
8... Input designation decoding section 9.10... Switching section agent Patent attorney Noriyuki Chika (1 other person)

Claims (1)

[Claims] In a computer device having a plurality of central processing units, a system console typewriter is installed between the plurality of central processing units and one system console typewriter, and is used to temporarily store data from the plurality of central processing units. A data buffer corresponding to each of the receiving central processing units, and a data buffer for sequentially transmitting data from the data buffer to the system console typewriter, and data from the system console typewriter to the plurality of central processing units. a switching mechanism section having means for selecting any one of the central processing units and transmitting the data buffer data corresponding to the central processing unit; and means for specifying any one of the central processing units. A console device having a t-% sign that an intervening process is performed.