JPS5952294A - Liquid crystal driving system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal driving method for dynamically driving a liquid crystal display.

In general, the dynamic drive method for liquid crystal displays is:

LCD display? An AC voltage waveform (driving voltage waveform) of a predetermined level is supplied to the first and second electrodes in a time-sharing manner, and the lighting is turned on or off depending on the magnitude of the potential difference between the two electrodes. Bias - 1/3 duty, 1
There are drive systems such as /2 bias-172 duty.

However, in devices such as dot matrix displays that drive liquid crystals at high-order duty.

The operating margin is small, and the range of lighting voltages that can easily cause crosstalk, which causes a decrease in contrast, is 1. As shown by the shaded area in Figure 1, the area is extremely narrow. Therefore, is the drive voltage waveform unique? This is due to variations in the manufacturing process of liquid crystal displays (for example, if the thickness of the liquid crystal layer differs from product to product, its resistance component will also vary).

The driving voltage applied to the liquid crystal becomes biased toward the high potential side or the low potential side with respect to the optimum value of the liquid crystal (center voltage value of the shaded area in FIG. 1), and the luminance decreases accordingly.

In order to prevent this, conventionally, the level of the drive voltage waveform is changed by volume control, and the drive voltage applied to the liquid crystal is adjusted to the optimum value for that liquid crystal.

However, in this type of device, the N source voltage itself has to be changed, so it cannot be used in common with a single circuit power supply, and the power supply circuit becomes complicated.
There will be a lot of wasted current consumption.

In addition, external parts such as a volume are required.

Therefore, this kind of device is not suitable for small electronic devices such as 11J children's wristwatches.

This invention has been made based on the above-mentioned circumstances, and its purpose is to
A liquid crystal drive that digitally controls the duty of the drive normal pressure waveform supplied to the electrode and the second electrode to change the effective value of the drive voltage applied to the liquid crystal and match it to the optimum value for the liquid crystal. The purpose is to provide a method.

Hereinafter, this invention will be specifically explained with reference to FIGS. 2 to 6. This embodiment takes as an example a 1/3 duty liquid crystal drive system in which a small electronic device such as an electronic wristwatch is used and its liquid crystal display section performs matrix display according to a dynamic drive system. 1 in the figure is
This is a circuit for digitally creating a plurality of waveform signals with different duties.This creation circuit is composed of an n-ary counter 2 and a gate circuit 3.
is for counting the clock 1 signal of a predetermined frequency, and each bit output thereof is inputted to a gate circuit 3. This gate circuit 3 appropriately combines each bit output of the n-ary counter 2, and calculates the duty of the clock 1 signal. Multiple pulse signals aO~
Φ is applied to the data select circuit 5 which outputs an in parallel and opens the 1 selection circuit 4.

The selection circuit 4 is configured as follows.

That is, the manual switch 60 on operation signal (IJ OW of binary logic level) is a signal that opens the AND gate 8 via the inverter 7 .

This AND gate 8 outputs a predetermined frequency signal inputted thereto only while the block switch 6 is turned on, and its output is sent to the binary counter 9.
is given to and counted. This binary counter 9 receives a pulse signal a O% a n output from the gate circuit 3.
Count according to the number of! The counted value data is given to the data select circuit 5. This data select circuit 5 receives a pulse signal a output from the gate circuit 3.
It is configured to selectively output @-a n according to the count value data from the binary counter 9.

Therefore, the output of the data select circuit 5 is.

According to the count value of the binary counter 9, the pulse signal aO,
at, affi...am, ao...
...This is the signal.

On the other hand, the liquid crystal display 10 is a display having 10 rows and 10 columns, and performs an IJ lux display, although it is not shown in the drawings.

Ten 11th F poles (X electrodes) are disposed in the row direction, and ten second electrodes (X electrodes) are disposed in the column direction, facing each other. Then, the liquid crystal display body 10 is operated in synchronization with the driving normal pressure waveforms D1 to Dto supplied from the X electrode driving circuit 11 to the first electrode and the driving voltage waveforms D1 to l)+o. The drive voltage waveform 8egn supplied to the second 'i[i, pole from
It appears to be dynamically driven with a duty of 173 according to ent1-56gm6ntlO. In addition.

Both electrode drive circuits 11 and 12 will be described in detail later, but the X electrode drive circuit 10 receives scanning signals d1 to dso periodically output from the scanning circuit 13, a 32H2 signal with a 7-frame frequency,
According to the output of the data selection circuit 5, the actual voltage waveform]) 1 to D10'iff is generated and output, and the X electrode drive circuit 12 generates and outputs the 10-bit display output from the X electrode selection circuit 14. data data
Drive normal pressure waveforms Segment 1 to S6gment 10 are generated and output in accordance with the output of the data select circuit 5, which is a 32 Hz signal having a frequency of 1 to data 10%7V-A.

Next, referring to FIG. 3, the X electrode drive circuit 11, ie,
Only the circuit that outputs the drive voltage waveform IJ t and Segm6nt 1 'q is shown, and the other circuits are omitted because they have the same configuration as the circuit described above. First, X
The configuration of the electrode drive circuit 11 will now be explained.

The output from the data select circuit 5 is connected to the inverter 15.
The 32 Hz signal is applied to the AND gate 15 via the 32 Hz signal. This anime channel MO8
) are respectively supplied to the gate side of the transistor. One end of the P-channel MOS transistor of the CMOS inverter 17 has a four-level level of pressure, for example, Vo (O volts), Vl (-1,5yK#)), Vt (-3
7Kk) ), V4 (4.5 volts), H1
A voltage Vo, which is a voltage at the gh level, is applied, and N
Channel! MO8) A pressure ■1 is applied, and depending on the output e of the AND gate 16, the 'MUS inverter 17 outputs a voltage VO1V1'&switching output j.

'! r, =, the output e of the AND gate 16 is directly connected to the gate electrode of one of the pair of N-channel M (J8) transistors forming the selection gate 18.

In addition, the other gate electrodes are each supplied via an inverter 19. This selection gate 18 is constituted by the pair of MOS transistors and an inverter 19 connected in series, and one of the transistors, ie,
A voltage t is applied to one end of the transistor to which the output of the inverter 19 is supplied, and the other MOS)
One end of the transistor is stamped with a pressure 8.

Fourth, the output of the data select circuit 5 is the scanning signal d1.
They are also supplied to the Noah gate 20, respectively.

The output f of this NOR gate 20 is supplied to an exclusive OR gate 21 to which the output e of the AND gate 16 is input. The output of the exclusive OR gate 21 is then passed through the inverter 22 to the CMOS transmission gate 23.
Directly to the gate electrode of the P channel/l/Mush transistor constituting the transistor.

The voltage is supplied to the gate electrodes of the N-channel MUS transistors through inverters 22, respectively. CM 7-08) The transmission gate 23 is formed by joining the transistors O8) between the above and the P channel, and the output voltage Mol of the CMOS inverter 17 is applied to one junction point, and the output voltage Mol of the CMOS inverter 17 is applied to the other junction point. The junction point is connected to one end of the N-channel MOS transistor 24. Note that a voltage Vo as a substrate voltage is applied to the P-channel transistor O8). This M.O.
The exclusive OR gate 2 is connected to the gate of the S transistor 24.
1' is supplied, and the output voltage v23 taken out from the connection point of each MO8 transistor constituting the selection gate 18 is applied to the other end.

Then, a drive voltage waveform Dl is taken out from the connection point between the 0MO8) transmission gate 23 and the N-channel M(J8) transistor 24.

Next, the configuration of the Y[pole drive circuit 12 will be explained.

Note that the X electrode drive circuit 12 has substantially the same configuration as the X electrode drive circuit 11, and the same components are denoted by the same reference numerals aV and their explanations will be omitted. This X electrode drive circuit 12 is provided with a NOR gate 25 in place of the AND gate 16 of the X electrode drive circuit 11. The NOR gate 25 is directly inputted with the signal 32) (Z) and the output g delayed by one pulse of the signal 32H2 with respect to the output e of the AND gate 16. Moreover, the display data datal of the first bit is as follows.

The signal is supplied to the Noah game (20a) to which the signal is input. The output of this NOR gate 20a is supplied together with the output g of the NOR gate 25 to an exclusive OR gate 21a. Note that the other configurations are the same as the X electrode drive circuit.

Next, the operation of the above embodiment will be explained with reference to FIGS. 4 to 6. When the clock 1 signal of a predetermined frequency shown in FIG. 4 is input to the n-ary counter 2.

The n-ary counter 2 divides the frequency of the clock 1 signal.

@4 As shown in the diagram, pulse signals ao to aiY whose duty sequentially changes so that the pulse width is doubled are generated and output. In this case, manual switch b7 on operation j
Φ and the contents of the binary counter a while the manual switch 6 is turned on.

Since the step is performed according to the lock 2 signal outputted from the ANDCATE 8, the data select circuit 5 sends the pulse signals a O-a n in a predetermined order (i.e., aO, a!
......a! 1. aO...-...-...) is output continuously. Therefore, the output of the data select circuit 5 becomes a waveform signal whose duty becomes Iftiff. However, I was told to turn off manual switch 6.
According to the contents of the binary counter 9 at that time, the data select circuit 5 selects and outputs one type of waveform signal from among the pulse signals a O% a n.

In response to the output bfX of the data selection circuit 5, the X electrode drive circuit 11 and the Y electrode drive circuit 12 operate respectively. First, in the X electrode drive circuit 11,
The input signal is as shown in Figure 5! Assuming that the first HARLES information a1 is the output e of ANDKATE 15, the signal 32H2 is High as shown in FIG.
During the level, the signal becomes an inverted signal, and the rest is Low.
The level is sharp.

However, in CM (J8 inverter '17, signal e is LO
When the level is W, the P-channel MOS transistor is turned on, and when the level is I-l-1i, the N-channel MU8) transistor is turned on, so CM(J
8. The output voltage Vo+ of the inverter 17 is cc, 32'HZ (7) G, as shown in FIG.

The voltage waveform is such that Vl is output alternately. It's 1.

The selection gate 18 is an N-channel MO to which the output of the inverter 19 whose signal e is at a LOW level is supplied.
The S transistor was turned on. When the level is high, other N-channel MO8) transistors are turned on rL
Therefore, the output voltage Vex of the 1 selection gate 18 is the 51st”
zlK')K, the 32Hz signal is at the High level lh'1. The voltage waveform in which voltages Vg and Va are alternately output in synchronization with the @ sign is sharp.

Then, the output voltage Vot+X of the CMOS inverter 17
CMU S Applied to one end of the transmission gate 23, and the output voltage of the 1 selection gate 18■! 8 is applied to one end of the N-channel MOS transistor 24, and these voltages ot and Vgs are selectively output according to the output of the exclusive OR gate 21.

- "In other words, the scanning signal d1 shown in FIG.
When input to 0, the output f of the NOR gate 20 becomes as shown in the black diagram 5. The output of the exclusive OR gate 21 becomes a LOW level when both the signals f and e are at a HIGH level or a LOW level, and becomes a HIGH level in other cases. Therefore, the output of the exclusive OR gate 21 is L
When the signal is at OW level, &XCMUS transmission gate 23 is turned on, and when it is at High level, N-channel MOS transistor 24 is turned on.

As a result, the drive voltage waveform D1 becomes a duty voltage waveform according to the signal as shown in FIG.

Next, Yt Gokukou+? ! In the 11 circuit 12, the output g of the NOR gate 25 is at Low level while the signal of 32H2 is at -1i g h level, as shown in FIG.
Others are inverted signals of the signal d. Namely.

The signal g is delayed from the signal e by one pulse of the 32 Hz 0) signal. Therefore, the output voltage Vat of the CMUS inverter 17a and the output pressure Vgs% of the selection gates 12-18a are as shown in FIG. Then, the output voltage V o of the CMUS inverter 17a
t is applied to one end of the eMU 8) transmission gate 23 and called n. ^The output voltage vta of the selection gate 18a is N
A voltage P is applied to one end of the channel MOS transistor 24a, and each of these voltages VO.

Vl, Vg, and Vs are selectively output according to the output of exclusive OR gate 21a. That is, when the synchronized "fΦ indication data data datal is inputted to the scanning signal d1 as shown in FIG. 5, the output n of the NOR gate 20a becomes as shown in FIG. The result is a small change in the waveform.

As shown in FIG. 5, the drive voltage waveform 8egmentx becomes a duty voltage waveform according to the signal.

The drive voltage waveforms DI and Seg obtained in this way
When ment 1 is applied to the corresponding first and second electrodes of the liquid crystal display 10, the magnitude of the potential difference between the two voltage waveforms causes the IJ lux display element to light up for a predetermined value.
Become so.

Therefore, FIG. 6 shows the lighting and non-lighting waveforms of two types of drive voltage waveforms (drive voltage waveforms output from the X electrode drive circuit 11) with different duties, Dl, D
2 shows the lighting waveform, and DI' and D2' show the non-lighting waveform. The effective value ratios of these two types of lighting waveforms 1) 1, D2 and non-lighting waveforms D1', D2' are the same as shown in Figure 6, so in terms of operating margin, both drive voltage waveforms are Nothing will change if you ask. That is, the effective values of both drive voltage waveforms change without changing the operating margin.

Since this effective value changes according to the output of the data select circuit 5, the manual switch 6 is turned on to output each waveform signal a O% a from the data select circuit 5.
When m are sequentially output, the effective value of the drive voltage waveform changes sequentially. At this time, in the liquid crystal display 10, the display brightness changes according to the drive voltage applied to the liquid crystal.
The brightness changes like "bright→dark→bright". When the brightness is compared and the best brightness is reached, the manual switch 6 is turned off, and the liquid crystal display 10 will be driven at that brightness from now on. Even if the liquid crystal display body 10 varies from product to product, the drive voltage applied to the liquid crystal can be adjusted to the optimum value for the liquid crystal.

Furthermore, in the above embodiments, the manual switch may be externally operable so that the user can set the brightness to his or her desired level.

L-1 Although the above embodiment was applied to mounting a dot matrix display type liquid crystal display, the present invention is not limited to this.

As claimed in more detail, the present invention digitally controls the duty of the drive voltage waveform supplied to the first electrode and the second electrode constituting the liquid crystal display, and applies the waveform to the liquid crystal. Since the effective value of the drive voltage is changed to match the optimum value of the liquid crystal, it is possible to perform the adjustment without changing the power supply voltage, and it can be used in common with one circuit. At the same time, it is possible to prevent the complication of the ii source circuit, thereby eliminating wasted current consumption.

15-

[Brief explanation of the drawing]

Figure 1 is a conventional luminance characteristic diagram, Figures 2 to 6 are examples of the present invention, Figure 2 is an overall block circuit diagram, 3N is an X electrode drive circuit, Yw FIG. 4 is a diagram showing details of the electrode drive circuit. 51.1 is a waveform diagram of various signals, and FIG. 6 is a waveform diagram of a drive voltage applied to the liquid crystal. 1... Creation circuit, 4... Selection circuit, 10.
...Liquid crystal display body, 11...X electrode drive circuit,
12...Y electrode drive circuit. Patent applicant Casio Computer Co., Ltd. 16- Fig. 1, Horse ward dynamic voltage 0 + - ~ To town >>> 5 ζ (To JQ N + AC: 52oo o θ - (XJL'J Q OQ Q

Claims (1)

[Scope of Claim] A liquid crystal driving method in which a driving voltage waveform is supplied to a first electrode and a second electrode constituting the liquid crystal display, respectively, to dynamically drive the liquid crystal display. A creation means for digitally creating multiple types of pulse signals with different duties; a selection means for selectively selecting each pulse signal created by the creation means; and a selection means for selectively selecting each pulse signal created by the creation means; and control means for controlling the duty of the driving voltage waveform supplied to the first electrode and the second electrode, the driving voltage being applied to the liquid crystal according to the driving voltage waveform duty-controlled by the control means. A liquid crystal drive method that changes the effective value of the voltage and selects the optimal drive voltage for the liquid crystal.