JPS5951640A - Method for transmitting data between microcomputers - Google Patents

Abstract

PURPOSE:To check a transmission line at data transfer, by providing additionally a redundant bit after being defined for the data transfer between two microcomputers coupled loosely at an optional distance. CONSTITUTION:A start bit 2 and the 1st reply bit 3 are defined in advance as LOW and HIGH, a slave CPU outputs the start bit 2 and the echo is read while being outputted up to a data bit 4. If a failure takes place on a bus, since there appears a difference in an output data by bit 2 or 3, the slave CPU detects a data error, the CPU waits at a transfer wait routine, and after bit 4 is outputted, the process advances to the sampling of the data bus, and the CPU reads and fetches the data bit 5 and the 2nd reply bit 6. After the master CPU fetches a data up to the bit 4, the bit 5 is outputted and the CPU outputs the bis 6 at an LOW level, own interruption mask is released.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to systems that perform independent tasks at a distance from each other, such as an indoor unit and an outdoor unit that make up a room air conditioner, or a main body and a camera that make up a video tape recorder. However, the present invention relates to a data transmission method between microcontrollers that requires bidirectional data transmission and reception.

Conventional configuration and its problems Traditionally, the method of transmitting data between microcomputers has been serial transmission, which is economical because it saves the transmission data lines and the input/output terminals of the microcomputer. There are start-stop synchronization methods that wait for the transfer, and two-pass synchronization methods that have a transfer clock, and these are controlled by a program, using a dedicated LSI, or a microcomputer with a shift buffer for this purpose. There is.

However, in the start-stop synchronization method, which is the most common method for low-speed data transmission, the transfer direction of the 1-byte data sandwiched between the start bit and the stop bit is constant, making it possible to receive and receive mutual signals. To do so, the structure had the disadvantage of being extremely complex.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned drawbacks of the conventional art.
The number of data transfer lines between two microcomputers loosely coupled across the MII is minimized, the data transfer direction is defined on the time axis, and logical values are The objective is to improve the reliability of data transfer by adding two different definition bits.

Structure of the Invention To achieve this object, the present invention configures a system in which a plurality of microcomputers are connected by a single transfer data line, outputs and samples data at regular intervals, and detects abnormalities in the data bus. Two check bits with different logic values are added to detect the data, and an interrupt input terminal is used to synchronize the start of transfer to allow bidirectional data transmission between the microcomputer and the computer overnight. An internal timer is used for data transfer and sampling.

Description of examples An embodiment of the present invention will be described below with reference to the accompanying drawings.

First, the bit structure of transfer data will be explained with reference to FIG. In the figure, since all bits of the transferred data may be 0 or 1, abnormalities in the data bus cannot be determined by mere echo reading.

Therefore, start bit 2 and first reply bit 3
By defining LOW and HIGH in advance, the slave CPU first outputs start bit 2, and performs an echo read while outputting up to data bit 4. If a bus abnormality occurs here, a difference with the output data will appear in the start bit 2 or the first pass bit 3, so the slave CPU detects the data error and waits in the transfer wait routine. Furthermore, after outputting the data pin 4, the slave CPU moves to sampling the data bus, reads and captures the data bit 6 and the second reply bit 6. After the master CPU takes in data up to data bit 4, it outputs data bit 5, and finally the second
After outputting regri bit 6 to LOW, cancel its own interrupt mask. Last second glue bit 6
The slave CPU also checks its logical value, and if it matches a predefined value, it is determined to be a normal sequence.

In this way, by adding defined redundant bits, it is possible to check the transmission line during data transfer.

Effects of the Invention As is clear from the above embodiments, the present invention provides an excellent effect in that transmission lines can be checked during data transfer by adding defined redundant bits.

[Brief explanation of the drawing]

FIG. 1 is a bit explanatory diagram of transfer data in an embodiment of the present invention, and FIG. 2 is a timing diagram of the transmission data. 2... Start bit, 3... First reply bit, 4... Data bit, 5...
...Data bit, 6...Second reply bit.

Claims (2)

[Claims] (1) Connected to multiple microconbeaters, one common data line, and one common ground line, synchronization of transmission start controlled by interrupt input that can be masked by program, and data transmission It constitutes a serial data communication device whose direction is defined by the time axis, echo-reads output data for error checking of transmitted data, and
A data transmission method between microcomputers that adds two data bits with different logical values. (2) Connect two microcomputers with one common data line via a signal amplifier and a common ground line, and connect one microcontroller to one human power port to a long terminal that can mask interrupts. 2. The method for transmitting data between microcomputers as set forth in claim 1, wherein the base timers of each microcomputer are operated for the same length during the data transmission period.