JPS5951145B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static type semiconductor memory device.

Conventional static memory cells are composed of a circuit in which two inverters are cross-coupled, so the minimum number of elements required is four, and if you include the transmission gate that controls the writing and reading of information, there are five elements. elements are required.

On the other hand, a dynamic memory cell that requires refreshing requires a total of two capacitors for temporary storage and a transmission gate.
Since the static type is inferior to the dynamic type in terms of cell area, the chip area increases accordingly and the price is high, so its applications are limited. Therefore, an object of the present invention is to provide a static type semiconductor memory device with a small cell area by reducing the number of elements.

FIG. 1 is an equivalent circuit diagram of a two-element static memory according to the present invention.

In the figure, 1 is a MOS field effect transistor, and 2 is a bipolar transistor. Although N channel and NPN type will be described as examples, the same applies to P channel and PNP type. The drain 3 of the transistor 1 is connected to the positive potential VDD and is formed together with the source 4 in a P-type region 5, the source 4 being the same as the collector of the transistor 2, and the P-type region 5 being connected to the transistor 2. It is the same as the base of The emitter 6 of the transistor 2 is grounded. A fixed power supply 8 is connected between the gate 7 and the source 4 of the transistor 1, with the gate 7 having a more positive potential and a potential several volts higher than the threshold value VT of the transistor 1. In this state, if the source 4 is at the same potential as the drain 3, no current will flow between the drain and source. P-type region 5
Since no current is supplied from anywhere, transistor 2 is turned off. At this time, since a potential equal to or higher than the threshold value VT of the transistor 1 is applied to the gate 7 by the fixed power supply 8, the transistor 1 is in an on state, and the source 4 is kept at the same VDD potential as the drain 3. In this way, since transistor 1 is in the on state but transistor 2 is in the off state, a state in which no current flows is maintained. Next, when the source 4 is forced to the ground potential from the outside, the VDD potential is applied between the drain and source of the transistor 1, so that electrons run in the channel from the source to the drain. When VDD is high enough to form a high electric field near the drain, electrons coming from the source are accelerated and cause ionization collisions, generating electron-hole pairs. The holes thus generated forward bias the P-type region 5, turning on the transistor 2, and electrons are supplied from the emitter 6 to the collector 4, that is, the source 4 of the transistor 1. The electrons thus supplied are guided to the channel of the transistor 1 and again cause ionization collision near the drain, generating holes. As a result, current continues to flow from VDD to the ground potential through transistors 1 and 2. In this way, this memory device can stably take two states, one in which current flows and one in which current does not flow, so these states can be used as a storage device by corresponding to the logic "O" and "1" states. can. When current does not flow, source 4 is at VDD potential ("1" level), and when current flows, it is at a potential close to ground potential ("0" level), so it is memorized by detecting the potential of source 4. Information can be read. When the transmission gate that controls the writing and reading of information to and from the memory device of FIG. 1 is connected to the source 4, it becomes a memory cell, which is a complete unit of memory. In FIG. 2, a MOS type field effect transistor 30 is a transmission gate, and one end 9 of its source or drain is connected to the source 4 of the transistor 1, and the other end 10 is connected to an information line (bit line) 13. ing.

The gate 12 of transistor 30 is connected to a control line (word line) 14. Note that this figure shows a depletion type transistor 1 in which the gate and source are short-circuited and the drain and source are conductive even if the gate potential is the same as the source potential. As is clear from a comparison with FIG. 1, this method simplifies the circuit structure since it does not require a separate power source (power source 8 in FIG. 1). When a "1" level is applied to the control line 14 and the transistor 30, which is a transmission gate, is turned on, the information line 13 and the source 4 of the transistor 1 are connected, and the state of the memory cell, that is, the source 4 of the transistor 1 is changed. A voltage potential is sensed on information line 13 to read the information stored in the memory cell. In this case, the information line 13 is charged to the "L" level in advance, and then electrically isolated from the surrounding circuits.
Transmission gate transistor 3 remains charged at the "1" level due to the temporary memory effect caused by the parasitic capacitance of transistor 3.
0 is turned on, and the information line 13 becomes "1" according to the information in the memory cell, that is, the potential of the source 4 of the transistor 1.
A good method is to read by discharging and non-discharging the level of charge. That is, the source 4 of transistor 1 is "O"
If the source 4 of the transistor 1 is at the "L" level, the charges at the "1" level on the information line 13 are discharged to the ground potential through the transistor 2, but are held without being discharged. If the potential of the information line 13 is measured with the transmission gate transistor 30 turned on, it means that the information in the memory cell has been read. Note that to rewrite the information in the memory cell, the transmission gate transistor 30 is turned on, the information line is set to the "1" or "0" level, and the source 4 of the transistor 1 of the memory cell is forcibly set to "1". ”
Alternatively, this is done by setting it to the "O" level. Second
The specific structure of the circuit shown in the figure is shown in FIG. That is, P-type regions 5 and 11 are formed in the N-type semiconductor substrate 23, and N-type 1 drain region 16 and source region 18 are formed in the P-type region 5, and the metal electrodes 3 and 11 are formed in the N-type semiconductor substrate 23, respectively. 4 is connected. Substrate 23 between source and drain
A gate insulating film 17 and a gate electrode 7 are formed on the surface thereof. Directly below the source region 18, a P-type 1
N-type high impurity concentration region 6 across region 5 and substrate 23
is buried, the source region 18 is the collector, and P
Bipolar transistor 2 is constructed using type region 5 as a base and using high impurity concentration region 6 and substrate 23 as an emitter. Further, in the 2P type region 11, a drain or source region 19 or 21, a gate insulating film 20 and a gate electrode 12, a drain or source region 9 or 10 are formed, and a MOS type transistor 30 is configured (transistor 30 is a transmission gate;
Either 19 or 21 can be the source or drain depending on the operating state). As is clear from the above explanation, the source region 18 of transistor 1 is
The P-type region 5 is also the base that houses the transistor 1 and the base of the transistor 2. Gate and source electrodes 7 and 4 of transistor 1 are connected to source or drain electrode 9 of transmission gate transistor 30, forming the circuit shown in FIG. The high impurity concentration region 6 buried directly under the source 18 is provided to increase the efficiency of electron injection into the P-type region 5 serving as the base. Although the substrate 23 also acts as an emitter, its injection efficiency is low. The arrows in FIG. 3 indicate the direction of current flow.

Now, assuming that the source 18 has a value close to the ground potential, a channel current Ich flows between the drains 16 and 18.
Potential V applied to the drain electrode 3. When O is sufficiently high, electrons accelerated by the high electric field near the drain 16 cause ionization collisions and generate electron-hole pairs.

If the avalanche multiplication factor at this time is M, the current 1ch due to the electrons traveling from the source 18 becomes a current expressed as 10:MXIch when it reaches the drain 16, and the generated holes flow into the P-type region 5. The current flows and becomes the base current h of the transistor 2.

ID=Ich+h will be established, so from now on h=(M-1)×Ich There is a relationship.

If the current amplification factor of transistor 2 is HFE, collector current 1 flows between collector 18 and emitter 6. There is a relationship between IC:HFEXIB and the base current h.

The collector current 1 is sufficient for the source 18 to remain self-held at a value close to ground potential. must flow, and this condition is expressed in the form 10>Ich.

From now on, using the above relational expression, (M-1)XhFE〉1 It turns out that this relationship is necessary.

When the impurity concentration of the P-type region 5 is 1 x 1016 cm-3, the distance between the drain 16 and the source 18 is 10 μM, and the voltage applied to the drain 16 is about 10 V, a value of about M-1:0.1 is usually obtained. HFE of
If is a value of 10 or more, the potential of the source 18 is self-maintained close to the ground potential.

Furthermore, if the potential of the source 18 is close to that of the drain 16,
Ich is very small and the base current 1B becomes negligibly small, hence the collector current 1. becomes almost zero and the transistor 2 is turned off, so that the source] 8 is maintained at approximately the same potential as the drain 16. In this way, the information in memory is stored statically. Although the bipolar transistor 2 has been described using a vertical type in which the collector current flows in a direction perpendicular to the surface of the substrate 23, the above-mentioned conditions also apply to a lateral type in which the collector current flows in a direction parallel to the surface. HF that satisfies
If E is obtained, it can be used in the configuration of this invention.

In addition, in order to operate this device at as low a voltage as possible, it is sufficient to increase the avalanche multiplication factor M of the MOS transistor 1 at a low drain voltage. The depth of the diffusion layer may be made shallow to facilitate formation of a high electric field region near the drain. As described above, according to this invention,
A static memory device is composed of three elements including the transmission gate. Furthermore, since the bipolar transistor is formed without particularly increasing the area occupied by the MOS transistor, it corresponds to only two elements in terms of the area of the memory cell. In contrast, since conventional static memory cells require five elements, the present invention provides a significant reduction in cell area. And since a dynamic memory cell has two elements, this invention has made it possible to have an integration density that is almost the same as that of a dynamic memory. , 4K bit is the largest capacity for static data).
In addition, in the memory cell of the present invention, the memory holding current is the drain current of the MOS transistor 1, ID=Ic
h+IB, but since IB=(M-1)Ich and M-1K is about 0.1, it can be roughly regarded as Ich.

However, as explained with reference to FIG. 2, the information read speed is determined by the discharge speed of the charges stored in the information line 13, which depends on the collector current Ic, so the HFE of the bipolar transistor 2 is The conditions (M-l
)×HFE>l, if it is sufficiently larger than I.

This creates a margin for information, allowing high-speed information reading. That is,
The second advantage is that the charge on the information line can be discharged with a current larger than the memory holding current Ich, and the read speed is faster than the current consumption. This means that the present invention is suitable for large-capacity, high-speed reading. In this way, this invention is extremely useful industrially.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment in which a transmission gate is connected, and FIG. 3 is a sectional structural diagram of the embodiment of FIG. 2. 1...MOS type field effect transistor, 2.
...Bipolar transistor, 3...
Drain, 4... Source, 5...
P-type region, 6... Emitter, 7...
・Gate, 30...MOS type field effect transistor.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type is used as an emitter, a region of a second conductivity type formed in the substrate is used as a base, and a region of the first conductivity type formed in the base region is used as an emitter. A bipolar transistor whose collector is the collector; the collector of the bipolar transistor is the source, another region of the first conductivity type formed within the base region is the drain, and a gate insulating film formed between the source and drain; A first state in which no current flows between the drain and source, that is, collector and emitter; and avalanche multiplication in the vicinity of the drain due to the current flowing. and the resulting carriers of the second conductivity type are implanted into the base region, resulting in the transfer of the first conductivity from the emitter to the collector or source.
1. A semiconductor memory device characterized in that the semiconductor memory device is configured to self-maintain a second state in which the current continues due to the flow of a conductive type carrier. 2. The semiconductor memory device according to claim 1, wherein a high impurity concentration region of a first conductivity type is buried substantially directly under the collector or source region and across the base region and the semiconductor substrate. 3. Claims in which the channel between the source and the drain is a depletion channel that is in a conductive state even when no voltage is applied between the gate and the source, and the gate is electrically connected to the source. 1st
The semiconductor storage device described in 1. 4. The semiconductor memory device according to claim 1, wherein a transmission gate for controlling writing and reading of information is connected at one end to the source, that is, the collector. 5 A binary logic level is supplied through the transmission gate, forcing the source or collector to be at approximately the same potential as the drain or emitter, causing current to flow between the drain and source, or collector and emitter. 5. The semiconductor memory device according to claim 4, in which a non-existent state or a flowing state is written. 6 After a charge is stored at the other end of the transmission gate so that it has approximately the same potential as the potential applied to the drain, when the transmission gate becomes conductive, the charge at the other end of the transmission gate becomes the same as the potential applied to the drain. 6. The semiconductor memory device according to claim 5, wherein reading is performed depending on whether or not the source is discharged through the collector and emitter.