JPS5820148B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that supplies a reference voltage to a sense amplifier of a semiconductor memory device.

The development of high-sensitivity sense amplifiers is essential for the development of CCDRAM (random access memory in the form of a charge transfer device) or ITr/Ce# (memory element consisting of a charge storage section consisting of a depletion layer and a gate transistor) memory. Currently, these sense amplifiers include differential type sense amplifiers and flip-flop type sense amplifiers.

In the latter method, in order to distinguish the presence or absence of charge, it is necessary to generate a reference charge and input it to a flip-flop, and the present invention proposes this reference charge generation device.

In the semiconductor device of the present invention, a charge storage electrode is formed on a one-conductivity type semiconductor substrate via an insulating film, and gate electrodes are formed on both sides of the charge storage electrode via an insulating film, and a source is formed on the semiconductor substrate on both sides. The present invention is characterized in that a diffusion layer with a high impurity concentration of the opposite conductivity type is provided to serve as a drain region, which will be described in detail below with reference to the drawings.

FIG. 1 shows one element of a CCDRAM, in which 1 is a semiconductor substrate, 2 and 3 are field oxide films, 4 is an electrode for charge storage,
5 is a gate electrode, 6 is an insulating film, 7 is a diffusion layer that constitutes a bit line, and 8 and 9 are channel stop diffusion layers.

For writing in this memory element, a voltage is applied to the electrode 4 to form a depletion layer, a voltage of V or 0 is applied to the diffusion layer 7 according to 1 or 0 of the data to be written, and a voltage is applied to the electrode 5 to gate the gate. When opened, charges flow from the diffusion layer 7 into the depletion layer formed in the semiconductor substrate below the electrode 4 (1) or do not flow (0).

Writing is thereby performed, and when reading, the diffusion layer 7 is placed in a floating state and connected to the sense amplifier.
When the gate electrode 5 is opened and the voltage of the electrode 4 is changed to a voltage that reduces or does not create a depletion layer, the charge in the lower depletion layer of the electrode 40 (when 1 was written) enters the diffusion layer 7 and its Lower the potential.

This is sensed by the sense amplifier and produces a read output of 1.

On the other hand, if there is no charge below the electrode 4, the potential of the diffusion layer remains unchanged, which gives a read output of O.

However, in such a memory element, the volume of the diffusion layer 7 is quite large, and the amount of charge accumulated in the depletion layer of the lower substrate of the electrode 4 is quite small.

Therefore, even if the charge in the depletion layer enters the diffusion layer, the change in potential is extremely small, and the sense amplifier must sensitively detect this minute change in potential.

An example of such a flip-flop type sense amplifier SA is shown in FIG. 2, in which two switching transistors Qt and Q2 are flip-flops, Q3 . Q4 is a transistor that serves as a load resistance.

is the potential of transistors Q1.7A and 7B. Q2 vt
The transistor Q6 provided to maintain the voltage at or above h is a reset transistor.

7A and 7B are the aforementioned diffusion layers, and transistor Q
1 and the gate of Q2, and the transistor Q
It is connected to the drain of Q2 and the gate of Ql.

M is a memory element, and in the case of a CCDRAM type element, it is composed of the aforementioned storage electrode 4, gate electrode 5, and the like.

Note that these memory elements M and sense amplifiers SA are formed on a common semiconductor substrate, and only one bit of each of a plurality of words is shown; in reality, a large number of such elements are arranged.

When reading, first the transistor Q6 is turned on to make the potentials of both diffusion layers 7A and 7B the same, and then the transistor Q6 is turned off and the gate 5 corresponding to the bit of a word is opened, and the electrode 4 is turned on. The potential of
to cause the charge to flow out to the diffusion layer, for example 7A (when 1 is written).

This lowers the potential of the diffusion layer 7A (when the charge is electrons), turning on the transistor Q1 of the sense amplifier and turning on the transistor Q2.
is turned off and a readout of 1 is obtained.

However, when 0 is written, no charge flows into the diffusion layer 7A even if the gate 5 is opened, and therefore, in the sense amplifier SA, which is a flip-flop, Ql.
Which transistor of Q2 is turned on is uncertain, and due to differences in characteristics during manufacturing, one of them will be turned on and O
The read output will be extremely unstable.

To avoid this, it is better to use differential cellular.

Reference numeral 10 in FIG. 2 indicates this differential cell, which is connected to the diffusion layers 7A and 7B on both sides, and when reading, the charge smaller than the accumulated charge for data 1 (hereinafter referred to as 0.5 charge) is connected to the diffusion layers 7A and 7B on the opposite side. Supply to the diffusion layer.

In this way, for example, when the memory element connected to the diffusion layer 7A supplies the accumulated charge amount corresponding to data 1 to the diffusion layer during reading, the differential cell 107 connected to the diffusion layer 7B on the opposite side , 5 are supplied to the diffusion layer, and as a result, the diffusion layer IA side becomes a low potential and the diffusion layer 7B side becomes a high potential by a potential difference corresponding to the charge amount of 0.5, turning on the transistor Q0 and turning off the transistor Q2. Become.

Further, when the memory element is written with data O and no charge is supplied to the diffusion layer 7A during reading, the potential of the diffusion layer 7A remains unchanged, whereas the diffusion layer 7B is charged from the differential cell. A charge amount of 0.5 is supplied, resulting in a low potential, and a potential difference corresponding to the charge amount of 0.5 is generated in both diffusion layers, turning on the transistor Q2 and turning off the transistor Q1.

When the memory element on the diffusion layer 7B side is read, the differential cell on the diffusion layer TA side supplies a charge amount of 0.5, and a similar read operation is performed.

In this way, by using the differential cell, the flip-flop SA can be operated reliably, and the data 1
, 0 can be read accurately.

The present invention proposes a structure of a differential cell that generates a charge amount of 0.5, that is, a reference charge.

FIG. 3 shows an embodiment of the invention.

In this figure, 11 is a P-type silicon semiconductor substrate, 12a
, 12b is an N-type diffusion layer formed inside the substrate, 13 is an insulating film such as a 5i02 film deposited on the surface of the substrate, and 14a.

14c and 14b are gate electrodes and charge storage electrodes made of polysilicon embedded in the insulating film 3.

The diffusion layer 12a is connected to either point (2) or (2) of the 7 lip-flop shown in FIG. 2, and the diffusion layer 12b is grounded.

FIG. 4 shows the voltages at each terminal a, b, c in FIG.

Next, referring to FIG. 3, the operation of the apparatus shown in FIG. 2 will be explained.

In this device, a positive voltage is applied to terminal a at t1°t before and after operation.
b and electrode 14a.

Depletion layers are generated within the lower substrate 11 of 14b, and charges (electrons) are stored in these depletion layers.

Next, as shown at time t2 in FIG. 4, when the voltage applied to terminal a is set to 0 and the voltage applied to terminal C is set to positive voltage, a depletion layer is generated in the lower substrate 11 of the electrode 14c. The lower part of the charge storage electrode 14b and the diffusion layer 12a are communicated with each other.

Next, at time t3, the voltage of the electrode 14b is set to O, and the charge under the electrode is moved to the diffusion layer 12a.

The amount of this charge is 0.5 as described above, and this can be adjusted by the area of the electrode 14b and/or the voltage applied to the electrode.

As is clear from a comparison with FIG. 1, this reference charge generating device can be manufactured in the same process as a CCDRAM element, and is extremely advantageous in manufacturing a memory.

Note that the voltage applied to the terminals is not limited to the rectangular voltage shown in FIG. 3, and may be a DC voltage.

As explained in detail above, according to the present invention, the CCDRA
To provide a semiconductor device, that is, a differential cell, which can reliably supply a reference voltage as desired to a flip-flop type sense amplifier of an MO8 type semiconductor memory such as M or I Tr /Cel, and can be manufactured in the same process as a memory element. be able to.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a CCDRAM element, FIG. 2 is an explanatory view showing a part of a storage device using the memory element of FIG. 1, and FIG. FIG. 4 is a diagram showing the waveform of the driving voltage. In the drawing, 11 is a semiconductor substrate, 14b is a charge storage electrode, and i4
a and 14b are gate electrodes, and 12a and 12b are diffusion layers.

Claims (1)

[Claims] 1-A charge storage electrode is formed on a conductive type semiconductor substrate via an insulating film, and gate electrodes are formed on both sides of the charge storage electrode via an insulating film, and opposite conductive electrodes are formed on the semiconductor substrate on both sides to serve as source and drain regions. What is claimed is: 1. A semiconductor device for supplying a reference voltage for sense-up of a semiconductor memory device, characterized in that a diffusion layer with a high impurity concentration is provided.