JPS59502090A - Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ - Google Patents

Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ

Info

Publication number
JPS59502090A
JPS59502090A JP59500090A JP50009084A JPS59502090A JP S59502090 A JPS59502090 A JP S59502090A JP 59500090 A JP59500090 A JP 59500090A JP 50009084 A JP50009084 A JP 50009084A JP S59502090 A JPS59502090 A JP S59502090A
Authority
JP
Japan
Prior art keywords
input
output
port
arbiter
character
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59500090A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0253983B2 (enExample
Inventor
クラ−ク・ベツキ−・ジエ−ン
Original Assignee
バロ−ス・コ−ポレ−ション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by バロ−ス・コ−ポレ−ション filed Critical バロ−ス・コ−ポレ−ション
Priority claimed from PCT/US1983/001803 external-priority patent/WO1984002239A1/en
Publication of JPS59502090A publication Critical patent/JPS59502090A/ja
Publication of JPH0253983B2 publication Critical patent/JPH0253983B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP59500090A 1982-11-23 1983-11-18 Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ Granted JPS59502090A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US443967 1982-11-23
PCT/US1983/001803 WO1984002239A1 (en) 1982-11-23 1983-11-18 Speed independent arbiter switch employing m-out-of-n codes

Publications (2)

Publication Number Publication Date
JPS59502090A true JPS59502090A (ja) 1984-12-13
JPH0253983B2 JPH0253983B2 (enExample) 1990-11-20

Family

ID=22175583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59500090A Granted JPS59502090A (ja) 1982-11-23 1983-11-18 Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ

Country Status (1)

Country Link
JP (1) JPS59502090A (enExample)

Also Published As

Publication number Publication date
JPH0253983B2 (enExample) 1990-11-20

Similar Documents

Publication Publication Date Title
Grover Quantum mechanics helps in searching for a needle in a haystack
US5548775A (en) System and method for adaptive active monitoring of high speed data streams using finite state machines
EP0109850B1 (en) Speed independent selector switch employing m-out-of-n codes
EP0104802A2 (en) Five port module as a node in an asynchronous speed independent network of concurrent processors
US4481623A (en) Speed independent arbiter switch employing M-out-of-N codes
Lehmann On a theorem of Bahadur and Goodman
JPS58502071A (ja) プロセッサの並行ネットワ−クにおけるセレクタ・スイッチ
JPS63129425A (ja) デ−タ処理装置
US4475188A (en) Four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors
US6700825B1 (en) Implementation of a multi-dimensional, low latency, first-in first-out (FIFO) buffer
Chang et al. A group testing problem on two disjoint sets
EP1355319B1 (en) Content addressable memory system
JPS59502090A (ja) Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ
Moore et al. Counting distinct strings
Dijkstra The distributed snapshot of KM Chandy and L. Lamport
US10719387B2 (en) Memory interface with tamper-evident features to enhance software security
US5257385A (en) Apparatus for providing priority arbitration in a computer system interconnect
JP3013800B2 (ja) 非同期ｆｉｆｏ回路
Georgescu et al. A New Approach to Communicating X-Machine Systems.
Heubach et al. Avoidance of partially ordered patterns in compositions
Moravec Fully interconnecting multiple computers with pipelined sorting nets
JPS58501788A (ja) バス装置
Denton Methods of computing deque sortable permutations given complete and incomplete information
Yoeli et al. Behavioral equivalence of concurrent systems
US3092807A (en) Check number generator