JPS59502050A - Vertical integrator circuit for TV and its time constant adjustment circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] TV divider circuit and horizontal oscillator Background of the invention TECHNICAL FIELD The present invention relates generally to TV systems, and more particularly to corresponding the current or amount of current used to trim the horizontal oscillator TV vertical with precisely defined characteristics by drawing part from it Regarding integrator circuits.

It is common knowledge that horizontal oscillators in TV systems must be accurately adjusted. It is knowledge. For example, the application was filed on December 29, 1980 under the title “1 Horizontal Oscillator”. is assigned to the assignee of this invention, the teachings of which are incorporated herein by reference. In the horizontal oscillator described in pending U.S. Application No. 220,606, Ha, capacitive Hiroga! l) (capacitivezpr　a　ad　) is This is corrected when the oscillator is trimmed by an external resistor network, which Set the standard current. resistance without further adjustment of the associated vertical integrator characteristics. can be precisely defined by the current or part of that current set by the network. That is desirable.

Summary of the invention The object of the invention is to provide an improved horizontal oscillator and vertical integral for use in TV systems. It is to provide a vessel.

Another object of the present invention is to provide reference current adjustment in associated horizontal oscillators. Therefore, by providing a method and apparatus for adjusting the time constant of a TV vertical integrator circuit. be.

Yet another object of the present invention is to provide a TV horizontal oscillator and corresponding Apparatus and method for correcting capacitive widening of both vertical integrators are provided. I'm whispering.

According to a broad aspect of the invention, a capacitive network is alternately charged and discharged, and its node Used with an oscillator circuit that is trimmed by a reference current set at the An improved vertical integrator circuit of the type described above is provided, which improves the oscillator and a current mirror coupled between the integrator and the reference current; Current is drawn from the integrator to set the time constant of the capacitive network.

According to another aspect of the invention, the node is alternately charged and discharged. type used with non-oscillator circuits, trimmed by a reference current set by A method is provided for setting the time constant of the integrator circuit.

The method includes generating a current signal representative of the reference current and from the integrator. including deriving the current signal and setting the time constant.

The above and other objects, features and advantages of the present invention will be apparent from the accompanying drawings. It will be more clearly understood from the detailed description below.

Brief description of the drawing FIG. 1 is a schematic diagram of a well-known horizontal oscillator.

FIG. 2 is a schematic diagram of an eight-way vertical integrator circuit.

Figure 3 is a schematic diagram showing a circuit that couples the horizontal oscillator of Figure 1 to the integrator of Figure 2. When the oscillator is trimmed at 92, it produces a reference current, a portion of which also comes from the integrator. pulled out to set its time constant without further adjustment.

Description of the preferred embodiment FIG. 1 is a schematic diagram of one example of a horizontal oscillator for use with the present invention. This issue The oscillator is an on-chip nitride capacitor 10 coupled between nodes 12 and 14. including.

This circuit consists of a bias chain consisting of resistors 1/), 18, 20 and 22, a die Turnaround circuit consisting of ode 24 and transistor 26, transistor 2 a first comparator including transistors 8 and 30; a second comparator including transistors 62 and 34; .

Current source, transistor, including transistors 36 and 38 and resistors 40 and 42 Reference amplifier, current mixer including resistors 44, 46 and 48 and resistors 50 and 52 transistors 54 and 56. and transistors 58, 60 and 62 and a lower current mirror circuit including resistors 64, 66, 68, 70 and 72. nothing.

Reference amplifier transistor 44 has its base electrode connected to the bias voltage at the node. Match. Therefore, when transistors 44 and 46 are perfectly matched, zero temperature A precise reference voltage having a number is developed at node 76. Next, the accurate reference current (JR ) is set by an external resistor network (represented by resistor 78). standard The current IR is selected to compensate for the capacitive widening of the oscillator.

The base of transistor 48 is coupled to the collector of transistor 44. to Transistors 48, 54 and 56 have their respective base and emitter electrodes together. are coupled to each other, so the current generated in each of their collector electrodes is approximately Almost equal. Gain of the lower current mirror circuit (transistors 58, 60 and 62) , the current through transistor 58 is much larger than the current through transistor 56. If the input current is larger, current will be drawn from the capacitor 10 and the output signal line will be (rnrphp).

This condition exists when the lower mirror circuit has a high gain. As the gain decreases, The current flowing through transistor 58 is smaller than the current flowing through transistor 56. , this difference flows into capacitor 10 creating the upward portion of the output ramp.

Finally, transistor 80 along with resistors 82 and 84 connect nitride capacitor 10 Provides temperature correction for Capacitor 86 is coupled to the base of transistor 46 represents a leaky capacitor.

For a thorough explanation of the operation of the horizontal oscillator shown in FIG. See pending patent application. Here, this oscillator sets the reference current IR appropriately. Suffice it to say that it is trimmed by selecting.

Separates the vertical sync pulse from a composite signal that combines horizontal and vertical sync pulses. An example of an integrated circuit for this purpose is shown in FIG. Always conductive PNP) run The emitter of the first current source, such as transistor TI, is connected to conductor 88 (Vaa ) is combined with The base of transistor T1 is connected to conductor 8 by diode D. It is connected to 8. The collector of transistor T is coupled to conductor 90, which creates a first current path to the current mirror circuit 92. PNP that is always conductive) The emitter of the second current source, such as transistor T2, is connected to conductor 88 by resistor R2. , whose base is coupled to the base of transistor T1. Tran The collector of transistor T is coupled to conductor 94, which is the first input to current mirror circuit 92. Creates two current paths. The emitter of transistor T is connected by limiting resistor R3. and is adapted to receive a signal that is integrated by a signal. Capacitor 96 is connected to conductor 90 and 94, and thus between the collectors of the first and second current sources T1 and T, combined. A current mirror circuit 92 has a collector coupled to conductor 90 and a large An NPN transistor T3 with its emitter coupled to a reference potential such as ground include. The current mirror circuit also includes series-connected NPN) transistors T4 and T. The collector of included shear transistor T4 is coupled to conductor 94 and its emitter The collector of transistor T, is coupled to the collector of transistor T, and the collector of transistor T, is connected to It is grounded. The base of transistor Tll is connected to the emitter of transistor T. It is also coupled to the base of transistor T. Transistor T4 The base of T3 is coupled to conductor 90 and thus to the collector of transistor T3. ing.

The potential at point A is a variable bias slicer amplifier including transistors T6 and Tf. Applied to the width gauge. Transistor T6 has a collector coupled to collector 88, point Base coupled to A, inviting resistor R? is connected to pin 98 by These capacitors and resistors may be external. Capacitor 100 and resistor R0 are connected in parallel between ground and pin 98. Transistor T? Is that this? a conductor 88 by a load resistor R6, and its base connected to a transistor T. 6 and the emitter is coupled to pin 98. transition The transistors T6 and rq constitute a Darlington type amplifier, and the transistors T6 and When T7 conducts due to the positive voltage at the base of transistor T6, the capacitor 100 is charging. The charge on capacitor 100 gives slice level V8, and V8 is the magnitude of the voltage at the base of transistor T6 and transistors T6 and T? is determined by the time during which the current is in a non-conducting state.

The time constant of resistor R0 and capacitor 100 seems to be longer than that between vertical pulses. should be adjusted to Therefore.

The charge on capacitor 100 decreases only slightly between vertical sync pulses. Conde The variable bias provided by the charge on sensor 100 is the magnitude of the voltage at point A. The magnitude of this voltage is in turn determined by the strength of the signal reaching the TV receiver. Therefore, it is determined. Therefore, the slice level V8 of amplifiers T6 and T7 receives determined by the strength of the signal. Slice level V8 is vertical for strong signals It should occur in the middle of the pulse height and give excellent impulse noise performance. The vertical pulse should increase in the direction of the chip as the input signal decreases. .

The output of the slice amplifier is applied to the base of the inverting amplifier transistor T8, which Transistor T, has its emitter coupled to conductor 88 and its collector in series. It is grounded through connected resistors R4 and R. Separated vertical sync pulse The current appears at output terminal 102 at the junction of resistors R4 and R6. In Figure 2 A detailed description of the operation of the integrator shown in FIG. An integrator circuit for separating one vertical sync pulse, the teachings of which are mentioned here for reference. Pending U.S. Patent Application No. 220,614, dated December 29, 1980, entitled Please refer to the issue.

As mentioned above, in order to set the time constant of the vertical equinox, the horizontal oscillator It is desirable to use the same reference current JR or a portion thereof. This is the first Disconnect the IR or a portion thereof from the concentrator by disconnecting the connections between nodes 14 and 76 in the diagram. This can be achieved by placing a current mirror circuit between them. this thing can be achieved as shown in FIG. 3, where dashed block 10 4 includes a part of the oscillator, which partially includes the circuit already described, and the dashed block 10 6 includes part of an integrator, which also includes the circuits already described. Figure 1 and the circuitry in blocks 104 and 106 previously described in connection with FIG. The reason given is that the integrator time constant can be set by a known circuit and a suitable choice of IR. This is to show the correct structural relationship between the additional circuitry and the

Referring to the oscillator circuit of FIG. 6, the current mirror circuit includes transistors 108 and 110 included. The emitters of these two transistors 108 and 110 are coupled to node 76 via resistors 112 and 114, respectively. transition The collector of transistor 108 is connected as well as the pace terminals of transistors 108 and 110. It is coupled to node 14 .

As is well known, transistors 10B and 110 or resistors 112 and 114 or can be applied to a given part of the IR by appropriately scaling some combination of these values. can be caused to flow into the collector of transistor 110. Of course Tori Not only must it be assigned to JR as a timing current, but it must also be distributed by mirror elements. Corrections must also be made for the additional current required.

Referring to block 106, which represents a portion of the vertical integrator circuit, as shown in FIG. Diode D was removed and replaced with resistor 116 and PNP. ) A beta-corrected current mirror circuit including transistors 118 and 120 is used. There is. The collector of transistor 120 is grounded.

Its emitter is coupled to the pace of transistor T□ and 118. Tiger The emitter of resistor 118 is coupled to conductor 88 (Vo.) through resistor 116. It is. 2 collector of transistor 110 in the oscillator to complete the circuit is coupled to the collector of transistor 118 and is also coupled to the collector of transistor 12 in the integrator. 0 base. By this method, transistors T□ and rt (See Figure 2) can control the current flowing to the collector of the IR It can be set with just one adjustment. This technique has a high degree of tying for vertical pulses. TV systems that require high precision in timing, such as Teletext and VIR5. Especially applicable.

The above explanation is merely given as an example. A person skilled in the art will understand that it is beyond the scope of the invention. Changes in form and detail can be made without.

Tour rG, -1 Translation submission form of the Ministry of Correction (Article 184, Paragraph 7, Paragraph 1 of the Patent Law) 1. Viewing patent applications International application number PCT/USB31015372, title of invention TV integrator circuit and horizontal oscillator 3. Patent applicant Address: 60196, Illinois, USA. Shambab.

1303 Motorola Inn Coholated Representative: Rauner, Vincent G.I. Nationality: United States of America Country 4. Agent Address: January 23, 1984, 2-5-2 Minami-Nagasaki, Toshima-ku, Tokyo The scope of the claims 1. (Correction) The capacitive network is alternately charged and discharged.

with a horizontal oscillator trimmed by a reference current set at that node. In an improved vertical integrator circuit of the type used in.

coupled between the oscillator and the integrator and representing the reference current; draws a current from the integrator proportional to and sets the time constant of the capacitive network. A vertical integrator circuit characterized in that it comprises: a current mirror;

2. The integrator is.

with a capacitor.

a first current source that discharges the capacitor;

a second current power source that charges the capacitor;

At least the first. a second current path coupled to the first and second current sources, respectively; a first current mirror circuit with a A circuit according to claim 1.

3. The horizontal oscillator has a connection between the output of the oscillator and the reference voltage generated therein. 3. A circuit according to claim 2, comprising a combined capacitor.

4. The current mirror circuit.

a second current mirror circuit coupled to the node and the capacitor.

coupled between the second current mirror circuit and the first and second current sources; a third current mirror circuit receiving a current representing a quasi-current from the second current mirror; 7. A circuit according to claim 6 comprising:

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Claims (1)

[Claims] 1. A capacitive network is alternately charged and discharged to meet the set base at that node. For vertical integrator circuits used in conjunction with oscillator circuits trimmed by quasi-currents. Stay. coupled between an oscillator and an integrator to draw a current from said integrator representing a reference current; a current mirror for setting the time constant of the capacitive network by setting the time constant of the capacitive network; vertical integrator circuit. 2. The integrator is. with a capacitor. a first current source that discharges the capacitor; a first current mirror circuit coupled to each of the two current sources; A circuit according to claim 1. 3. The horizontal oscillator has a connection between the output of the oscillator and the reference voltage generated there. 3. A circuit according to claim 2, comprising a combined capacitor. 4. The current mirror circuit. a second current mirror circuit coupled to the node and the capacitor. coupled between the second current mirror circuit and the first and second current sources; a third current mirror circuit that receives a current representing a quasi-current from the second current mirror; A circuit according to claim 3 comprising: 5. The second current mirror circuit. With the first resistance. With the second resistance. Base and collector terminals are coupled to the capacitor. a first transistor having an emitter terminal coupled to the node via the first resistor; and. A base is coupled to the capacitor and an emitter is coupled to the node through the second resistor. a second transistor coupled to the third current mirror circuit and having a collector coupled to the third current mirror circuit; including A circuit according to claim 4. 6. According to claim 5, wherein the oscillator is a horizontal oscillator of a TV system. circuit. 7. The integrator is used before separating the horizontal and vertical sync pulses in the TV system. A circuit according to claim 6. 8. a first current mirror coupled to the oscillator and regenerating a portion of the reference current; coupled to an integrator and the first current mirror circuit to derive the reference current from the integrator; and a second current mirror circuit for setting the time constant of the integrator. Contains a capacitive network that alternately charges and discharges the reference set at the node Time constant of an integrator circuit of the type used with a current trimmed oscillator A circuit that adjusts the. 9. Generate a current signal representing the reference current and “draw said current signal from the integrator. including setting the time constant. It is alternately charged and discharged and triggered by the reference current set at that node. Sets the time constant of an integrator circuit of the type used with a humming oscillator circuit. Method.