JPH0444869B2 - - Google Patents

Description

Claim 1: A vertical integrator circuit comprising a first _T1 and a _second T2 current source for alternately charging and discharging capacitive networks 92, 96, having an internal circuit node 76 to which a reference current I _R is set. The circuit node 76 and the first and second current sources are connected to an oscillator to set a time constant of the capacitive network.
T ₁ , T ₂ , said current mirror circuit draws a reference current corresponding to the reference current I _R set in the oscillator and flowing through the current mirror circuit means 108, 110, 116, 118, 120. Vertical integrator circuit for TV characterized by means.

2. The vertical integrator circuit includes: a capacitor; a first current source that discharges the capacitor; a second current source that charges the capacitor;
and a first current source coupled to a second current source, respectively.
A vertical integrator circuit for a TV according to claim 1, comprising a current mirror circuit.

3. A vertical integrator circuit for a TV according to claim 2, wherein said oscillator comprises a capacitor coupled between the output of said oscillator and a reference voltage developed thereon.

4. The current mirror means includes: a second current mirror coupled to the node and the capacitor;
and a third current mirror circuit coupled between the second current mirror circuit and the first and second current sources, the third current mirror circuit receiving a current representative of the reference current from the second current mirror circuit. 4. The vertical integrator circuit for TV according to claim 3, comprising a current mirror circuit.

5. The second current mirror circuit includes a first resistor, a second resistor, a second resistor having a base and a collector terminal coupled to the capacitor, and an emitter terminal coupled to the node via the first resistor. a second transistor having a base coupled to the capacitor, an emitter coupled to the node via the second resistor, and a collector coupled to the third current mirror circuit; A vertical integrator circuit for TV according to claim 4.

6. The vertical integrator circuit for TV according to claim 5, wherein the oscillator is a horizontal oscillator of a TV system.

7. A vertical integrator circuit for a TV as claimed in claim 6, wherein the vertical integrator circuit separates horizontal and vertical synchronization pulses in a TV system.

8. A circuit for adjusting the time constant of an integrator circuit of the type comprising capacitive networks 92, 96 alternately charged and discharged from a first _T1 and _{a second} T2 current source, said integrator The circuit is used in conjunction with an oscillator circuit that sets a reference current _I a first current mirror circuit 108, 110 that generates a representative current of the reference current at the collector of the reference current;
and coupled to the first T ₁ and second T ₂ current sources of the integrator and the output of the first current mirror circuit to set a time constant of the integrator circuit;
A time constant adjustment circuit for a vertical integrator circuit for TV, comprising second current mirror circuits 118 and 120 that draw out the representative current of the reference current from the integrator.

BACKGROUND OF THE INVENTION The present invention generally relates to television equipment (TV
system), and more specifically, the adjustment (trim, trim) of the connected horizontal oscillator.
The present invention relates to a vertical integrator circuit for TVs and its time constant adjustment circuit, the characteristics of which are precisely defined by drawing the current, or a portion of that current, used to do so.

It is well known that horizontal oscillators in TV systems must be precisely calibrated. See, for example, U.S. Pat. In the horizontal oscillator described, capacitive spreading (dispersion, capacitive
The spread is compensated when the oscillator is trimmed by an external resistor network, which sets an accurate reference current. It would be desirable if the characteristics of the connected vertical integrators could be precisely defined by the current or part of that current set by the resistor network without further adjustment.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved TV vertical integrator circuit and its time constant adjustment circuit for use in a TV system.

Another object of the invention is to provide a time constant adjustment circuit for a vertical integrator circuit for TV by means of reference current adjustment in a connected horizontal oscillator.

Yet another object of the invention is to compensate for the capacitive spread (dispersion) of both the TV horizontal oscillator and the vertical integrator connected to it with only one adjustment.
The present invention provides a vertical integrator circuit for TV and its time constant adjustment circuit.

In accordance with a broad aspect of the invention, an improved vertical integrator circuit of the type used with an oscillator circuit in which a capacitive network is alternately charged and discharged and trimmed by a reference current set at its nodes. is provided, the improved vertical integrator circuit including current mirror means coupled between said oscillator and said integrator to draw a current representative of said reference current from said integrator and to draw a current from said capacitive Set the time constant of the network.

According to another aspect of the invention, the time constant of an integrator circuit of the type used with an oscillator circuit that is alternately charged and discharged and trimmed by a reference current set at its node is set. A circuit is provided, the adjustment circuit including generating a current signal representative of the reference current and extracting the current signal from the integrator to set the time constant.

The structure of the present invention is as shown below. That is,
The present invention is directed to a vertical integrator circuit comprising a first T ₁ and a second T ₂ current source that alternately charges and discharges capacitive networks ₉₂ , 96. The circuit node 76 and the first and second current sources are connected to each other to set a time constant of the capacitive circuit network.
T ₁ , T ₂ , said current mirror circuit draws a reference current corresponding to the reference current I _R set in the oscillator and flowing through the current mirror circuit means 108, 110, 116, 118, 120. Alternatively, the vertical integrator circuit comprises: a capacitor; a first current source discharging the capacitor; and a first current source discharging the capacitor. a second current source for charging, and at least the first and second current paths connected to the first current source;
and a first current source coupled to a second current source, respectively.
a current mirror circuit; or, the oscillator includes a capacitor coupled between the output of the oscillator and a reference voltage generated therein. or, the current mirror means is configured as a vertical integrator circuit for a TV, or the current mirror means includes a second
and a third current mirror circuit coupled between the second current mirror circuit and the first and second current sources, the third current mirror circuit receiving a current representative of the reference current from the second current mirror circuit. or, the second current mirror circuit includes a first resistor, a second resistor, and base and collector terminals. a first transistor coupled to the capacitor and having an emitter terminal coupled to the node via the first resistor; a first transistor having a base coupled to the capacitor and an emitter coupled to the node via the second resistor; and a second transistor whose collector is coupled to the third current mirror circuit.
Alternatively, the oscillator is a horizontal oscillator of a TV system.
The vertical integrator circuit is configured as a TV vertical integrator circuit, or the vertical integrator circuit is configured as a TV vertical integrator circuit that separates horizontal and vertical synchronization pulses in a TV system. Alternatively, the invention provides a circuit for adjusting the time constant of an integrator circuit of the type comprising capacitive networks 92, 96 which are alternately charged and discharged from a first _T1 and a _second T2 current source. The integrator circuit is used in conjunction with an oscillator circuit that sets a reference current I _R at the oscillator circuit node 76, and connects the input (collector, base of 108) to the oscillator circuit node 76 through which the reference current flows. a first current mirror circuit 108, 110 that is coupled to generate a representative current of the reference current at its output (collector of 101);
and coupled to the first T ₁ and second T ₂ current sources of the integrator and the output of the first current mirror circuit to set a time constant of the integrator circuit;
The present invention has a configuration as a time constant adjustment circuit for a vertical integrator circuit for TV, which is composed of second current mirror circuits 118 and 120 that draw out the representative current of the reference current from the integrator.

The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a known horizontal oscillator.
FIG. 2 is a schematic diagram of a known vertical integrator circuit. FIG. 3 is a schematic diagram showing a circuit that couples the horizontal oscillator of FIG. 1 to the integrator of FIG. and set that time constant without further adjustment.

Summary of the invention Separating vertical and horizontal synchronizing pulses
In a TV integrator circuit, the time constant of the TV vertical integrator circuit is set by drawing from the integrator a representative current of the reference current used to trim the connected horizontal oscillator. be done. Current mirror circuits are used both to generate a representative signal in a horizontal oscillator and to derive a representative signal in an integrator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic diagram of one example of a horizontal oscillator for use with the present invention. This oscillator is node 1
includes an on-chip nitride capacitor 10 connected between 2 and 14. This circuit has a resistor of 16,1
a bias chain consisting of 8, 20 and 22;
Turnaround circuit consisting of diode 24 and transistor 26, transistors 28 and 30
a first comparator including transistors 32 and 34;
a second comparator including transistors 36 and 38;
and a current source including resistors 40 and 42, a reference amplifier including transistors 44, 46 and 48 and resistors 50 and 52, current mirror transistors 54 and 26, and transistors 58, 6
0 and 62 and resistance 64, 66, 68, 70
and a lower current mirror circuit including 72.

Reference amplifier transistor 44 has its base electrode coupled to bias voltage Vcc at node 74. Therefore, when transistors 44 and 46 are perfectly matched, an accurate reference voltage with a zero temperature coefficient is developed at node 76. The correct reference current I _R is then set by an external resistive network (represented by resistor 78). The reference current I _R is selected to compensate for the capacitive spreading (dispersion) of the oscillator.

The base of transistor 48 is transistor 44
is coupled to the collector. transistor 4
Since 8, 54 and 56 have their respective base and emitter electrodes commonly coupled, the currents generated in each of their collector electrodes are approximately equal. Depending on the gain of the lower current mirror circuit (transistors 58, 60, and 62), the current conducting transistor 58 may be greater or less than the current conducting transistor 56. If the current conducting transistor 58 is greater, current will be drawn from capacitor 10 creating a downward portion of the output signal ramp. This condition exists when the lower mirror circuit has a high gain. As the gain decreases, the current flowing through transistor 58 becomes less than the current flowing through transistor 56, and this difference increases the current flowing through capacitor 1.
0 to create the upward portion of the output ramp. Finally, transistor 80 along with resistors 82 and 84 provide temperature compensation for nitride capacitor 10. Capacitor 86 represents a leakage capacitor coupled to the base of transistor 46.

For a complete explanation of the operation of the horizontal oscillator shown in FIG.
See specification No. 4374366. Suffice it to say here that this oscillator is trimmed by appropriate selection of the reference current I _R.

An example of an integrated circuit for separating a vertical sync pulse from a composite signal containing horizontal and vertical sync pulses is shown in FIG. The emitter of a first current source, such as a normally conducting PNP transistor _T1 , is coupled to conductor 88Vcc by a resistor _R1 . Transistor T ₁
The base of is coupled to conductor 88 by diode D. The collector of transistor T ₁ is coupled to conductor 90 , which creates a first current path to current mirror circuit 92 . PNP that is always conductive
The emitter of a second current source, such as transistor _T2 , is coupled to conductor 88 by a resistor _R2 , and its base is coupled to the base of transistor _T1 . The collector of transistor T ₂ is coupled to conductor 94 , which creates a second current path to current mirror circuit 92 . The emitter of transistor _T2 is adapted to receive the signal to be integrated by limiting resistor _R3 . A capacitor 96 is coupled between conductors 90 and 94 and thus
and coupled between the collectors of the second current sources T ₁ and T ₂ . Current mirror circuit 92 is an NPN transistor having a collector coupled to conductor 90 and an emitter coupled to a reference potential, such as ground.
Contains _T3 . The current mirror circuit is also connected in series.
Also includes NPN transistors T ₄ and T ₅ ,
The collector of transistor _T4 is coupled to conductor 94, its emitter is coupled to the collector of transistor _T5 , and the emitter of transistor _T5 is grounded. The base of transistor _T5 is coupled to the emitter of transistor _T5 and also to the base of transistor _T3 . The base of transistor _T4 is coupled to conductor 90, thus
Coupled to the collector of transistor _T3 .

The potential at point A is the transistor T ₆ and
_Variable bias slicer amplifier (slicer
amplifier). Transistor T ₆ has a collector coupled to collector 88, a base coupled to point A, and an emitter coupled to pin 98 by resistor R ₇ . Pin 98 may constitute a pad of an integrated circuit. Pin 98 also has a separate individual capacitor 100 and a separate resistor.
R ₉ is coupled and these capacitors and resistors may be externally connected. Capacitor 10
0 and resistor R ₉ are connected in parallel between ground and pin 98. Transistor T ₇ has its collector coupled to conductor 88 by load resistor R ₆ , its base coupled to the emitter of transistor T ₆ , and its emitter coupled to pin 98 .
Transistors T ₆ and T ₇ form a Darlington type amplifier, and when transistors T ₆ and T ₇ conduct due to the positive voltage at the base of transistor T ₆ , capacitor 100 charges. The charge on capacitor 100 gives a slice level V _S and this
V _S is determined by the magnitude of the voltage at the base of transistor T ₆ and the time that transistors T ₆ and T ₇ are non-conducting. The time constant of resistor R ₉ and capacitor 100 should be adjusted to be long compared to the time between vertical pulses. Therefore, the charge on capacitor 100 decreases only slightly between vertical sync pulses. The variable bias provided by the charge on capacitor 100 is determined by the magnitude of the voltage at point A, which in turn is determined by the strength of the signal reaching the TV receiver. Therefore, the slice level V _S of amplifiers T ₆ and T ₇ is determined by the strength of the received signal. The slice level V _S should occur mid-height of the vertical pulse for strong signals to give excellent impulse noise performance, and the slice level V S should occur mid-height of the vertical pulse for strong signals, giving excellent impulse noise performance, and increase the vertical pulse tip as the incoming signal decreases. It should increase in the direction.

The output of the slice amplifier is applied to the base of the inverting amplifier transistor T ₈ and this transistor T ₈
has its emitter coupled to conductor 88 and its collector grounded through series connected resistors R ₄ and R ₅ . A separated vertical sync pulse appears at output terminal 102 at the junction of resistors R ₄ and R ₅ . A detailed description of the operation of the integrator shown in FIG. 2 is assigned to the assignee of the present invention, the teachings of which are incorporated herein by reference. Entitled “Integrator circuit to separate vertical sync pulses”
See US Patent Application No. 220,614, filed December 29, 1980 (US Pat. No. 4,449,146).

As mentioned above, it is desirable to use the same reference current I _R generated in the horizontal oscillator, or a portion thereof, to set (adjust) the time constant of the vertical integrator. This applies to nodes 14 and 76 in FIG.
This can be achieved by cutting the connection between the integrator and placing a current mirror circuit therebetween which draws I _R or a portion thereof from the integrator. This can be accomplished as shown in FIG. 3, where the dashed block 104 includes a portion of an oscillator, which partially includes the circuit previously described, and the dashed block 10
6 includes part of an integrator, which also includes the circuits already described. Blocks 104 and 10 previously described in connection with FIGS. 1 and 2
The reason for showing the circuit in 6 is to show the correct structural relationship between the known circuit and the additional circuit that allows the integrator time constant to be set by appropriate selection of I _R .

Referring to the oscillator circuit of FIG. 3, the current mirror circuit includes transistors 108 and 110.
The emitters of these two transistors 108 and 110 are coupled to node 76 through resistors 112 and 114, respectively. The collector of transistor 108 is coupled to node 14, as are the base terminals of transistors 108 and 110. As is well known, by appropriately scaling transistors 108 and 110 or resistors 112 and 114, or some combination thereof, a predetermined portion of I _R can be caused to flow to the collector of transistor 110. Of course, not only must I _R be considered as a trimming current, but compensation must also be made for the additional current required by the mirror element.

Block 106 showing a portion of the vertical integrator circuit
2, the diode D shown in FIG. 2 has been removed and is replaced by a resistor 116.
A beta compensated current mirror circuit including PNP transistors 118 and 120 is used. The collector of transistor 120 is grounded,
Its emitter is coupled to the bases of transistors _T1 and 118. The emitter of transistor 118 is connected to conductor 88 (Vcc) through resistor 116.
is combined with To complete the circuit, the collector of transistor 110 in the oscillator is coupled to the collector of transistor 118 and to the base of transistor 120 in the integrator. With this method, transistors T ₁ and T ₂
It is possible to control the current flowing to the collector of the oscillator (see Figure 2), and it can be set with a single adjustment of I _R in the oscillator. This technology can be used in TV systems where a high degree of timing accuracy for vertical pulses is required, such as Teletext and
Particularly applicable to VIRS.

The above description is given by way of example only. Those skilled in the art may make changes in form and detail without departing from the scope of the invention.