JPS5950119B2 - hall effect device - Google Patents

hall effect device

Info

Publication number
JPS5950119B2
JPS5950119B2 JP51132876A JP13287676A JPS5950119B2 JP S5950119 B2 JPS5950119 B2 JP S5950119B2 JP 51132876 A JP51132876 A JP 51132876A JP 13287676 A JP13287676 A JP 13287676A JP S5950119 B2 JPS5950119 B2 JP S5950119B2
Authority
JP
Japan
Prior art keywords
hall
voltage
terminal
unbalanced
effect device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51132876A
Other languages
Japanese (ja)
Other versions
JPS5357982A (en
Inventor
資馨 田中
哲二 小林
昇 松尾
治男 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP51132876A priority Critical patent/JPS5950119B2/en
Priority to GB46203/77A priority patent/GB1592908A/en
Priority to DE19772749763 priority patent/DE2749763A1/en
Priority to US05/849,416 priority patent/US4200814A/en
Publication of JPS5357982A publication Critical patent/JPS5357982A/en
Publication of JPS5950119B2 publication Critical patent/JPS5950119B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 この発明はホール効果装置に係り、特に4端子ホール素
子の不平衡電圧の補償手段に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Hall effect device, and more particularly to means for compensating unbalanced voltage of a four-terminal Hall element.

ホール素子はよく知られているように、磁場内において
この磁場に直交する方向の制御電流を流すことにより、
いわゆるホール電圧を生ずるものである。この場合、理
想的には磁場が零であれば夕制御電流を流してもホール
電圧を生じないはずであるが、現実にはいくらかの電圧
が発生する。この電圧は不平衡電圧と呼ばれ、各種の検
出あるいは測定用機器に利用した場合に誤差の原因とな
る。0 従来のホール素子は4端子のものが多いが、上
述した不平衡電圧を小さくするために一対のホール出力
端子を可能な限り対称性よ<作るのが一般的である。
As is well known, the Hall element allows a control current to flow in a direction perpendicular to the magnetic field within a magnetic field.
This generates a so-called Hall voltage. In this case, ideally if the magnetic field is zero, no Hall voltage will be generated even if the control current is passed, but in reality some voltage is generated. This voltage is called an unbalanced voltage and causes errors when used in various detection or measurement equipment. 0 Many conventional Hall elements have four terminals, but in order to reduce the above-mentioned unbalanced voltage, it is common to make the pair of Hall output terminals as symmetrical as possible.

このため、不平衡電圧は固定した極性を示さず、正から
負までランダムにばらついて、7むしろ不平衡電圧の補
償を難しいものとしている。この発明は上記した点に鑑
み、2個の4端子ホール素子を用いて確実に不平衡電圧
の補償を行つたホール効果装置を提供するものである。
Therefore, the unbalanced voltage does not exhibit a fixed polarity, but randomly varies from positive to negative, making compensation for the unbalanced voltage rather difficult. In view of the above points, the present invention provides a Hall effect device that reliably compensates for unbalanced voltage using two four-terminal Hall elements.

フ この発明では、一対のホール出力端子を意識的に非
対称とすることにより、不平衡電圧の極性を固定した4
端子ホール素子を用いることが基本である。
In this invention, the polarity of the unbalanced voltage is fixed by intentionally making the pair of Hall output terminals asymmetric.
The basic idea is to use a terminal Hall element.

即ち、不平衡電圧が正または負に予め定められた4端子
ホール素子を半絶縁性半導体基板の・両面に形設し、か
つこれら2個のホール素子を直列に結合し、不平衡電圧
を打消して和のホール電圧を得るように各ホール素子に
印加する電流を設定したことを特徴としている。以下、
図面を参照してこの発明の実施例を説明lする。
That is, four-terminal Hall elements whose unbalanced voltage is predetermined to be positive or negative are formed on both sides of a semi-insulating semiconductor substrate, and these two Hall elements are connected in series to cancel the unbalanced voltage. The current applied to each Hall element is set so as to obtain the sum of the Hall voltages. below,
Embodiments of the present invention will be described with reference to the drawings.

第1図は一実施例のホール素子ウェハを模式的に示すも
のである。図において、1はCrと00をドープした半
絶縁性GaAs基板であつて、この両面にエピタキシャ
ル成長させたn型GaAs層をホトエッチングして2個
の4端子ホール素子・ 2、3を形成している。裏面の
ホール素子3は破線で輪郭のみ示している。11、12
はホール素子2の制御電流端子電極であり、13、14
は同じくホール出力端子電極である。
FIG. 1 schematically shows a Hall element wafer of one embodiment. In the figure, 1 is a semi-insulating GaAs substrate doped with Cr and 00, and two 4-terminal Hall elements 2 and 3 are formed by photoetching an n-type GaAs layer epitaxially grown on both sides of the substrate. There is. Only the outline of the Hall element 3 on the back surface is shown by broken lines. 11, 12
are the control current terminal electrodes of the Hall element 2, and 13, 14
is also the Hall output terminal electrode.

図から明らかなように、表裏面のホール素子2,3はそ
れぞれの一対のホール出力端子が制御電流路に対して非
対称に段差をつけられており、かつ、これらは一方を電
流端子方向を軸として180゜回転させたとき他方に重
なるようなパターン配置に形成されている。このように
構成されたホール素子ウエハは予め端子電極が蒸着され
た第2図に示すようなセラミツク基板4にマウントされ
る。
As is clear from the figure, the pair of Hall output terminals of the Hall elements 2 and 3 on the front and back surfaces are stepped asymmetrically with respect to the control current path, and one of them is oriented in the direction of the current terminal. The pattern arrangement is such that when rotated by 180 degrees, one overlaps the other. The Hall element wafer thus constructed is mounted on a ceramic substrate 4 as shown in FIG. 2 on which terminal electrodes have been deposited in advance.

21,22,23,24は裏面のホール素子3のための
端子電極であり、31,32,33,34は表面のホー
ル素子2のための端子電極である。
21, 22, 23, 24 are terminal electrodes for the Hall element 3 on the back surface, and 31, 32, 33, 34 are terminal electrodes for the Hall element 2 on the front surface.

即ち、第1図のウエハを第2図のセラミツク基板4上に
鎖線で示す位置に載せて熱圧着することにより、裏面の
ホール素子3の端子電極がセラミツク基板4上の端子電
極21〜24に接続される。表面のホール素子2の端子
電極11〜14はそれぞれワイヤボンデイングによりセ
ラミツク基板4上の端子電極3フ〜34に接続される。
この状態を第3図に示してある。なお、端子電極23と
33の間がワイヤボンデイングにより接続され、これに
よりウエハの表裏面に設けられた2個のホール素子2,
3は直列に結合されたことになる。このように構成して
、端子電極21,22間に電源25、可変抵抗26を接
続し、同様に端子電極31,32間に電源35、可変抵
抗36を接続して表裏面のホール素子2,3に互いに逆
方向となる制御電流を流し、磁界Hを印加して端子電極
24と34の間にホール出力を得るものである。
That is, by placing the wafer shown in FIG. 1 on the ceramic substrate 4 shown in FIG. Connected. The terminal electrodes 11-14 of the Hall element 2 on the front surface are connected to the terminal electrodes 3-34 on the ceramic substrate 4 by wire bonding, respectively.
This state is shown in FIG. Note that the terminal electrodes 23 and 33 are connected by wire bonding, thereby connecting the two Hall elements 2 and 33 provided on the front and back surfaces of the wafer.
3 are connected in series. With this configuration, a power source 25 and a variable resistor 26 are connected between the terminal electrodes 21 and 22, and a power source 35 and a variable resistor 36 are similarly connected between the terminal electrodes 31 and 32, so that the Hall elements 2 and 2 on the front and back surfaces are connected. Control currents in opposite directions are passed through the terminals 3 and a magnetic field H is applied to obtain a Hall output between the terminal electrodes 24 and 34.

いま、磁界Hを印加しない状態で各ホール素子2,3に
逆方向の制御電流を流すと、それぞれのホール出力端子
の非対称性ゆえに画素子2,3には異符号の不平衡電圧
VHO2,VHO,が生じる。可変抵抗26,36で各
々の制御電流を調整することにより、不平衡電圧VHO
。,VHO,の大きさは等しくなるから、端子電極23
,(33)を零電位に設定すれば全体としての出力端子
電極24,34間には出力電圧が現われない。次に磁界
Hを印加した場合、各素子2,3に生ずるホール出力電
圧VH,,VH,は磁界と制御電流の関係から全体とし
てのホール出力電圧VHはこれらの和VH,+VH,と
なり、1個のホール素子の場合に比べて約2倍の大きさ
になる。
Now, if a control current in the opposite direction is applied to each Hall element 2 and 3 without applying the magnetic field H, unbalanced voltages VHO2 and VHO of opposite signs will be generated in the pixel elements 2 and 3 due to the asymmetry of the respective Hall output terminals. , occurs. By adjusting each control current with the variable resistors 26 and 36, the unbalanced voltage VHO
. , VHO, are equal in size, so the terminal electrode 23
, (33) are set to zero potential, no output voltage appears between the output terminal electrodes 24 and 34 as a whole. Next, when a magnetic field H is applied, the Hall output voltages VH, , VH, generated in each element 2 and 3 are the sum of these VH, +VH, and the Hall output voltage VH as a whole is 1 due to the relationship between the magnetic field and the control current. The size is approximately twice as large as that of a single Hall element.

このようなホール効実装置は例えば電力量計等に適用し
て有用である。
Such a Hall effect device is useful when applied to, for example, a power meter.

即ち、負荷電圧を変圧器に入れて独立した2個の低圧出
力を得、これを第3図示の制御電流用電源25,35と
置換し、また負荷電流を電磁石のコイルに流して磁界H
を得る。この結果、得られるホール出力VHは負荷電圧
と負荷電流の積、即ち消費電力に比例したものとなる。
このような電力量計では、前述したとおり、ホール素子
の不平衡電圧の影響が除去されるため、特に軽負荷電流
領域での測定精度が非常に高いという特徴を有する。以
上説明したように、この発明に係るホール効実装置は、
従来の4端子ホール素子単体に比べてほゞ2倍のホール
電圧が得られると共に、不平衡電圧が確実に補償され、
電力量計等に適用して優れた測定精度が得られる。
That is, the load voltage is input into a transformer to obtain two independent low-voltage outputs, and these are replaced with the control current power supplies 25 and 35 shown in Figure 3, and the load current is passed through the coil of the electromagnet to generate the magnetic field H.
get. As a result, the Hall output VH obtained is proportional to the product of the load voltage and the load current, that is, the power consumption.
As described above, such a watt-hour meter is characterized by extremely high measurement accuracy, particularly in the light load current region, because the influence of the unbalanced voltage of the Hall element is removed. As explained above, the Hall effect device according to the present invention is
Compared to a conventional 4-terminal Hall element alone, it is possible to obtain a Hall voltage that is approximately twice as high, and unbalanced voltage is reliably compensated for.
Excellent measurement accuracy can be obtained when applied to power meters, etc.

また、この発明に係るホール効実装置では、2個のホー
ル素子がウエハの両面に形成されるから、例えばモール
ド済みのホール素子単体を2個用いる場合に比べて小形
にlなることは勿論、磁場強度や温度等が2つの素子に
ついて均一になり、高い測定精度が得られる。更に、ウ
エハの両面に形成されたホール素子には互いに反対方向
の制御電流を流すことになり、熱起電力が相殺されると
いう効果もある。なお、この発明は上記実施例に限られ
るものではない。
In addition, in the Hall effect device according to the present invention, since two Hall elements are formed on both sides of the wafer, it is of course smaller in size than, for example, when two single molded Hall elements are used. Magnetic field strength, temperature, etc. become uniform for the two elements, resulting in high measurement accuracy. Furthermore, control currents in opposite directions are passed through the Hall elements formed on both sides of the wafer, which has the effect of canceling out thermoelectromotive force. Note that this invention is not limited to the above embodiments.

例えば実施例では制御電流の大きさを制御することによ
り不平衡電圧を確実に相殺するようにしたが、第4図に
示すように制御電流電源25,26により各制御電流を
固定しても、可変抵フ抗41とバイアス電源42をホー
ル出力端に接続し、ホール出力電圧に外部バイアスを加
えることによつて不平衡電圧を補償することが可能であ
る。
For example, in the embodiment, the unbalanced voltage is reliably offset by controlling the magnitude of the control current, but even if each control current is fixed by the control current power supplies 25 and 26 as shown in FIG. It is possible to compensate for the unbalanced voltage by connecting the variable resistor 41 and the bias power supply 42 to the Hall output terminal and applying an external bias to the Hall output voltage.

【図面の簡単な説明】[Brief explanation of drawings]

ク 第1図はこの発明の一実施例におけるホール素子ウ
エハを示す図、第2図は上記ウエハをマウントするため
のセラミツク基板を示す図、第3図は上記ウエハを上記
セラミツク基板にマウントしてバイアスを印加した状態
を示す図、第4図は他のク実施例を示す図である。 1 ・・・・・・半絶縁性GaAs基板、2.3・・・
・・・ 4端子ホール素子、11,12・・・・・・制
御電流端子電極、13,14・・・・・・ホール出力端
子電極、4・・・・・・セラミツク基板、21,22,
23,24,31,32,33,34・・・・・・端子
電極、25,35・・・・・・電源、26,36・・・
・・・可変抵抗、41・・・・・・可変抵抗、42・・
・・・・バイアス電源。
Figure 1 is a diagram showing a Hall element wafer in an embodiment of the present invention, Figure 2 is a diagram showing a ceramic substrate on which the wafer is mounted, and Figure 3 is a diagram showing the wafer mounted on the ceramic substrate. FIG. 4 is a diagram showing a state in which a bias is applied, and FIG. 4 is a diagram showing another embodiment. 1...Semi-insulating GaAs substrate, 2.3...
... 4-terminal Hall element, 11, 12... Control current terminal electrode, 13, 14... Hall output terminal electrode, 4... Ceramic substrate, 21, 22,
23, 24, 31, 32, 33, 34... terminal electrode, 25, 35... power supply, 26, 36...
...Variable resistance, 41...Variable resistance, 42...
...Bias power supply.

Claims (1)

【特許請求の範囲】[Claims] 1 一対のホール出力端子を非対称に配置することによ
つて不平衡電圧の極性を固定した2個の4端子ホール素
子を、半絶縁性半導体基板の両面に形成し、かつこれら
2個のホール素子をそれぞれの不平衡電圧の極性が逆方
向となるように直列に結合し、不平衡電圧を打消して和
のホール電圧を得るように前記各ホール素子に通電する
電流値を設定したことを特徴とするホール効果装置。
1. Two four-terminal Hall elements whose unbalanced voltage polarity is fixed by asymmetrically arranging a pair of Hall output terminals are formed on both sides of a semi-insulating semiconductor substrate, and these two Hall elements are coupled in series so that the polarities of the respective unbalanced voltages are in opposite directions, and the value of the current flowing through each of the Hall elements is set so as to cancel the unbalanced voltages and obtain a sum of Hall voltages. Hall effect device.
JP51132876A 1976-11-05 1976-11-05 hall effect device Expired JPS5950119B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP51132876A JPS5950119B2 (en) 1976-11-05 1976-11-05 hall effect device
GB46203/77A GB1592908A (en) 1976-11-05 1977-11-07 Multiplier with hall element
DE19772749763 DE2749763A1 (en) 1976-11-05 1977-11-07 MULTIPLICATION
US05/849,416 US4200814A (en) 1976-11-05 1977-11-07 Multiplier with hall element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51132876A JPS5950119B2 (en) 1976-11-05 1976-11-05 hall effect device

Publications (2)

Publication Number Publication Date
JPS5357982A JPS5357982A (en) 1978-05-25
JPS5950119B2 true JPS5950119B2 (en) 1984-12-06

Family

ID=15091612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51132876A Expired JPS5950119B2 (en) 1976-11-05 1976-11-05 hall effect device

Country Status (1)

Country Link
JP (1) JPS5950119B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04159803A (en) * 1990-10-23 1992-06-03 Matsushita Electric Ind Co Ltd Power amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04159803A (en) * 1990-10-23 1992-06-03 Matsushita Electric Ind Co Ltd Power amplifier

Also Published As

Publication number Publication date
JPS5357982A (en) 1978-05-25

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