JPS5949589A - Blinker - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Misfiring LII4 relates to flashers.

Figure 1 shows the circuit configuration of a conventional flasher. In this conventional circuit, a shift register (21f31) shifts the output of the D-turn signal CK from the clock generation circuit i11 at the rising edge of Figure 2(a). At the same time, the serial input signals SD1...SO2, which are shift data, are read and output in xi and small watts.The serial input signal SDI is always ramped up and kept at the sHs level.In addition, the serial input signal SD2 is Shift register (2
) is selectively connected to one of the outputs using the pattern switch (4). Shift register (2) shifts the tt signal RS to shift register (2).
6), it is designed to reset using its own output. In this conventional example circuit, first, the reset signal R5 shown in FIG. 2(b) is input to the shift register (2), and when the reset signal R5 shown in FIG. 2(b) is applied, all outputs of the shift register (2) are 〃Become the level. Therefore, at this time, the shift l-data is the serial input signal 5t)
2 is also at the L level. Next, when the clock CK is applied, an 11 level signal 7L is output to the smallest pit of the shift register (3). Each time the clock signal is added to CK, each output gradually increases to #H toward the maximum pit. Serial input signal SD2 in the state shown in this figure.
is as shown in Fig. 2(c), and according to this, each output of the shift register (3), the blinking output signals (6a) to (
6h) will be sequentially output as shown in FIG. 2(d) to (j). In other words, it will blink 1 dot and 6 blinks.

In this way, the conventional circuit requires one shift register each for creating a butter shifter and for shifting the blinking pattern, and the blinking pattern data is also limited to continuous on and off states. Therefore, it is possible to provide a flasher with a simple construction and low cost by using every other or two flashers.

The present invention will be explained below with reference to Examples. FIG. 3 is a basic block configuration diagram of one embodiment, and FIG. 4 shows a specific circuit of one embodiment, in which (1) a zero-kick generation circuit, (7) a shift register for shifting the blinking pattern, ( 8) outputs the data set signal DS and the data set signal DH of the serial input signal SD, which is shift data, by each blinking output signal (6a) to (6h) of the shift register (7), and calculates the blinking pattern and the number of circuits. The switching pattern/circuit number switch (9) is a data switch that switches the serial input signal SD, which is Schifmil data, in accordance with the data set signal DS and the data reset signal DR.

Next, the operation of this embodiment will be explained using the circuit shown in FIG. 4 and the time cisode shown in FIG.

Serial input signal SD as shift data in initial state without freezing
Suppose that #H#' is #H#'. Here, when D Tsukui No. 8 CK is added as shown in FIG. 5(a), the blinking output signal (6a) of the 1111 level shown in FIG. ) is output. At this time, since the data reset signal JPjDR and the data reset signal DS do not change as shown in FIG. 5(c) and (d), the state of the serial input signal SD also changes as shown in FIG. 5(b). There is no. Like Jin, R0tsuku signal C
Every time K is added, a blinking output signal % (6a) tri continues to be output from the output terminal Ql of the shift register (7).

Then, when 4 CKs that receive 0x are added to the shift register (7), the blinking output signal Jj (6d) output from the output terminal Q4 of the shift register (7) is switched to the pattern/number of circuits switch (8). The data reset signal DR is outputted through the first selection switch SWI as shown in FIG. 5(c), and the output of the data switch 'ffFf91 consisting of a flipflop is inverted at the rising edge of the data reset signal DR. In other words, the serial input signal SD is inverted to the L level, and each time the next 0 clock signal CK is input to the shift register (7), the output terminal Q1 of the shift register (7) is input to the shift register (7).
The output becomes 〃L# level. Andori D Tsukushin JPj
'When 8 CKs are added, the output on the 9th day of the shift register (7), the flashing output signal JPj (6h), is set as data via the second selection switch SW2 of the pattern switch (8). The signal DS is inputted to a data switch (9) consisting of a flip-flop shown in FIG. 5 (ω), and the output is inverted. In other words, after the serial input signal SD changes to the #H level, the above-described operation is repeated.

As described above, a blinking pattern is created and sequentially shifted.
7) shows blinking output signals g(6a) to (6h) outputted from each output AMI Q1 to Q8, and these signals are connected to corresponding dimmers (101,) to (10a).
The lights Ll-Ls can be turned on or off through the dimmers (101) to (1oa). By the way, since the output of the shift register (7) is fed back and the shift data, that is, the serial manual input (=WsD) is set and reset, the blinking pattern and number of circuits are changed, so each blinking output value ゛ (6a) to (6h ) logical sum of
It is also possible to create various blinking patterns by performing a logical product or the like to obtain the data set signal JJDS and the data reset signal 1)R.

FIG. 6 shows an embodiment made in view of this point.

In other words, a Nasido gate (lO) is used as the pattern/number of circuits switch (8), and if all outputs of the shift 1 noister (7) are "L" in the initial state, the serial data is not set. Because there is, please trust the clock!
Every time +CK is added, the output terminal Q of the shift register (7)
1 to Qa # l (# level flashing output signal (6a)
~ (6h) is shifted and when it is shifted to the output terminal Q8, this time, the serial data is reset.From the L1 order of the awn node, the ILI (..., bell signal can be shifted.In other words, the serial data is reset. The blinking output signal (6h) becomes the data reset signal DR and inverts the output of the data switch (9). When the Ll level signal is shifted and reaches the output terminal QeK of the shift register (7), all The outputs of the output terminals Q1 to Q8 become βL and I\, and a high level signal is output, that is, a data set signal DS is output, and the daycliff changer is output. (The output of 1 is inverted and the shift data is set. In this way, the upper pits 5 from the smallest pit sequentially output blinking output signals (6a) to (6h) to respond. Each lamp is turned on through a dimmer, and after all the lamps are turned on, the lights are turned off one after another starting from the smallest pit, resulting in a sequential flashing pattern.
The figure shows a time chart of signals in each part of the circuit.1.
Figure (a) Beam D-tock generation circuit [Output from 11 is 0
The figure (b) is the serial input signal SD which is the shift data output from the Cheetah V nokuri (9), the figure (c) is the data reset signal 'ij D R, the figure (d
) is the data set signal DS, (e) to (1) in the figure are each output of the output terminal Ql''Qa of the shift register (7),
That is, the blinking output signals J8 (6a) to (6h) are shown.

FIG. 8 shows another embodiment circuit of the present invention, and this embodiment circuit uses a shift register (7) as a data set signal DS.
) The blinking output signal (6c) output from the output terminal Q3 of
In addition, a shift register (
7) The blinking output light No. 1 (6b) of the output terminal Q2 is used to obtain a blinking pattern of turning on twice and turning off once. FIG. 9 shows a time chart of the output signals of each part of the circuit of FIG. Serial input signal SD to output
, (c) shows the data reset signal DR, and (d) shows the data reset signal DR.
) shows the data set signal DS, and (e) to (1) in the same figure show the blinking outputs (*'+ (6a) to (6h)) output from each output terminal Ql -Qa of the shift register (7).

The present invention includes a clock generation circuit and a shift register for shifting a blinking pattern, which takes in a cross-D check signal from the clock generation circuit and outputs the output from the output end of the valley pit as a blinking output signal for controlling blinking. Extract any two blinking output signals and convert one signal into a data set.

The shift register is equipped with a data switch which uses the other signal as a data reset signal and switches the shift data of the shift register to z i (# or ILI level) by these data set signals and data reset signals. Since data creation and shifting are performed in the same shift register, it is possible to reduce the size and cost, and since the shift data is created by feeding back the output, it is possible to freely set the blinking pattern. This has the effect of

[Brief explanation of drawings]

f)'r, Figure 1 is a circuit configuration diagram of a conventional example, Figure 2 (a)
- (j) are the time cisodes of the output signals of each part of the same as above, Fig. 3 is a basic circuit configuration diagram of an embodiment of the present invention, Fig. 4 is a specific circuit configuration diagram of the same as above, and Fig. 5 (a) - ( 1) is the time chart of the output signal of each part same as above, FIG. The figure is a circuit configuration diagram of another embodiment of the present invention, and FIGS. 9(a) to (1) are time charts of output signals of each part of the same as above.
LD Tsukku generation circuit, (6a) to (6b) are blinking output section 9, (71iJ: shift register for blinking pattern shift, (9) is data switcher, SD is serial input signal, DS is data set signal, DR is Data reset signal, CK is a clock signal, Q1~Q8I/'i output terminal. Agent Patent attorney Ishi 1) Chief 7 Figure 2 (j) Figure 3 o@oBocoao@o+su1sn Figure 5 ((). Figure 6 ζ-NI NI-1 NI NI N-, ノ
, No. 51,.

Claims (1)

[Claims] It is equipped with a flashing pattern shift shift register which inputs the clock signal from the clock generating circuit and outputs the output from the output end of each pit as a flashing output signal for controlling flashing. , extract any two signals from the flashing output signals, use one signal as a data reset signal, and output the other signal as a data reset signal to the shift register using these data signals and data reset signals. A blinker characterized in that it is equipped with a data switcher for switching shift data to ``Hl'' or ``LI level.