JPS5949237U - Electronics - Google Patents

Electronics

Info

Publication number
JPS5949237U
JPS5949237U JP13089983U JP13089983U JPS5949237U JP S5949237 U JPS5949237 U JP S5949237U JP 13089983 U JP13089983 U JP 13089983U JP 13089983 U JP13089983 U JP 13089983U JP S5949237 U JPS5949237 U JP S5949237U
Authority
JP
Japan
Prior art keywords
calculation section
section
power supply
control signal
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13089983U
Other languages
Japanese (ja)
Inventor
伸太郎 橋本
橋本 定勝
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP13089983U priority Critical patent/JPS5949237U/en
Publication of JPS5949237U publication Critical patent/JPS5949237U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案−実施例の回路構成図、第2図、第3図
は他の実施例の回路構成図である。 QlないしQ8はPチャネルエンハンスメント型MO3
形電界効果トランジスタ、q1〜q7はPチャネルディ
プレッション型MO8電界効果トランジスタ、DPは表
示部、CCは計算部、KBはキ一部、DSは電源制御回
路をそれぞれ示す。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams of other embodiments. Ql to Q8 are P channel enhancement type MO3
q1 to q7 are P-channel depletion type MO8 field effect transistors, DP is a display section, CC is a calculation section, KB is a key section, and DS is a power supply control circuit, respectively.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)操作部、計算部、電源、及び表示部からなる電子
機器において、操作キーの操作終了後一定時間経過する
と、第1の制御信号を上記計算部に加えることにより、
該計算部への電源供給を終了し、その後任意の操作キー
への操作による第2の制御信号により上記計算部への電
源の供給を開始させる回路を設けたことを特徴とする電
子機器。
(1) In an electronic device consisting of an operation section, a calculation section, a power supply, and a display section, when a certain period of time has elapsed after the end of the operation of the operation keys, by applying a first control signal to the calculation section,
An electronic device comprising a circuit that terminates power supply to the calculation section and then starts supplying power to the calculation section in response to a second control signal generated by operating an arbitrary operation key.
(2)  上記回路をE/D−MOS トランジスタで
構成したことを特徴とする実用新案登録請求の範囲第(
1)項に記載の電子機器。
(2) Utility model registration claim No. (
Electronic equipment described in item 1).
JP13089983U 1983-08-23 1983-08-23 Electronics Pending JPS5949237U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13089983U JPS5949237U (en) 1983-08-23 1983-08-23 Electronics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13089983U JPS5949237U (en) 1983-08-23 1983-08-23 Electronics

Publications (1)

Publication Number Publication Date
JPS5949237U true JPS5949237U (en) 1984-04-02

Family

ID=30296118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13089983U Pending JPS5949237U (en) 1983-08-23 1983-08-23 Electronics

Country Status (1)

Country Link
JP (1) JPS5949237U (en)

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