JPS5948896A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor IC such as a semiconductor memory, etc. which works on a single power supply and can be converted into a high degree of integration, by forming the regions adjacent to each other for n and p channel type transistors and then actuating these two regions independently of each other. CONSTITUTION:The n and p channel type transistor regions 111 and 112 as well as 113 and 114 are adjacent to each other and then switched by common gate wirings 12, 13, 15 and 16 so that the region of one side is on while the other region is off respectively. Then these regions are actuated independently of each other. In the same way, n and p type transistors which form the memories of regions 111 and 112 as well as 113 and 114 are selected independently of each other by common gate lines 141, 142-. Thus the contents of storage are read out in response to the presence or absence of transistors. Thus it is possible to obtain a semiconductor IC such as a semiconductor memory, etc. which works on a single power supply and can be converted into a high degree of integration.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor 14 suitable for forming a ROM (read only memory) entirely on a substantially insulating substrate.
Related to product circuits.

[Technical background of the invention and its problems]

MO8 type integrated circuit As a means of integrating and improving the performance of an integrated circuit, so-called SO8 (5 silicon on 5apph) is used to form semiconductor elements on a semi-dedicated layer grown on an e-layer substrate.
There is a semiconductor device tf'L manufactured by JFJJ. The conventional SO8 type ROM has a pattern configuration as shown in Figure 1, and the memory cell portion is one channel (in this case, N
414 channels). Here, the contents of the stored data are determined by the presence or absence of transistors on the input signals 1-In. In FIG. 1, 11 to 14 are N channel (W transistor forming semiconductor regions, 21+2
2+31. ．． 3n is a dirt wiring, 41 to 44 are output wirings, the hatched part is a transistor part, and 51.

52 is a power supply VDD l vss wiring section.

Figure 2 shows SO8W filed IA: filed by the non-filing applicant.
It is a ROM (Japanese Patent Application No. 75164/1983). This one connects the P-chael-type transnostar-forming semiconductor region to the power supply V.
ss ” = Vc (ground), and the semiconductor region where the N-channel type transistor is formed is operated in the voltage range of V. to ■DD. As a result, the semiconductor region where the P-channel type transistor is formed and the semiconductor region where the N-channel type transistor is formed are reverse biased. 61 r64 in FIG.
is a P-channel transistor forming semiconductor region, 6216
3 is an N-channel transistor forming semiconductor region, and 53 is V. (Ground) potential wiring, 21.22.31.32...
3n is a dirt wiring. Further, the downward-left-cutting part is a P-channel type transistor, and the downward-rightward-cutting part is an N-channel type transistor.

The problems with the configuration shown in FIG. 1 are as follows: Gaps ffz are provided at regular intervals between the regions 11 to 14, resulting in poor integration. Also, the starting point of the configuration in Figure 2 is v88
This means that there will be a two-source system: + VG + VDD.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is intended to provide a semiconductor integrated circuit k''H such as a semiconductor memory, which can be integrated in a large area and can be operated in a simple manner.

[Song of invention, essential]

In order to achieve the above object, the present invention aims at high integration by inheriting the P-channel type transistor forming semi-conductor region and the N-channel type transistor forming semiconductor region. When connected to the armpit and operated in a humid environment, the circuit is removed and adjacent circuits operate independently of each other.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Third
The figure is a pattern plan view showing the configuration of the same embodiment, and FIG. 4 is a circuit diagram formed along lines 1-1 and nn in FIG. 3.
FIG. 5 is a sectional view taken along line I-1. 111 in the diagram
+112 +113.114 is I-1 line, ■-■ line,
The N-channel type, P-channel type, N-channel type, and P-channel type transistor forming semiconductor regions are located along the III-III line and IV-IVil, and the N-channel type region 111
and r-) wiring 12 of input I, dirt wiring J3 of input φ,
Input It+In gate wiring 141°14n, input φ
An N-channel transistor ■1. .

NjN, + N 111 NI n + Iφs1 *
IN'1 formation sensor formation channel type training area 112 and dirt wiring 12.13°J42. At the intersection with 14ng15g16, there is a P-channel MOS transistor Ipl.
* I$p1 t PI3 rPln, IφPI?
IP'1 is formed, and N channel type region 113 and f-
) Distribution #i! 12, 13 * 1411142+15.
At the intersection with 16, there is an N-channel type MO8) Lannostar I.
N2 r I$N2 t N21 + N22 r I
φN211N'2 is formed, and the P channel type singing region 114
and dirt wiring 12@13. 141 r14nH15
t at the intersection with +16: t P-channel type MO8) Lannostar IP2 * l1p2νP21 t P2n
t IφP2 e Ip'2 is formed. Also, the N channel l1i), the region 111 and the P disposed adjacent to this
The channel type IJl castle 11° is connected at one end 1i11 to the wiring 17 of the positive potential side (VDI), and at the other end to the wiring 18 at the ground If level (6). The N-channel region 113 and the P-channel region 113 disposed adjacent to the N-channel region 113
4 is IN! It is connected to the wiring 12 of one pillow source vDD at I, and connected to the contact J line wiring 18 at the other end. 1/this area 1
11~114μ output 02 r O+ + 03 +
04 is connected to glands 191-194. In addition, N 12 * P 11 r N of a part of the memory in FIG.
The 2n + P 22 portion indicates a portion where the gate insulating film is thick and no fVloi-i type transistor is formed in a substantial amount. Further, in FIG. 5, 21 is a sapphire substrate, and 22 is an insulating layer. Further, in FIG. 4, 31 indicates the P channel/lz type region 112 and the N channel type region 11.
1 are placed in contact with each other.

The special imitation of the circuit configuration in Figs. 3 and 4 is a P-channel type robust area, an N-channel type 4-head area, and a metal phase structure, and the 'power source vDD
* VG 2 A circuit configured as a power supply is provided with a P-channel and N-channel selection signal, and the circuit in the # area where a P channel is formed is 9. When making a work,
All circuits in the region where the N channel is formed are turned off. When the P-channel region is operated, the N-channel region adjacent thereto operates normally as a semiconductor memory rather than a mere output capacitor.

The operations in FIGS. 3 and 4 will be explained. First, a method for obtaining data on whether or not a transistor is formed in the N12 portion on the memory cells arranged in a matrix will be explained. First P.

The N selection signal ■ is set to the "■" (high) level. Also, human power I
``Hn level is input to all of the input data signals 11+I3+...In except 2.The above flexibility makes the difference φ'k''
When the level is H'', the transistor lN1tItN1*
IN'I turns on, transistors I, 1. I 1. ■φ
N1 t IP'1 turns off. Therefore, output 02 is L
” (low) level. At this time, the transistor I4N1 + Ipl.

■, '1 is off, so V from the power supply VDD. No blood flow path is formed. If the input φ is set to "l" level, the transistor level N1゜Ipl r Ip
'1 r Iφ2. is turned off, and the transistor Iφpal
IN111N'l turns on. In addition, in the memory cell part, the transistor N I I + N 13';'N
1 n and Pt2 are turned on, transistor Nl 2
+ pt I + Pl3 t...PtHfd is turned off. In this case, no transistor is formed in the N12 part, and this N120 part is the dirt wiring I in FIG.
As you can see in one of the N-type layers in 2, is the structure in which the transistors on both sides are completely shorted? Therefore, with the power supply VDD and all transistors I and 4 on output 02 on, the output 02 will be ``)(''(VDD). Things N1
Data indicating "transistor" is detected in the part 2. At this time, the transistor IφN11 I, t I
P', i.;t: , t 7 Takara, no current path from the power source VDD to vo is formed.

Next, a method for obtaining detection data indicating whether a transistor is formed in the memory cell P12 will be described. First, set the P and N operation signal to "L" level. Also, Irikadeku I excluding Irikani 2! +I3...Input L" level to all In. Input "H# level to I2. When the input cuff is set to "L" level under the above conditions, transistors I and I- turn on, and transistor ■N1゜Pl
φP1 1iN1+IφI'111N'1 is turned off. Therefore, the output 01 is precharged to the "L# level. At this time, the transistor IφP11 INl 1 r, /1 is off, so a current path from the power supply VDD to vG is not formed. ``When set to L# level,
Transistor v, 1. ■N1. IN'1. IφN1 is turned off, and the transistor IφN11 IP1 sub-bar becomes 71-
7 to 0 Also, in the memory cell part, the transistor Pth I
P13. ...Pln (however, pH=/) - Guyo'tx
x, qrh) and Ntz are turned on, and if a transistor is formed in the Pt2 portion, the transistor Pt2←L is turned off.

-For which reason, P11+P111. Despite lφP111P'f's Beni) and 1jII, the notri path of liJ between VDD and output O1 is 1 kiran, and the output OxM
Maintain the L# level. For this reason, in the ptz part, the r-yuka 4 part, ``°'' with trannosta,'' is displayed.

Note that the present invention is based on the above-mentioned actual J)l! 1. There's only one person for me
Individual applications are possible without any problems. 1 (For example, the transistor used in this circuit (〆ma) can be either an efficiency type or a depression type. Also, the positions of the electrical components Dゎ and vG are opposite to those in Example 1 and 1. The arrangement of (
You can also use λ. Further, the circuit gold/h'i n or substrate may be substantially +Ne g=, and is not limited to a sapphire substrate. 'G/Koshi1'E&
;L In Fig. 4, the output is from transistors Nll to N1.
．． One end or the other end of the series circuit of transistors P12~
It may be taken out from one end of the series circuit of P1n or from the other y-. For example, in Fig. 4, by selecting the DART IHA #) l transistor IN4. ■φ
N1 is a P-chael type, and the transistor IP11 I
≠P1 may be an N-channel type.

〔Effect of the invention〕

As explained above, according to the present invention, since the region where all the N-channel transistors are formed and the one-hole region where all the P-channel transistors are formed are in contact with each other, single-layer integration is possible, and it is possible to If you operate all the connected circuits, you will be able to operate only one of the connected circuits (I cut off the %' source line of the other circuit, so you can operate only one circuit. In other words, the first channel type circuit network By making the circuit functions of the circuit network and the circuit network of the second channel 41J different, and by selectively operating these circuit networks, it is possible to make the integrated circuit multi-functional. can perform nuclear functions according to the zolograms of two lances.Also, the circuit requires only one power source.

[Brief explanation of the drawing]

Figure 1 is a pattern plan view of a conventional SO8 type ROM;
The figure is a plan view of an improved type of turn, Figure 3 is a plan view of a pattern of an embodiment of the present invention, Figure 4 is an equivalent circuit diagram of the same pattern, Figure 5C [same] and I of a turn. - It is a sectional view taken along the I line. "l rl13... N-channel Q transistor formation region, 172 + 174... P-channel type transistor formation region, Iφ, 1... First switching child,
IP'1...Second switch;:・Futako, Iφp1・
...Third switch element, ■P1...Fourth switch 7), child, 1-1...Fifth switch element, -'1
...Sixth switch element, I<1lN1...Seventh switch element, INl...Eighth switch element, vD
D, vo...' Ichihara. Applicant's agent Patent attorney Takeshi Suzue Pork box 1 Figure 11121314 No. 2 k 1 Figure 3 I I 11 111 mlS7 Figure 4

Claims (8)

[Claims] (1) A first switch element, a first channel type MOS transistor of the first logic section, and a second switch element connected in series between the first potential supply terminal and the second potential supply terminal; A third switch element connected in series between the first potential supply terminal and the second potential supply terminal, a second channel type MO8) of the second logic section, a runnostar and a fourth switch element, and the MOS of each of the above logic sections. ) The input end connected to the dart electrode of the transistor and the above first and second logic parts respectively connected to the -
control so that when the first and second output terminals, the first switch element and the second switch element are turned on (off) at the same time, the third switch element and the fourth switch element are turned off (on) at the same time. The special purpose of the present invention is to implement means and 4, and to enable the circuit functions of the first channel type MO8) transistor system and the circuit functions of the second channel type MO8) transistor system to operate selectively and independently. A collection of semiconductors, (l(circuit). (2) A first switch element, a second switch element, and a first channel type MO8 transistor of the first memory section connected in series between the first potential supply end and the second power supply end. , a third switch element, a fourth switch element, a tin 5 switch element, a sixth switch element, and a second memory portion connected in series between the first 111th position supply terminal and the second potential supply terminal. When the second channel type 1vlO8) transistor, the seventh switch element, the eighth switch confectionery, the first switch element and the fourth switch element are turned on (off) at the same time, the fifth switch element and the eighth switch element are turned on (off) at the same time. a first means for turning off (on) the electric current at the same time; and the 7th switch Yuiko on and off so that the 1st thread is reversed (the second hand to wholesale,
1. A semiconductor integrated circuit which is capable of operating selectively and independently of the memory function of the first memory part and the memory function of the second memory part. (3) a substantially insulating body which is a substantially insulating material; a first switch element and a second switch element formed on the substantially insulating material and connected in series with each other; and a substantially insulating body which is connected in series with the switch element; A first conductivity type semiconductor region for forming a first channel type MOS transistor of the first memory portion formed above and a 4OS transistor connected in series to the above.
- third and fourth switches formed on the substantially insulating body, and fifth and sixth switches formed on the substantially insulating body and connected in series; a second channel type MO of a second memory portion connected in series to the switch element and formed adjacent to the first conductive rectangular semiconductor region on the substantially insulator; a semiconductor layer connected in series to the type half 2 outer body region and the second channel type MOS transistor and formed on the substantially insulator;
7 and 8th switch elements, and the first. 2nd switch element, 1st channel type N, 10S) Rannosk, 3rd.
lth series circuit consisting of a fourth switch element, and a ratio of 5. 6th switch element, 2nd channel type MO8) transistor,
7th. 8th Sui, 2nd series circuit consisting of Thioko, 1st
Parallel connection p' between the potential supply end and the 2'ii supply end
e-do 1st stage and soil 1j pi 1st. 2nd channel type MO
8) An input terminal connected to the dart terminal of the transistor, first and second output terminals connected to and connected to the first and second memory portions, respectively, and the first switch element and the first switch element. When the 4 switch elements are turned on (off) at the same time, the 5th switch element and the i@8 switch element are all turned off (on) at the same time! A first means for Y1111σ1j,
The above-mentioned second switch element and the third switch element have an all-on/off relationship reversed, and the sixth switch element and the seventh switch element have an all-on/off relationship opposite to each other. The second means to make ffflJ groan and the whole device 11m is a special coincidence, and 1 is a body integrated circuit. (4) The first channel above! Each switch element connected in series with the dust+JO8 transistor is a first channel type MO
8) The second channel type MO8 is formed of a transistor.
) Each switch element connected in series with the lannostar is formed of a second channel type MOS transistor.
A semiconductor integrated circuit according to any one of claims 1 to 3. (5) The semiconductor integrated circuit according to any one of claims 1 to 4, wherein a common dart input is provided to corresponding elements between the first and second channel type MOS transistors. (6) The semiconductor integrated circuit according to any one of claims 1 to 4, wherein each of the MOS transistors is an enforcement type MO8) transistor. (7) Each MO8 above) Lannostar is desolation type M
O8) The semiconductor integrated circuit according to any one of claims 1 to 4, which is a runnostar. (8) Each of the above memory parts consists of several MOSs.
) A MOS with transistors arranged in a matrix.) Consisting of a group of transistors lol! The semiconductor integrated circuit according to claim 2 or 3, wherein hta.