JPS5948110U - double multiplier - Google Patents

double multiplier

Info

Publication number
JPS5948110U
JPS5948110U JP14206482U JP14206482U JPS5948110U JP S5948110 U JPS5948110 U JP S5948110U JP 14206482 U JP14206482 U JP 14206482U JP 14206482 U JP14206482 U JP 14206482U JP S5948110 U JPS5948110 U JP S5948110U
Authority
JP
Japan
Prior art keywords
power divider
power
doubler
amplifier
double multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14206482U
Other languages
Japanese (ja)
Inventor
好孜 町野
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP14206482U priority Critical patent/JPS5948110U/en
Publication of JPS5948110U publication Critical patent/JPS5948110U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の基礎となる2逓倍器の構成概念図、
第2図は電力分配器の出力波形を示す図、第3図は増幅
器の出力波形を示す図、第4図は電力合成器の出力波形
を示す図、第5図は従来の2逓倍器の構成図、第6図は
この考案による2逓倍器の構成図、第7図はこの考案に
使用した分配器の機能図、第8図はこの考案に使用した
合成器の機能図であり図中1は電力分配器、2はB級増
幅器、3は電力合成器、4は平行3線電力分配器、5は
Y形電力合成器、6はスロット線路電力分配器、7はス
ロット線路電力合成器、8はマイクロストリップ線路、
9はスロット線路である。なお、図中同一あるいは相当
部分には同一符号を付して示しである。 8・−n了ソ尤− ”。・TdY凸了し  A 第4図 − / 4   l              1J−+。 、J−1+    、。 1     、L、−−一−−−−−−J     °
 D1 r−−一 −−−−−−−−qi         ’
11”     I :: +1 1IIIL−一−−−−−−−」 暮 11 L       −−:Il 1   、     1
Figure 1 is a conceptual diagram of the structure of a doubler, which is the basis of this invention.
Figure 2 shows the output waveform of the power divider, Figure 3 shows the output waveform of the amplifier, Figure 4 shows the output waveform of the power combiner, and Figure 5 shows the output waveform of the conventional doubler. Fig. 6 is a block diagram of the doubler according to this invention, Fig. 7 is a functional diagram of the distributor used in this invention, and Fig. 8 is a functional diagram of the combiner used in this invention. 1 is a power divider, 2 is a class B amplifier, 3 is a power combiner, 4 is a parallel three-wire power divider, 5 is a Y-type power combiner, 6 is a slot line power divider, 7 is a slot line power combiner , 8 is a microstrip line,
9 is a slot line. Note that the same or equivalent parts in the figures are indicated by the same reference numerals. 8.-n completed so- ”.・TdY convex completed A Fig. 4- / 4 l 1J-+., J-1+,. 1, L,--1-------J °
D1 r--1 ----------qi'
11" I:: +1 1IIIL-1-------" 11 L --: Il 1, 1

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号を2分配するとともに分配後の信号位相差が180
°となる電力分配器と、この電力分配器の二つの出力端
それぞれに接続されたB級増幅器と、この増幅器による
増幅後の二つの出力信号を同相で合成する電力合成器か
らなる2逓倍器において、電力分配器および電力合成器
にスロット線路を用いたことを特徴とする2逓倍器。
The signal is divided into two and the signal phase difference after distribution is 180
A doubler consisting of a power divider, a class B amplifier connected to each of the two output terminals of this power divider, and a power combiner that combines the two output signals amplified by this amplifier in phase. A doubler characterized in that a slot line is used for a power divider and a power combiner.
JP14206482U 1982-09-20 1982-09-20 double multiplier Pending JPS5948110U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14206482U JPS5948110U (en) 1982-09-20 1982-09-20 double multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14206482U JPS5948110U (en) 1982-09-20 1982-09-20 double multiplier

Publications (1)

Publication Number Publication Date
JPS5948110U true JPS5948110U (en) 1984-03-30

Family

ID=30317548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14206482U Pending JPS5948110U (en) 1982-09-20 1982-09-20 double multiplier

Country Status (1)

Country Link
JP (1) JPS5948110U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115717A (en) * 2001-10-03 2003-04-18 Nippon Dempa Kogyo Co Ltd Multi-element planar antenna
JP6109452B1 (en) * 2016-06-13 2017-04-05 三菱電機株式会社 High frequency rectifier

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115717A (en) * 2001-10-03 2003-04-18 Nippon Dempa Kogyo Co Ltd Multi-element planar antenna
JP6109452B1 (en) * 2016-06-13 2017-04-05 三菱電機株式会社 High frequency rectifier
WO2017216839A1 (en) * 2016-06-13 2017-12-21 三菱電機株式会社 High frequency rectifier
KR20180136558A (en) * 2016-06-13 2018-12-24 미쓰비시덴키 가부시키가이샤 High frequency rectifier
EP3447897A4 (en) * 2016-06-13 2019-05-22 Mitsubishi Electric Corporation High frequency rectifier
US10811991B2 (en) 2016-06-13 2020-10-20 Mitsubishi Electric Corporation High frequency rectifier

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