JPS5946335U - electronic flash device - Google Patents
electronic flash deviceInfo
- Publication number
- JPS5946335U JPS5946335U JP10936683U JP10936683U JPS5946335U JP S5946335 U JPS5946335 U JP S5946335U JP 10936683 U JP10936683 U JP 10936683U JP 10936683 U JP10936683 U JP 10936683U JP S5946335 U JPS5946335 U JP S5946335U
- Authority
- JP
- Japan
- Prior art keywords
- light
- detector
- input
- flash
- predetermined value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Exposure Control For Cameras (AREA)
- Stroboscope Apparatuses (AREA)
- Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の電子フラッシュ装置の実施例を示す
ブロック図である。第２図は、本考案の電子フラッシュ
装置に含まれる光デイジタル化回路の好適実施例の回路
図である。第３図は、第２図の回路の時間に対する電圧
レベルを示すグラフである。第４図は、本考案の電子フ
ラッシュ装置に含まれる光デイジタル化回路の他の好適
実施例の回路図である。第５図は、第４図の回路の時間
に対する電圧レベルを示すグラフである。第６図は、本
考案の電子フラッシュ装置に含まれる光デイジタル化回
路の他の好適実施例の回路図である。
第７図は、本考案の電子フラッシュの実施例の回路図で
ある。第８図、第７図の時間に対する信号レベルを示す
グラフである。
（符号説明）、１１・・・・・・フラッシュ・バルブ、
１３・・・・・・トリガ回路、１７・・・・・・フラッ
シュ終止回路、２１・・・・・・制御回路、２３・・・
・・・光センサ、２５・・・光デイジタル化回路、３１
・・・・・・カウンタ、３５・・・・・・論理回路、３
９・・・・・・ホトダ不オード。
」
” Ｔ
簗、３閃
濁FIG. 1 is a block diagram showing an embodiment of the electronic flash device of the present invention. FIG. 2 is a circuit diagram of a preferred embodiment of the optical digitization circuit included in the electronic flash device of the present invention. FIG. 3 is a graph showing voltage level versus time for the circuit of FIG. FIG. 4 is a circuit diagram of another preferred embodiment of the optical digitization circuit included in the electronic flash device of the present invention. FIG. 5 is a graph showing voltage level versus time for the circuit of FIG. FIG. 6 is a circuit diagram of another preferred embodiment of the optical digitization circuit included in the electronic flash device of the present invention. FIG. 7 is a circuit diagram of an embodiment of the electronic flash of the present invention. 8 is a graph showing the signal level versus time in FIGS. 8 and 7; FIG. (Explanation of symbols), 11...Flash bulb,
13...Trigger circuit, 17...Flash termination circuit, 21...Control circuit, 23...
... Optical sensor, 25 ... Optical digitization circuit, 31
...Counter, 35...Logic circuit, 3
9...Hotoda failure. ” ” T Yan, 3 flashes
Claims (1)
受けた閃光の強さに応じた出力信号を発生するため露光
するように配置された光センサと、前記光センサに接続
され前記出力信号に応じて充電して前記光センサが受け
た光エネルギー量を表わす電圧出力を発生するコンデン
サと、前記電圧出力を入力として受けるように接続され
る入力ヒステリシスを有する電圧レベル検出器であって
、入力の電圧に従って高出力又は低出力を出力する検出
器と、該検出器出力に接続され、該検出器の入力レベル
が所定値に達した時前記コンデンサを放電させる手段と
、前記検出器からのパルス信号数が所定値に達した時前
記コンデンサを放電させる手段と、前記検出器からのパ
ルス信号数が所定値に達した時に前記フラッシュバルブ
からの光を終止させる手段を有することを特徴とする電
子フラッシュ装置。A flash bulb that generates a flash of light that illuminates the subject,
a light sensor arranged to be exposed to light to generate an output signal responsive to the intensity of the flash of light received; and an amount of light energy received by the light sensor connected to the light sensor and charged in response to the output signal. a voltage level detector having an input hysteresis connected to receive the voltage output as an input, the detector outputting a high or low output depending on the voltage of the input; means connected to the detector output to discharge the capacitor when the input level of the detector reaches a predetermined value; and means to discharge the capacitor when the number of pulse signals from the detector reaches a predetermined value. and means for terminating light from the flash bulb when the number of pulse signals from the detector reaches a predetermined value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10936683U JPS5946335U (en) | 1979-01-04 | 1983-07-14 | electronic flash device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US999 | 1979-01-04 | ||
| JP10936683U JPS5946335U (en) | 1979-01-04 | 1983-07-14 | electronic flash device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5946335U true JPS5946335U (en) | 1984-03-27 |
| JPH0216347Y2 JPH0216347Y2 (en) | 1990-05-07 |
Family
ID=30254792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10936683U Granted JPS5946335U (en) | 1979-01-04 | 1983-07-14 | electronic flash device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5946335U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015206776A (en) * | 2014-04-19 | 2015-11-19 | 正雄 佐藤 | Combined device of three diodes and resistor |
-
1983
- 1983-07-14 JP JP10936683U patent/JPS5946335U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015206776A (en) * | 2014-04-19 | 2015-11-19 | 正雄 佐藤 | Combined device of three diodes and resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0216347Y2 (en) | 1990-05-07 |
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