JPS5945485A - Display panel - Google Patents
Display panelInfo
- Publication number
- JPS5945485A JPS5945485A JP57156207A JP15620782A JPS5945485A JP S5945485 A JPS5945485 A JP S5945485A JP 57156207 A JP57156207 A JP 57156207A JP 15620782 A JP15620782 A JP 15620782A JP S5945485 A JPS5945485 A JP S5945485A
- Authority
- JP
- Japan
- Prior art keywords
- display panel
- single crystal
- substrate
- circuit
- crystal substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、映像信号のドフィバー回路奮有するsi単結
晶基板と、画像表示するTPT基板を、有効に実+しし
7た、高コントラスト表示パネルに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-contrast display panel that effectively incorporates a Si single-crystal substrate with a diffuser circuit for video signals and a TPT substrate for image display.
従来、コントラストの高いTN液晶で表示する場合には
、液晶と画素電極を、2枚の偏光板に挾み、下偏光板の
下に反射板をおく構造に限定される為、画素電極塞板は
、透明であることが要求される。該TPT基板は、結晶
性の不完全性から、高速トランジスタ全内蔵することが
一1+ft 1/−0一方Si単結晶においては、高速
シフトレジスタの内蔵は可能であるが、不透明である為
、イ(4光板を画素電極下に入りることか出来ず、TN
液晶を使用出来ない。この為、コントラストの低い例え
ば、ゲスト−ホスト液晶による表示しか出来なかった。Conventionally, when displaying with a high-contrast TN liquid crystal, the liquid crystal and pixel electrode were sandwiched between two polarizing plates, and the structure was limited to placing a reflector under the lower polarizing plate, so the pixel electrode cover was required. is required to be transparent. Due to imperfect crystallinity, the TPT substrate cannot accommodate all high-speed transistors (1+ft 1/-0). On the other hand, with Si single crystal, it is possible to incorporate a high-speed shift register, but since it is opaque, it is difficult to integrate high-speed transistors. (The 4-light plate could not be placed under the pixel electrode, so the TN
LCD cannot be used. For this reason, only low-contrast, for example, guest-host liquid crystal display could be used.
本発明はこ′i]、らの両者の持つ欠点を解消し、高コ
ントラストでコンパクトな表示パネルを提供するもので
ある。The present invention eliminates both of these drawbacks and provides a compact display panel with high contrast.
以下本発明を実施例をもって説明する。The present invention will be explained below with reference to examples.
実/J毎例1
第1図は、本発明表示パネルの一例を示したものであり
、1の」二偏光板、2のガラス、3の品行処理層、4T
N液晶、5の封止剤よシなる液晶%llと透明石英6.
マトリックス状のl・ヲンジスタ、容量、透明電極7よ
りなるT F’ T表示基板、さらに、下偏光板82反
射板9.と、映像信号をドフィブする回路11ff有し
たSi単結晶基板10.及び該シフ1−レジスクのX−
Y出力12ヲ、上層のTF”?it イ似ヘワイヤボン
デイング結線j3する構造で形成さり、ている。イ11
)元板全通過した偏光は、画素電極がOF F′時に&
J、偏光軸が」−下側光方向と一致する為、白くONす
ると、90α、1転し、クロスニコル状態となって、コ
ントラスト表示出来る。8 iノ1(冬板上にイiQ層
して、結線する方法d、コンパクトで信頼性も高い。Actual/J Example 1 Figure 1 shows an example of the display panel of the present invention, which includes 1' bi-polarizing plate, 2 glass, 3 quality treatment layer, and 4T.
N liquid crystal, 5% liquid crystal with encapsulant and transparent quartz 6.
A T F' T display substrate consisting of a matrix-like l-on register, a capacitor, and a transparent electrode 7 , and a lower polarizing plate 82 and a reflecting plate 9 . and a Si single crystal substrate 10 having a circuit 11ff for converting the video signal. and the X- of the Schiff 1-resic
The Y output 12 is formed with a wire bonding connection j3 to the upper layer TF"?it A11.
) When the pixel electrode is OFF, the polarized light that has completely passed through the original plate is &
J, since the polarization axis coincides with the lower light direction, when the light is turned on in white, it turns 90α, turns 1, and becomes a crossed nicol state, allowing contrast display. 8 i-1 (Method of laying i-iQ layer on the winter board and connecting wires d, compact and highly reliable.
実施例2
第2図は、Si単結晶内の、シフトレジスタ以外の部分
に、fi<E乱性反射面14f形成し、反射板9を、S
i単結晶に内蔵した4’l+¥造である。Embodiment 2 In FIG. 2, a fi<E disordered reflection surface 14f is formed in a portion of the Si single crystal other than the shift register, and the reflection plate 9 is
It is a 4'l + ¥ structure built into the i single crystal.
該方式は、反射板を取9除くことが出来、薄型化を可能
とした。又、シフトレジスタからの結線をフィルムキャ
リア方式15によるギヤングボンデングで行うことによ
り、合j、+4!化、高イdね化を図った1゜又、Si
単結晶基板として、従来のシフトレジスタ内蔵のアクテ
ィブパネルを使用しても、実施例2と同等の効果が確認
出来、従来のアクティブパネルのシフトレジスタ良品で
画素欠陥がアルハネル、の有効活用も可能となった。With this method, the reflective plate could be removed, making it possible to make the device thinner. Also, by connecting the wires from the shift register by Guyang bonding using the film carrier method 15, the total j, +4! 1゜Also, Si
Even if a conventional active panel with a built-in shift register is used as a single crystal substrate, the same effect as in Example 2 can be confirmed, and it is also possible to effectively utilize a conventional active panel with a good shift register but no pixel defects. became.
第3図に、本発明の概略結線図を示す。FIG. 3 shows a schematic wiring diagram of the present invention.
X、Yレジスタ内蔵のSz’単結晶基板16と、画素駆
動用トランジスタ2()、容f′(′i−,21よりな
るTFT基板19は、ボンディング18結線されている
。An Sz' single crystal substrate 16 with built-in X and Y registers, and a TFT substrate 19 consisting of a pixel driving transistor 2() and a capacitor f'('i-, 21) are connected by bonding 18.
本発明では、X、Yシフトレジスタ共、Si単結晶内に
含んだが、Xだけでも可能であるし、必ずしも、2個づ
つシフトレジスタをもつ必要もない。又T F Tも、
石英基板上へのPO,[Y−8iデボ方式でも、アモル
ファスSZ’方式でも良いし、単なる上下電極方式でも
良い。In the present invention, both the X and Y shift registers are included in the Si single crystal, but it is also possible to use only the X, and it is not necessarily necessary to have two shift registers each. Also, T F T
PO on a quartz substrate, [Y-8i debo method, amorphous SZ' method, or simply upper and lower electrode method may be used.
第1,2図は本発明衣ボハ坏ルの概略図である。
第3図は、本発明表示パネルの結線図である。
1:偏′)’c、板 2:ガラス板 3:前行処理層4
:TNi晶 5:封止剤 6:TFT基板7:画素電極
8:偏光板 9:反射板+(1: S i単結晶基板
11:ドフィノ々−回路12:電極 13
:ワイヤホント。
14 : S i単結晶基板内蔵反射オル15:フィル
ムキャリアボンディング
16:8j単結晶基板 17:トヲンスミツシヨンゲー
トトヲンジスタ 18:ボンデインク゛19: T F
’ T基板 20:画素トランジスタ21:コンデ
ンサー 22:液晶
以 」二
出願人 株式会社諏Wb鞘工舎
代岬人 弁理士 最 上 務Figures 1 and 2 are schematic diagrams of the present invention. FIG. 3 is a wiring diagram of the display panel of the present invention. 1: Polarized ')'c, plate 2: Glass plate 3: Pre-treatment layer 4
: TNi crystal 5: Encapsulant 6: TFT substrate 7: Pixel electrode 8: Polarizing plate 9: Reflector + (1: Si single crystal substrate 11: Dofino circuit 12: Electrode 13
: Wire true. 14: Reflector with built-in Si single crystal substrate 15: Film carrier bonding 16: 8j single crystal substrate 17: Power transmission gate resistor 18: Bonding ink 19: T F
``T board 20: Pixel transistor 21: Capacitor 22: Liquid crystal'' 2nd Applicant Suwa Wb Co., Ltd. Sayakoshayo Misaki Patent attorney Tsutomu Mogami
Claims (1)
像信号を送る回路を有する5cLl¥i結晶基板上に、
該信号を受けて画像表示する透過型TPT(THエト−
F工LM TRANS工S T OR) f、H積層
し、両者を結線して表示するとと全特徴とした表示パネ
ル。 f21 映像信号を送る回路を有するSi単結晶基板
内に、散乱性反射面全イラすることを特徴とした第一項
り己載の表示パネル。[Claims] C)) On a 5cLl\i crystal substrate having a circuit for sending a video signal in a liquid crystal display panel having a semiconductor circuit,
Transmissive TPT (TH etho) receives the signal and displays an image.
F engineering LM TRANS engineering S T OR) A display panel that has all the characteristics of laminating f and H and connecting both for display. f21 A display panel mounted on a Si single crystal substrate having a circuit for transmitting a video signal and having a scattering reflective surface all over it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57156207A JPS5945485A (en) | 1982-09-07 | 1982-09-07 | Display panel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57156207A JPS5945485A (en) | 1982-09-07 | 1982-09-07 | Display panel |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5945485A true JPS5945485A (en) | 1984-03-14 |
Family
ID=15622705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57156207A Pending JPS5945485A (en) | 1982-09-07 | 1982-09-07 | Display panel |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5945485A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54154992A (en) * | 1978-05-29 | 1979-12-06 | Seiko Epson Corp | Semiconductor electrode substrate for liquid crystal panel drive |
JPS576282A (en) * | 1980-06-14 | 1982-01-13 | Kobe Steel Ltd | Air separator |
-
1982
- 1982-09-07 JP JP57156207A patent/JPS5945485A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54154992A (en) * | 1978-05-29 | 1979-12-06 | Seiko Epson Corp | Semiconductor electrode substrate for liquid crystal panel drive |
JPS576282A (en) * | 1980-06-14 | 1982-01-13 | Kobe Steel Ltd | Air separator |
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