JP3288989B2 - Flat panel display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device, and more particularly to a structure of a flat display device which can be made thin.

[0002]

2. Description of the Related Art A flat display device represented by a liquid crystal display device has been used in various fields by utilizing its features of light weight, thinness, and low power consumption. Among them, liquid crystal display devices are frequently used in portable information devices represented by personal computers.

In recent years, such liquid crystal display devices have been required to be further reduced in thickness.

[0004]

In order to satisfy such a demand, an external circuit is reduced by integrally forming a drive circuit on one of the substrates constituting the liquid crystal display device, thereby reducing the thickness of the liquid crystal display device. Attempts have been made to achieve this.

[0005] However, even in such a configuration, the external circuit has not been completely integrated, and some external circuits have to be provided at present.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a flat display device which can achieve a further reduction in thickness.

[0007]

The above-mentioned problems SUMMARY OF THE INVENTION In order to achieve the solution to the purpose, the flat panel display device according to claim 1, each other
A plurality of signal lines and scanning lines substantially orthogonal to each other, and the signal
Switch element arranged near the intersection of a line and the scanning line
And a pixel electrode arranged via
Scanning line driving circuit section, and a signal line connected to the signal line
A drive circuit section, wherein the switch element, the scan line
The driving circuit unit and the signal line driving circuit unit are each a polycrystalline silicon.
A display panel including an electrode substrate formed of a thin film transistor including a recon film, a drive circuit substrate on which components are mounted and supplying a drive signal to the electrode substrate of the display panel, the electrode substrate and the drive circuit substrate, A light guide plate disposed on the back side of the display panel; and a surface light source unit including a tubular light source disposed such that one end surface of the light guide plate is an incident end surface. a flat display device, the other end surface opposite to the one end face of the light guide plate, said a thinner than the one end surface, the drive circuit board, the electrode substrate along the other end face of the light guide plate To
The signal lines of the electrode substrate
The drive circuit unit has an end surface orthogonal to the one end surface of the light guide plate.
And the connecting portion is connected to the one of the light guide plates.
Connected to the electrode substrate on the side along the end face orthogonal to the end face.
It is characterized by having.

[0008]

According to the flat display device of the present invention, the drive circuit board is arranged along the other end surface which is thinner than one end surface of the light guide plate, thereby preventing the device from being made thin.
Further, since a part of the drive circuit is formed integrally on the electrode substrate of the display panel, the circuit substrate area can be reduced, so that the frame size is not significantly reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the flat panel display according to the present invention will be described with reference to the drawings.

As shown in FIGS. 1 and 2, the liquid crystal display device 1 includes a liquid crystal panel 100 and the liquid crystal panel 100.
And a bezel 900 for holding the liquid crystal panel 100 between the surface light source unit 800 and a driving circuit board 500 that supplies a driving signal to the liquid crystal panel 100. Then, the liquid crystal panel 100 and the drive circuit board 500 are electrically connected via the flexible wiring board 950.

More specifically, this liquid crystal panel 100
As shown in FIG. 4, an effective display area 102 conforming to the XGA specification having a display pixel of (1024 × 3) × 800 with a diagonal size of 12.1 inches is included. The liquid crystal panel 100
Array substrate 200, counter substrate 400, array substrate 2
TN (twisted nematic) liquid crystal layer 4 held between alignment layer 00 and counter substrate 400 via an alignment film, respectively.
10 is included.

The array substrate 200 is composed of 1024 × 3 signal lines Xi (i = 1) arranged in a matrix on a transparent insulating substrate 201 made of glass and having a thickness of 0.5 mm in order to achieve further reduction in thickness. , 2, ..., 1024 x 3) and 8
A switching element 211 composed of 00 scanning lines Yj (j = 1, 2,..., 800), a thin film transistor or a TFT disposed near the intersection of the signal line Xi and the scanning line Yj, and Pixel electrode 2 to be connected
13 is provided.

The switch element 211 includes a polycrystalline silicon film having a channel region 212c and a source region 212s and a drain region 212d interposed between the channel region 212c, that is, a p-Si film;
A gate insulating film 21 on the channel region 212c of the Si film;
4 and a gate electrode 215 electrically connected to the scanning line, and a source electrode 21 connected to the source region 212s and the drain region 212d, respectively.
6s and the drain electrode 216d.

The gate electrode 215 is connected to the scanning line Yj, the drain electrode 216d is connected to the signal line Xj, and the source electrode 216s is connected to the pixel electrode 213.

The pixel electrode 213 includes a transparent conductive member,
For example, an interlayer insulating film 217 and a passivation film 21 which are formed of ITO and are sequentially stacked on the TFT 211
8 and are disposed on the color filter layer CF. The interlayer insulating film 217 and the passivation film 218 are formed of silicon nitride. The pixel electrode 213 is covered with an alignment film 219 disposed over the entire effective display area 102.

The counter substrate 400 is made of glass
A counter electrode 403 facing the pixel electrode 213 is provided on a transparent insulating substrate 401 having a thickness of mm. The counter electrode 403 is formed of a transparent conductive member, for example, ITO, and is formed of an alignment film 4 disposed on the entire effective display area 102.
05.

Outer surface of array substrate 200 and counter substrate 40
A pair of polarizing plates 220 and 407 whose polarization directions are set in accordance with the characteristics of the liquid crystal layer 410 are provided on the outer surface of the liquid crystal layer 410.

Inside effective display area 102 and effective display area 1
02, a resin spacer 1 for forming a predetermined gap between the array substrate 200 and the counter substrate 400 is formed.
04 is arranged.

The array substrate 200 and the counter substrate 400 are
In a state where a predetermined gap is formed by the spacer 104, they are bonded by the sealant 106.

In the peripheral area of the effective display area 102, an integrated drive circuit section 110 is arranged.

That is, scanning line driving circuits 251 and 253 for supplying scanning pulses are provided at both ends of the scanning line Yj.
Is arranged. These scanning line driving circuits 251, 2
A shift register 53 sequentially transfers and outputs the vertical start pulse STV based on the vertical clock signal CPV.

On one end of the signal line Xi, a pair of signal line drive circuit units 261 and 263 are arranged. Since the configurations are substantially the same, the configuration of the signal line driver circuit portion 261 will be described here.

The signal line drive circuit section 261 includes a shift register 271 for sequentially transferring and outputting a horizontal start pulse STH based on a horizontal clock signal CPH. The output of the shift register 271 is guided to the logic circuit unit 281. Further, based on the output of the logic circuit unit 281, the analog sampling unit 291 samples predetermined analog video signals Video (+) and Video (-), and outputs them to the corresponding signal lines Xi.

The logic circuit unit 281 includes a set of OR gates 2
83, 285, a NAND gate 287, and a NOR gate 289.

The OR gate 283 is connected to a selection wiring to which the selection signal SW is supplied, and is connected to a first output terminal of the shift register 271 via an inverter circuit 284. The OR gate 285 is connected to a selection wiring to which the selection signal SW is supplied, and is also connected to a first output terminal of the shift register 271.

The OR gate 283 performs sampling of the positive-phase analog video signal Video (+) based on the selection signal SW and the signal output from the first output terminal.
A signal for controlling the gate of the pattern sampling TFT 293 is output. The OR gate 285 is configured to output the negative-phase analog video signal Video based on the selection signal SW and the signal output from the first output terminal via the inverter circuit 284.
N-type sampling TFT for sampling (-)
295 to output a signal for controlling the gate.

The NAND gate 287 is connected to a selection line to which the selection signal SW is supplied, and is also connected to a second output terminal of the shift register 271. NO
The R gate 289 is connected to a selection wiring to which the selection signal SW is supplied, and is connected to a second output terminal of the shift register 271 via an inverter circuit 288.

The NAND gate 287 performs sampling of the positive-phase analog video signal Video (+) based on the selection signal SW and the output signal from the second output terminal.
A signal for controlling the gate of the pattern sampling TFT 293 is output. The NOR gate 289 receives the negative-phase analog video signal Video based on the selection signal SW and the output signal from the second output terminal via the inverter circuit 288.
N-type sampling TFT for sampling (-)
295 to output a signal for controlling the gate.

According to the above configuration, since the analog video signal Video supplied from the outside can be separated into at least a positive phase and a negative phase and wired on the substrate, power consumption can be reduced, and the waveform of the analog video signal Video can be further reduced. There is no deterioration. In this embodiment, the pair of signal line drive circuits 261 and 263 are arranged so as to divide the signal line Xi into two in order to shorten the wiring length for transmitting the analog video signal Video on the substrate. In addition, this is because the respective processing times are set to be substantially long by operating them in parallel. Here, it is divided into two, but it can be set to three or more.

Further, with the above configuration, the analog video signal Video can be wired on the substrate while being separated into a positive phase and a negative phase, and the polarity can be inverted for each adjacent signal line Xi. Thereby, flicker can also be reduced.

A digital video signal Video and a system clock signal CK are externally input to a driving circuit board 500 for driving the liquid crystal panel 100. The control circuit G / A 511 controls the digital video signal V
The video is distributed to the positive and negative digital / analog conversion circuits 521 and 523 based on the system clock signal CK.

The positive digital / analog conversion circuit 521
Divides the distributed digital video signal Video from 5 to 1
The signal is converted to a positive-phase analog video signal Video (+) in the range of 0V. Negative digital / analog conversion circuit 523
Indicates that the distributed digital video signal Video is 0 to 5
The signal is converted into a negative-phase analog video signal Video (-) in the range of V. Then, in the distribution circuit 531, the outputs of the positive-side digital / analog conversion circuit 521 and the negative-side digital / analog conversion circuit 523 are guided to the positive and negative phase transmission lines, respectively.

In this embodiment, in order to achieve a reduction in the thickness of the device, an IVH
A substrate 551 having an (Interstitial Via Hole) structure is used. The control circuit G / A 511 and the digital / analog conversion circuits 521 and 523
(Chip Size Package) structure is used.

As shown in FIG. 5, a substrate 551 having an IVH structure has a plurality of layers of copper foils 561, 563, 565, 567,
569 are laminated via insulating materials 571, 572, 573, and 574, and the copper paste 561,.
583, 585, 587 are electrically connected. Therefore, the mounting density can be increased.

The CSP structure has a structure as shown in FIG.
A substrate on which a semiconductor chip is mounted face-up or face-down is connected by bumps formed of solder balls or the like. The size can be sufficiently reduced, and narrow-pitch connection is possible.

Further, in this embodiment, as shown in FIG. 5, C is used to further reduce the size and thickness.
The control circuit G / A 511 having the SP structure is connected to the substrate 5
The copper foil 56 of the inner phase is embedded in a groove 591 provided in
3 is electrically connected.

In this embodiment, as shown in FIG. 1 and FIG. 2, the tubular light source 811 of the surface light source section 800 is connected to one end face of the liquid crystal panel 100 in the short direction, that is, one side of the scanning line driving circuit 253 side. It is arranged along the end face. The circuit board 500 includes the liquid crystal panel 1 facing the tubular light source 811.
00 is arranged along the short-side end face, ie, the other end face on the scanning line drive circuit 251 side.

On the back side of the liquid crystal panel 100, a light guide plate 821 of the surface light source unit 800 held by the frame 831 is arranged. This light guide plate 821 has a thickness of about 2.0 m.
m thick portion 821A and a thin portion 8 having a thickness of about 0.8 mm
21B is formed of a wedge-shaped acrylic resin. The tubular light source 811 is disposed on one end surface of the thick portion 821A of the light guide plate 821. Circuit board 500
Are arranged along the other end surface of the thin portion 821B of the light guide plate 821.

The light emitted from the tubular light source 811 enters the light guide plate 821 from the incident end face 821C on the thick portion 821A side, and propagates inside the light guide plate 821. On the back surface of the light guide plate 821, a reflection sheet (not shown) is disposed, and the light guide plate 8
The light leaking from 21 to the back surface is reflected again toward the light guide plate 821. The light that has propagated through the entire light guide plate 821 is emitted from the emission surface 821D facing the liquid crystal panel 100. Light emitted from the emission surface 821D is given predetermined optical characteristics by an optical sheet, for example, a diffusion sheet or a prism sheet, interposed between the light guide plate 821 and the liquid crystal panel 100. Incident on the side.

Light incident on the liquid crystal panel 200 is modulated by the liquid crystal layer 410 controlled by an electric field between the pixel electrode 213 and the counter electrode 403, and is selectively transmitted for each display pixel to form a display image. .

As described above, in the liquid crystal display device 1 of this embodiment, a part of the drive circuit is integrally formed on the array substrate 200. Therefore, the external circuit scale can be reduced as compared with the conventional case. Moreover, the substrate 51 having the IVH structure
1 and the CSP structure are effectively combined, so that the circuit board 500 can be reduced in size and thickness.

Further, in this embodiment, the drive circuit board 500 that achieves such miniaturization and thickness reduction is arranged along the short direction of the liquid crystal panel 100, that is, along the scanning line drive circuit 251 side. For this reason, the thickness of the entire apparatus can be sufficiently reduced.

Further, the side on which the circuit board 500 is disposed is the thinner portion 821B side of the wedge-shaped light guide plate 821, and the circuit board 5 is larger than the sum of the thickness of the liquid crystal panel 100 and the thickness of the light guide plate 821.
00 is formed to be thin, so that the wedge-shaped light guide plate 82
The one thin portion 821B side can be formed extremely thin.

In this embodiment, the circuit board 500 is arranged along the outer periphery of the end surface of the liquid crystal panel 100 on the scanning line drive circuit 251 side.
It may be arranged so as to overlap the thin portion 821B. That is, as shown in FIGS. 6 and 7, the thickness of the circuit board 500 is smaller than the difference in thickness between the thick portion 821A and the thin portion 821B of the light guide plate 821. For this reason, the circuit board 500 is moved along the end portion of the thin portion 821B of the light guide plate 821.
, The liquid crystal display device 1 can be formed extremely thin, and the frame width can be reduced.

Although the above embodiment has been described by taking a liquid crystal display device as an example, other display panels can be used.

[0047]

As described above, according to the present invention, it is possible to provide a very thin display device even if the drive circuit is not completely integrated on the substrate constituting the display device. Becomes

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a liquid crystal display device according to an embodiment of the flat panel display device of the present invention.

FIG. 2 is a schematic sectional view of the liquid crystal display device shown in FIG. 1 taken along the line II-II.

FIG. 3 is a schematic sectional view of a liquid crystal panel applied to the liquid crystal display device shown in FIG.

FIG. 4 is a diagram showing an equivalent circuit of the liquid crystal display device shown in FIG. 1;

5 is a schematic sectional view of a circuit board applied to the liquid crystal display device shown in FIG. 1,

FIG. 6 is a schematic perspective view of a liquid crystal display device according to another embodiment of the flat panel display device of the present invention.

FIG. 7 is a sectional view of the liquid crystal display device shown in FIG.
It is the schematic sectional drawing cut | disconnected along the line.

[Explanation of symbols]

 Reference Signs List 100 liquid crystal panel 102 effective display area 200 array substrate 400 counter substrate 410 TN liquid crystal layer 500 driving circuit board 800 surface light source 950 flexible wiring board

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tomio Makino 7-1, Nisshincho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Electronic Engineering Corporation (56) References JP-A-6-273789 (JP, A) JP-A Heisei JP-A-7-131030 (JP, A) JP-A-8-255981 (JP, A) JP-A-10-170953 (JP, A) JP-A-9-146113 (JP, A) A) JP-A-11-149251 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09F 9/00 G02F 1/133

Claims (5)

(57) [Claims] 1. A plurality of signal lines and scanning that are substantially orthogonal to each other.
A scanning line, and the signal line and the scanning line.
A pixel electrode disposed via a switching element
A scanning line driving circuit portion connected to the scanning line;
A signal line driving circuit section connected to the
Element, the scanning line driving circuit section, and the signal line driving circuit
The part is a thin film transistor containing a polycrystalline silicon film
A display panel having the configured electrode substrate, a drive circuit board on which components are mounted and supplying a drive signal to the electrode substrate of the display panel, and a connection for electrically connecting the electrode substrate and the drive circuit board and parts, a flat display device including a surface light source unit, a containing tubular light source arranged to the rear surface side positioned light guide panel and the one end face of the light guide plate and the incident end face of the display panel The other end face of the light guide plate facing the one end face is thinner than the one end face, and the drive circuit board is substantially parallel to the electrode board along the other end face of the light guide plate.
And the signal line driving circuit section of the electrode substrate is provided on the light guide plate.
The connection portion is disposed along an end surface orthogonal to the one end surface, and the connection portion is an end surface orthogonal to the one end surface of the light guide plate.
A flat display device connected to the electrode substrate on a side along the line . 2. The flat display device according to claim 1, wherein the thickness of the drive circuit board is smaller than the sum of the thickness of the display panel and the thickness of the other end face of the light guide plate. 3. The flat display device according to claim 1, wherein the drive circuit board has an IVH structure. 4. The signal line driving circuit sections operate in parallel with each other.
Including a plurality of signal line drive circuit blocks
The flat panel display according to claim 1. 5. A shift register according to claim 1, wherein said signal line driving circuit is a shift register.
A video bus line for supplying a video signal;
It is supplied to the video bus wiring based on the register output.
Sample the video signal and output it to the signal line.
And a sampling circuit.
Item 2. The flat panel display according to item 1.