JPS5944900A - Circuit board device - Google Patents

Circuit board device

Info

Publication number
JPS5944900A
JPS5944900A JP15603282A JP15603282A JPS5944900A JP S5944900 A JPS5944900 A JP S5944900A JP 15603282 A JP15603282 A JP 15603282A JP 15603282 A JP15603282 A JP 15603282A JP S5944900 A JPS5944900 A JP S5944900A
Authority
JP
Japan
Prior art keywords
solder
electronic component
board
layer
board device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15603282A
Other languages
Japanese (ja)
Inventor
相川 昇
井窪 正紘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15603282A priority Critical patent/JPS5944900A/en
Publication of JPS5944900A publication Critical patent/JPS5944900A/en
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はテレビジョン受像機等に使用される配線基板装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a wiring board device used in television receivers and the like.

従来例の構成とその問題点 第1図は従来例における配線基板装置を示すものであり
、基板1の脚挿入孔2に電子部品3の脚4を挿入し、基
板1の裏面の導電体6に脚4を半田6によシ固定する。
Structure of a conventional example and its problems FIG. 1 shows a wiring board device in a conventional example, in which the legs 4 of an electronic component 3 are inserted into the leg insertion holes 2 of a board 1, and the conductor 6 on the back side of the board 1 is inserted into the leg insertion hole 2 of the board 1. Fix the legs 4 with solder 6.

このように取付けられた電子部品3を基板1から取外す
ためには、半田6を溶融し、電子部品3を引き抜く必要
がある。電子部品3の脚4の数が多い場合には、すべて
の半田を一度に溶融するのが困難であり、部品3の取外
しに手間を要する欠点がある。
In order to remove the electronic component 3 attached in this manner from the board 1, it is necessary to melt the solder 6 and pull out the electronic component 3. When the number of legs 4 of the electronic component 3 is large, it is difficult to melt all the solder at once, and there is a disadvantage that removing the component 3 requires time and effort.

発明の目的 本発明は上記欠点を除去し、容易に半田を溶剤tして電
子部品を取外すことができるようにしようとするもので
ある。
OBJECTS OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks and to make it possible to easily remove solder by dissolving the solder into a solvent and removing electronic components.

発明の構成 本発明は基板の脚挿入孔の周囲に抵抗体層を設け、その
上に絶縁体層を介して半田付可能な導電体層を設けたも
のであり、抵抗体層に電流を流すことによって発熱させ
、半田を溶融するようにしたものである。
Structure of the Invention The present invention provides a resistor layer around the leg insertion hole of a board, and a solderable conductor layer is provided on the resistor layer through an insulator layer, and current is passed through the resistor layer. This generates heat and melts the solder.

実施例の説明 以下本発明の一実施例について図面を参l@シて説明す
る。第2図〜第4図に示すように樹月旨あるいはセラミ
ック等で構成された基板7に電子¥!i1品の脚I諏入
孔8を設ける。基板7の裏面に訃ける脚挿入孔8の周囲
に抵抗体層9を焼成によって設ける。この抵抗体層9に
は導電体10a、10bを介して端子11a、11bが
接続されている。抵抗体層9の上には絶縁層12を介し
て半田付可能な導電層13を設けて赴く。この導電層1
3の上vCil−1Iあらかじめ半田14を溶着してお
く。電子部品16の脚16を脚挿入孔8に挿入した状態
で、抵抗体層9に電流を流し、半田14を溶融し7、脚
16を導電体13に接続し、固定する。電子部品16を
基板7よシ取外す場合には抵抗体9に電流を流し、半田
14を溶融し、脚16を半田14より引き抜けばよい。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in FIGS. 2 to 4, the electronic ¥! A leg I entry hole 8 is provided for the I1 product. A resistor layer 9 is provided around the leg insertion hole 8 on the back surface of the substrate 7 by firing. Terminals 11a and 11b are connected to this resistor layer 9 via conductors 10a and 10b. A solderable conductive layer 13 is provided on the resistor layer 9 via an insulating layer 12. This conductive layer 1
3. Solder 14 is welded on vCil-1I in advance. With the leg 16 of the electronic component 16 inserted into the leg insertion hole 8, a current is applied to the resistor layer 9 to melt the solder 14 7, and the leg 16 is connected to the conductor 13 and fixed. In order to remove the electronic component 16 from the board 7, a current may be applied to the resistor 9 to melt the solder 14, and the legs 16 may be pulled out from the solder 14.

電子部品16の脚16が多い場合でも、すべての半田を
一度に溶融することができるので、取外しはきわめて容
易に行うことができる。
Even if the electronic component 16 has many legs 16, all the solder can be melted at once, so removal can be performed extremely easily.

発明の効果 以上のように本発明によれば、半田を一度に溶融するこ
とができるので電子部品の取外しをきわめて容易に行う
ことができるものである。
Effects of the Invention As described above, according to the present invention, since the solder can be melted at once, it is possible to remove the electronic component extremely easily.

【図面の簡単な説明】 第1図は従来例における配線基板装置の断正面図、第2
図は本発明の一実施例における配線基板装置の断正面図
、第3図は同装置の一部分の拡大断面、第4図は同装置
の平面図である。 了・・・・・・基板、8・・・・・・脚挿入孔、9・・
・・・・抵抗体層、10a、10b・・・・・・導電体
、11a、11b・・・・・・端子、12・・・・・・
絶縁層、13・・・・・・導電層、14・・・・・・半
田、15・・・・・・電子部品、16・・・・・・脚。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第3図 第4図
[Brief explanation of the drawings] Figure 1 is a cross-sectional front view of a conventional wiring board device;
The figure is a sectional front view of a wiring board device according to an embodiment of the present invention, FIG. 3 is an enlarged sectional view of a portion of the device, and FIG. 4 is a plan view of the device. Completed... Board, 8... Leg insertion hole, 9...
...Resistor layer, 10a, 10b...Conductor, 11a, 11b...Terminal, 12...
Insulating layer, 13... Conductive layer, 14... Solder, 15... Electronic component, 16... Leg. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 基板に電子部品の脚挿入孔を形成し、上記基板の裏面に
おける上記脚挿入孔周囲に抵抗体層を設け、この抵抗体
の上に絶縁層を介して半田付可能な導電体層を形成し、
上記抵抗体に電流を流す導電体を設けた配線基板装置。
A leg insertion hole for an electronic component is formed in the board, a resistor layer is provided around the leg insertion hole on the back side of the board, and a conductive layer that can be soldered is formed on the resistor via an insulating layer. ,
A wiring board device provided with a conductor that allows current to flow through the resistor.
JP15603282A 1982-09-08 1982-09-08 Circuit board device Pending JPS5944900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15603282A JPS5944900A (en) 1982-09-08 1982-09-08 Circuit board device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15603282A JPS5944900A (en) 1982-09-08 1982-09-08 Circuit board device

Publications (1)

Publication Number Publication Date
JPS5944900A true JPS5944900A (en) 1984-03-13

Family

ID=15618818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15603282A Pending JPS5944900A (en) 1982-09-08 1982-09-08 Circuit board device

Country Status (1)

Country Link
JP (1) JPS5944900A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5542520A (en) * 1978-09-18 1980-03-25 Okamura Shokuhin Kogyo:Kk Overall tasty nourishing food
JPS5764990A (en) * 1980-10-09 1982-04-20 Hitachi Ltd Method of exchanging circuit element in wired substrate unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5542520A (en) * 1978-09-18 1980-03-25 Okamura Shokuhin Kogyo:Kk Overall tasty nourishing food
JPS5764990A (en) * 1980-10-09 1982-04-20 Hitachi Ltd Method of exchanging circuit element in wired substrate unit

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