JPS5943475A - Association processor having variable length high speed multiplying capacity - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This 'I steaming (I:5) generally relates to associative processing (a s 5-
) eta tive processing), and is particularly applicable to associative processing arrays that perform high-speed multiplications with a variable number of elements in the mask system i'+ll'-F. The associative processing array of this invention is an LSIC large-scale aggregation circuit) or Vr,SI (1jj()(LQ,
4'A'! L kA 1ljl 路) J[TE use suru, 1! : If? 4), in which Ij
A reduction in the amount of 4 circuits and the number of peer 1 systems is achieved with the unique circuit of the present invention.

Mask II! l'O'lkawa・-(范variable number length?+44
．． Associative processing combination that performs the above-mentioned high-speed multiplication with high speed) 0 rose, 7 st ma associative processing combination, - not only for middle school and 1j, but also for the system that has a high and other total L-71 tonne force. 1?
In general, there are -τ2 for ij. - A system like Pi (,i+IJ is an engineer,
Data 2-Pace Money Nomenon 1 System (2), Topological Mathematics 1i1JF Analysis, Graphic J2 Display, Audio Language 1, F Quantity Development [], Engineering and Track Analysis and Tracking, Text Editing System and Denotal Filter wave k @
fJ-Tsunshu etc.

[Technical background of the invention]

An associative processor can be thought of as an array of single 7g snow processors where each single cell accesses only the cells in its neighborhood. Associative data: The memory can be accessed by mutually parallel data streams, its memory is addressable by its contents, and its structure is based on tags.

A normal processor operates on many data objects at the same time, but it operates on many data objects at the same time. It must be of the same format even for every nine degrees of There is a fact that this class's data (Single
In5truction Multiple Data
It is known as "Grosselli" (hereinafter referred to as SIi■D).

The associative glow is constructed from a rectangular array of 11 bit combinators arranged in an LSI.
1 (for example 2) (or 64 bits of memory k)
4 I can do it. Note that each of these cells jilts in response to the same simultaneous command operating on its own data. The cell can be interchanged with a 4Li cell and an external input and output resistor at all seven opening forces.

0 (The cells in the row of the L70R7ZA array are marked, and the sails are '
The furrowed V is also dynamic in the field due to the 11 @ city + 1 i (thigh meat) 1 upper 7 y.
(can be formed from one command to the next)
.

Each field (<l is a separate combination that can be operated on for a given word length, -
It can operate independently as if it were a night.

These fields can all be rowed at the same time according to the same command, or selectively under the program 11I11fIII.

(The effect of (L) is the effect of a set of computers of any given word length that, when enabled, perform all the same computational or logical operations on different data items simultaneously.

This computer suite can be applied to matrix calculations, algebra, vector calculations, pixel processing, and problems necessary for search and no-ξ-turn recognition problems and voice recognition. They can perform both fixed point and floating point Ml' calculations with any desired accuracy. The sloop of this processor set depends on the size of the array, the length and number of fields, and the rate of play that is enabled for a particular operation. For example, it is estimated that a 128.times.128 cell array operating at 8 bits (2048) using a 10 Mf (z) clock simultaneously performs additions or logic operations on the order of 4 billion per second and multiplications on the order of 1 billion per second.

Sometimes content addressable memory (ContentAd
Associative memories (also known as dressable memories) are generally well known and are configured to function in associative processors, in which computational operations are simultaneously performed on one or more digital words stored in memory. Good too. Such an associative processor is described in U.S. Pat. No. 4,068,305 A', ltl-1.
4i' The VC description is blank. U.S. Patent No. 4.296,
Efforts have been made to reduce the number of connection bits required to use such content-addressable table memory 0;1' word organization, as illustrated by No. 475 specification. He is a Buddha. 4if between the bits consisting of the O word and the bits assigned to i'+ff (e.g. from a state flipflop), +i (the idea is that the data processor ignores one or more associative bits in the command word). It is said that the phalanges are conditionally executed by the mask bits coming together.This is shown in U.S. Pat.
:Notes:It is written in ii&. U.S. Patent No. 4,044
, No. 338 - An associative memory having associative areas separated by Q is described. Selective coupling of circuit elements to a boot circuit in which each circuit element has 4f associative addresses is disclosed in U.S. Pat. No. 4,188,670,
Self listed.

U.S. IJI Patent No. 4,159,538 111)
;jLsI content addressable memory is shown, in which the number of bin connections is reduced by sharing input data, output data, and mask pins consisting of 1M traces. An associative memory that accesses the 1.alpha. column is described in U.S. Pat. No. 44,153,943-IF.

[First aspect of the invention] In this invention, an array of associative process cells is used as a mask 1li.
l] ii knock down 2. 1st floor with a figure similar to a turtle 2 mosquito
The present invention relates to a one-machine processor configured to perform high-speed multiplication.

The associative zero loss sensor of this invention consists of cells each configured to simultaneously accumulate sum bits and carry bits gold. It comprises an array arranged in rows and columns of microscopic cells.

Each cell has a massing hand for determining that one or more particular cells have either a multiplier or a bit, or a combination thereof; k % father Bi, 1 hand to dandan, ;, 1
νThe means to perform the liquid calculations of the two brothers and sisters.

Eye i1! ! +2-15 le is Ko f? 7) Means for enabling said cells during operation to accumulate two bits of yield; 111 unit means of calculation theory to calculate the total amount of 11'5. and,
・Jε−1′? , is any −? The result of the current event (the top of E) is generated simultaneously in the cell in instantaneous contact with the seven crests of the length and the multiplier of fixed or variable.
(!:gafgura]L same shift as I-1: & between!j
There is a characteristic of a rose that looks down as a means of bringing good luck to the adjacent mountain range cells.

This clearing can be made suitable for prefixed calculations as shown in the example below, in which the embedding sequence of all cells is at the end of a row of cells or arrays. Whether in the center or in the center, the 8-axis total mass sequence is also compatible with the 8-meter sequence without a leap-line system.

In one embodiment of the associative cell structure, a separate GiV
It can be enabled at the same time or alternately and it can be very exciting.
lResaveno<? (borrow 5 ave pas)
s) Contains an improved computational logic unit for f@.

[Embodiments of the invention]

Referring to FIG. 1, an associative array 100 is shown in a schematic block diagram with its horizontal and vertical mask registers 102 and 104.

Mask registers 102 and 104 selectively enable or disable portions of array 1000, thereby effectively playing 100] which area dH7 Ray! till fall 4'i ii"7', determines whether to operate in response to a specific command from 106.

Array it'll l (applicable to I device 106) ° program is stored and passed through mask command line 108 to mask register 1.
02 and 104, and is coupled to the array node 0θ via the array command line 110f. programmed and/or
Alternatively, it can be constructed with any known control device having a programmable system. Typically 40 such books; p 108 j-3- and 4
There may be zero 110s in the array. The commands on line 108 perform all micronogram control for mask registers 102 and 104 and couple the array address to address I/noster 112. The address d is a memory address that is assigned to each play cell as shown at 212 in FIG. 3, which will be described later. Command If on line IIo provides microprogram control for array 100. line 1
The combined effect of the commands above 0B and 110 can be used to cause the play and its mask register to search the file for a record with a particular property, and then to multiply that portion of the record by a factor of .

The 1114 virtual array may be thought of as a sub-device 6 of an associative processor and is generally shown in FIG. To explain, the array has 7 cells of 20 cells by 4 cells. 2
A 0-bit vertical mask register 208 and a 20-bit vertical output register 209 are provided.

In FIG. 3 (y-z) a single associative cell, such as cell 204, is shown in its composition according to the characteristics of . The same cell 204 is one A type flip flop 21
0, eight M-type slots (71. shown collectively as 212), and associated control logic. The eight M-type frizzo frogs represent randomly accessible memory, and the flip-flops 21
2 acts as a memory data register bit. 8th
Only the number 8000 or 154,00 is shown.
It can be any number such as 0.

The computational logic unit (hereinafter abbreviated as ALU) 214 performs arithmetic operations as is well known, and may be of a conventional design. Also, as is well known in data processing, ALU 21
4 is added 4゛P: 1 used as a vessel (, ``f line 216
The above output is the same as the carry output on line 2) 8. ALLJ 214 is performing the addition 11, \, line 216 ((; bit is manually operated by selection switch zzzz) -
070/”, ?to is supplied to return to Z).
−, T [(slow out) f, $22
Combined with 4.

9)! The fast speed (fast) of 2.70 is -j=$-
If the A free lag flop 220 is connected to the select 'I' gate 232 and a land is supplied to the ALU 214 section of the cell for example, the answer is . l￥-6th gear output line is Go)2
It is connected to the I10 renostar 2θ9 in the figure so that the ijl calculation result of the ALU 214 is σ for all 1ja weeks. Low speed output means no carry to the first line of the first line. Data from neighboring cells, the data from neighboring cells, soft = 5 i to r - ta (7:) are connected to line 234 (Ic.
Similar to 4, it consists of associative cells, and the connection 205 in FIG.
, 207.

4th. ;(W5 and 61/1 are 300°3 in Figure 4)
Illustratively shown as 02 and 304, series-parallel multipliers consisting of more identical units! ,! 7' device] operation?
show. Norizzo Fronno 0306.308 and?
70 has a multiplicand. 2) The ξ number is line 312 one bit at a time.
is supplied to high-speed human power lines. FIG. 4 shows, for example, a part (3 units, 1) of a 5-bit east'-v unit, and its multiplier requires 10 units as shown in FIG. The works are as follows: 1. - It is. Multiplier value &': J: Provided during high-speed human power + 1312, and Dart 314 multiplicand p, l- and AND processing 6, resulting in IJa 11 unit, 'i16'
It was used for 1 history as an engineering input for \. line,? 1 The second power of addition 316 by B comes from the low iton output of the previous unit, and 5 it comes from the bit before the multiplication operation in cell 300 from multiplication 1 on line 312.'', (arithmetic operation 5, the third human power of lJO calculator 316 is the sub'27'' before the 1st power nu''9. Q:),
- From the knee 1 calculation result, it becomes ``W'' in the middle of ``U'' and ``F0320''. ((First time, Noko Sue j-tsu)ノ.

171.1: srf I)'IL ノ〈-m,'IQ
- to 9 results, fl] :F;= and A', rsU]
, that is JL soritsunonoro, , f , i 22 and 32
It is stored at 0 and σ. The operation of cells 300 and 304 is identical to cell 302.

j'j-, 5 Figure Sakae Isho and series parallel east 3kI Qr
Exemplary /rI+ where 11 pieces are multiplied by a multiplier of 5 bits, 1 (1) Yoshi, so is 5 bits, and t! :About arithmetic operations, 1. !
I have Pino 1τ. If the result is 10 Bi, l. (Go to -toga-〇2).

East of Lock 10 1: Yugod) Columns I to 100 are shown 71
Teido, ga, uniform'I; Figure 5, NEET row 7: Kou,
1.1. 1, bi1+, /Koi. Unique l
-6 to 10 are instead shifted to 14. You may change it. Series counter n, flat bit ζt while moving
- These are generated in units of 1, 7, 5 and 3. - They can be used in units of 1, 5 and 3.

No. 51 ¥! Each unit of l Uj 坏 [1 bit, t S and carry hit C can be accumulated at the same time, each step of 0 arithmetic, when performing 7'', each unit U, 2,, l-i71: The sum is on the right The incoming profit bits in each unit are propagated to generate a new L7 sum bit and a new giri bit, as explained earlier with reference to FIG. The existing carry hit 1? and the multiplicand located there are combined with the logical result of the incoming multiplication 9 statement.

The binary number that is the result of binary addition can be written as consisting of two lines, one line containing a pi' (c included, other lines containing garibit) fr. The total 1) can be done in such a representation in binary numbers, and the final absorption of carries is O[
This multiplication technique can be delayed until such time as it is necessary to produce a result in the final form 1ρ (i) consisting of a single column of 1 bit. 2i1 until the end of the multiplication where is finally absorbed
This is the sound effect of the 2fJ' expression of KH9.

The following numerical example of a 5.times.5 multiplication is described with reference to FIG.

MC=ilO11 M　P　　　01.110 The product becomes 0101], 11.010.

In FIG. 6, a column of multiplication units is shown, in which the vertical column has 10 multiplication units or alternatively 5 multiplication units (U=91.1 to 5) and 5 multiplication units.
It represents the status of the shift I/nostar (units 6 to 10) of the stage. The figure fully illustrates how addition is performed by each unit or stage. However, 5
You should understand that for ×5 multiplication, it is necessary to have 4 Samurai, tU Uni, Toro to 1 () with force 11 arithmetic.

The M flip-flops 3bθ, 352, 54, 356 of L units 1 to 5 are multipliers.

358 (・C is retained. This fl, these multiplicand pits G, and 8-1 36
θ, 4° to 362.3, i 6 (i, ,
The multiplier bit is ANDed at the anddart within each cell, shown as 36B. Therefore, it acts as a mask for the multiplier bit (-1 multiplier bit).

Row A shows the status of all 10 units before multiplication is started. Is there a column for each row? -, J: Carry on the left, sum output on the right, and the bottom column shows the input value after AND processing. The do11 bits &, - and the carry bits are zero in all cells to the row. , 11A, the first operation is all units.

It is the addition of the multiplicand to the . Since the least significant bit of the multiplier is seven, the effect in row A as a result of the AND operation is to add all zeros to the already empty unit. This result appears in row B. Notice that in row B all carry and sum bits are still zero.

In row B, it is again desired to separate the contents of each unit by the multiplicand, and when this operation is performed it can be observed that the next least significant bit of the multiplier is a one. The number B, , l- & J, appears in the position below row B. Row B
For the first column of C, 1 is added to the
It is Numera J] that outputs the sum bit 1 and the carry bit 0 for the column. Also, in the first column of row B, ``zero J sum r S, J bit V to the second column of row B, ``pyro'' carry [C1 plus C? :σ, MC bit “1” and i
'i VC([ILj', y tr 1. J OJ
: and row C24'', 2nd column, caliber bit rOJi is generated.The arrow in the cell indicates the addition unit 1b in each unit.
Show the work.

In line (), the multiplier is again “1” and the action is as in line C
This is the same as explained above.

In row E all "0"s are again added to each unit. This is because in the example of numbers 2 and 18, the multipliers B, , and G are 1 subtract "0". The time spent adding all r OJ i in row E (1/l is not wasted, it is not wasted time). This is because when the dipping bit is generated by the fifth unit, it is immediately used.
4'f: is necessary because it is not known whether the bond bit is "1" or "0" until -2 units of trnl are executed.

Row F l-j 7P of carry bits to the right, which is necessary for the propagation of the end. (1.2 parrots 1101.l
Product 01.011 ], i by multiplying by X011100
(This is an example of the operation of the unit to obtain 110.

J of the multiplier 111H to be used for setting @tK (this is a book).

Multiplier value in a pj column parallel multiplier designed for multiplication only: East 5.''1. Vessel...-Dou, the bukome hexagram that goes into the a, and the whole 1 warp out (7) If you don't use it somewhere else, the distribution fiQ ze turn is fat, and the zaizu reed device hardware is fixed. An advantageous feature of the present invention is that the position of the associative cell in the row can be changed and the selectable Orlando length can be predetermined by software or by accessing the memory contents. The multiplier and the I-P selective Yas (
This is related to the 19th generation.

Next (= Fig. 7) or variable length “
A diagram of lj2 rl-wait ii'i' is shown.・+1 (I think cell-ze: Such a variable length value using flj (i: j+.1 especially 11 (has a stupid east in application to the line circuit of lottery).Zoha, Shi1!
・14 thoughts of 0 rose and 1 can be used as a re-1 tone 1-earth filter in the equalizer. Katsuda 1st grade. Thoughts, no 0
The processor can be used as a high-performance filter in a transformer.

Extended ijJ 'jj? Associative floss 0 rose 2 s 4 - [small use machii I 7 multiplication is one soil,
It is effective in non-stationary applications, and is applicable to general signal shouting, ... and J-space applications.

4 wide and 11 long [to obtain a 1st and 11th array, V is multiplied by IJ (there is a convex digit on the top - C, and a mask is used])
Order off, must. Therefore, each associative cell is 1 bit 2 . when enabled during an east-stop operation. It must receive the multiplier of 1 bit, the multiplicand of 1 bit, and the 2 bits of the total result. One of the bits of gluing and pickling can be used to overwrite all of the characters.

Each one Toso cell is multiplied by 14 σ to its neighboring cells when disabled during multiplication, therefore also (~i, it is at the boundary of the active area: t rf should be done In order to enable the series multiplier, the necessary ``loop pack'' between the input and output of the active cell must be enabled.

Figure 7 shows the work by Ilb () ← of the same day as this completion of the mission. The arrow indicates the data flow 7'V, (D) i"j 7-' enable mask, (E) on the L side of the figure.
i<t: Indicates enable mask state. 8th
The figure shows the initial state of the calculation operation of Azuma A and multiplicand B, and both of those numbers are, for example, 2 on the 1st floor and 2 on the 1st floor.
i′! It is the li number. FIG. 7 also shows the multiplication in the shift/rus of n + 1 of the cell and the cell. This same amount (n + 1 as Bi in 8, 1 as the number n
+1's 7 footpulse)', in winter) Tiger Aba 4 Yoshisong R
of,? @ by the first n+1 (lowest digit) bit
will be replaced. The high-order bit of n+1 is held in the delayed binary recorder and the carry binary register in In Figure 4, a simple fritsuno flop is 'I) Mother IJP is out. - One digit pitted or on the right Hill.

Figure 7 (/,) ;'jQ
Each cell jrl ill arithmetic logic unit (ALU) 400.401...402. +9
・1s i sentence B. , 131... Bn Gold 1 Gakul Temple 4 (), 7, 404-405, Squared X & An, An-
1-...Ao gold holding registers 4θ6, 4θ7...
Contains 4o8, registers 403d, ・retains the lower finger bits, registers 406il,' ・“I
)-ni 柘吃゛ノDO衜子IS[-E/). The mask is J-
Nafuru, 1 Noni p1. 1ull nose f: 10 months? 'r−1= Lou? ? rl 7. . mask sword 1
-y゛King Isu-Buru Nipisu 1. Then, the right end of the mask L enable section □n is disabled ('(y on line 412] (forcefully. Mask Enable Bull Sec 71n (ID) and "1 jil +' (2t)
,・(Ha, Maskon-゛Isneaglesel Me0t)
, by 'q 4 1 4, l/jista (furi,) 0・
Noro, -y') (o 6 followed by 4.

:t＞7isl (7)+'N-c b-t *
+No.゛1劃÷N: %-'r to r [cannot be done.

Sign multiplication uses the uppermost bits (MSB) representing the sign.
)-t. number is displayed. In two's complement calculation, the MSB is (f, zero represents a positive number, 1
represents a negative reason.

iii number of 2 (signality > 2 ae. p ox
Suppose we are trying to multiply two very dangerous values. 211a
The numbers P and Q are expressed as follows.

P =-an2"+"(n-1)2"-'-1-a(
n-2) 2n-2,,, ae2.

= -a 2n+A Q = -b n2"+b (,,)2"-'-4-b
(n-2)2”-2-b o2.

=-b2"+B, P X Q= (-an2") X (-bn2")
+ (-an2n) x B+(-bn2”)XA+
AXB Referring again to the multiplier configuration in FIG. I can do it. Therefore: a.2j is represented by a.T, where T. is Furi3, I J
j Soph0・F[
This is the j2t♀th shift guru, which makes a total of 7 data shifts from the tip 408 to the line 410.

``Fuding'' is an example of sign multiplication and 8-hour/time display.

l'-a(n-2)b(n-1)' ■ Tn(-an)b(n-2),' =-an φ
b(n-2)T, +1 1(an)b(n-1) --an-b(
The same circuit form that applies to unsigned numbers from above n-, ) is applied to Maki Q's computational logic unit for l&1 digit bits (represented by bn), such that l- subtracts instead of addition. It was determined that by setting fN, the operation also works for numbers with signs. Vomited P's 1
When the upper bit (represented by a) is shifted by 7 and entered, the calculation logic unit must be set to subtraction and must be set to subtraction. The logical unit must be set to 7JI]. For proper operation for numbers with signs a shift of 2° must be provided (11) so that zeros are shifted in place of the coefficients of P. Must be shifted during government (renosta) or LS (least digit)
Either the result must be output for writing somewhere else after the 'r shift) before half of the high order digits of the result are inserted.

Referring to Figure 8, change the cells described in Figure 7!
[Then an associative cell is shown, which is capable of performing two;fi features. The cell groove configuration is as follows. That is, the number An...A(11-1)...An
・・Ao's 1st thread G an' an-j ”' ”01
'Keeping the stranger's cod/--Renosta of Atsushi's neighboring cells 450, 452, 454 I
'F' and 1 in 456 1. I'll be disappointed. E? L
EI Bo・-I's,・B(,,-1) ・・R,
, Irj l/nosta 458.46θ, 462 and 4
I was left stunned during my 64th birthday. Those l/nostas are each A
, (, σ coupled to TJ4e6°468.470 and 472)1. I'm here.

All 3. Processing operations occur during mask disable 4)) rather than during mask-r enable (E). (I can tolerate it). The use of this state of existence i-1 mask disney ``1 city is exciting, 7°・F1] 456
All subsequent outputs between the output of the ALU 4 G 6 and the ALU 4 G 6 are automatically enabled.
.

When 46g:j;- and 472 perform addition (other (7)
On the contrary, when performing ALU/ノ; decrease), ALU (7
2 is till 'C'? ) AI, U 472
27J, that the function of fulfillment is determined by Selkellf'
It is to point. 7Iゝノ] (fζ7JMosically enabled section (E> mask-disabled cell at other end &, t ALU 466 renostar (Nori, f Flora: f) 4. At evening 0, %!4
Connect by 73.

Figure 8] Hiroshi says about the circuit in Figure 7, ``It's good, but (1) Mask disable [edge of area;
It is guaranteed that the 3 cells have l”i Q property.1.IEδ,・
2) It is guaranteed that the gi and rebit from the cursor action will be compatible with the next subtraction riHIJ work in the calculation unit and to. Before giving the answer to the above problem, let's talk about it.
First, let me clarify.

In Figure 9) j: +3 of compatible 1'1' of azui♂ cell:
'ilj' of moth, indicating quality. The intervening 7 pages are either fl(l
Z is not caused by the actual connection of the mask disabled cells of Z
]'t in the cell in the middle of the mask disabled area.
= be accomplished.

In the cell D1, 1 of FIG. 9, the above-mentioned mask bus I-~Pull and both operations of the 7J FflX cell are repeated (Norino, . . . =T)Ll-/7'A:J-
``YoB ri iiQ ノ1itsu: y) 1 came out ii I
I'1 Ij-Katamu). Furi, -f・furo/′/″482
The output of!・:1: -'rr 8 figure I/) star (free, 1o, -7o,,, 7') 45 ri is put 1 se'machi nein 1'1 ÷ nft line (7t is insufficient ← Line 4.!?,?
vclertst, -are, A [, LI 4801)
2t'ya',) Output ki square + i (l') -7 s':'f' 4 s1----bIt, -1=ri7
* 7 (I!H) ノ 2/L, +C, J: 1.1-
y +) ,, J f -no・1~. fA, 4,820 manpower! Dokosa t7ru. Heraniheshi tI / 8 /) is the same as that of ALU i 72 of No. 81゛-i1 and rotation 3 (θ
at 11:11.゛lIorif-,yTQ ke)-'f+
-, ('r 3.1ffl i・[1・7) Vl'
i'Jzen-j, fri'nia°・noronotsu'' A J
', - and Moe in B 6.' Mask Quest 4-Guru f; Go in B sweat no) be: 辷: ') 1t' ? - Supply 5tE to all cells in r. /ft・cell・;/ −,,,−
) Y-S's 42,! As a result of the %i form (and Iriko JC hand) Z, o tit'lk, it is said that it is safe in the action of making a monument], and it remains in the 1-21 lr (・
Sureri”: naranai/ko〉, 7), (2, reshi: 7j
It doesn't work in the rF valley. The details of how the river ゛71.gadp),,l: is converted into φ are shown below.

The true 1 direct table shown in the background is ALU4.
'? Makoto in θ (shows the logic behind the execution of the 7 functions. Here, A is the number held in Renometa 482.

13 is held in register 484, which acts as a subject. '1°C7 is the incoming Galibinot.

co&'i are the bits that go out.

R, is the result coming in from the previous step.

Ro is the result of the lit force.

The state is the state of cell D according to the values A, B and C1.

, the 1-direct surface θl, 2, 5, 7 is stable, but the state 6H-il 1 i-B, which then becomes the state 7,
4 becomes state 0. As mentioned above, all mask-disabled cells except cell c-4 at the far left of the mask-disable area (D) indicated by cell C in Figure 1410. 11. It was discovered that cell C in Figure 10 contains the most significant digit of the multiplicand, and the part after specification 1; It must be said that it is something that is referred to as such. Cell differentiation or identification can be done by supplying a human data bit for a particular cell, or by having a second internal identification bit that can be set by a previous command. can be done.

FIG. 10 shows a row of associative cells performing a 3-bit multiplication in cells A, B and C. Each cell (cl.
You can refer to the entire figure.

Cells D, E, and F are identical to the cells described in FIG.
, f-flop and ALU-i.

- The issue of the compatibility of the second interlude mentioned above, namely the carry from the addition J9b work with subsequent subtraction in the ALU, will be discussed. In fact, we assume that we have alternate additions and subtractions that are ``carry 1 = -bu'', and ``CI'' is also active during this period: however, it is active either simultaneously or alternately. The type of carry and borrow save ξ (borrowTIRVe pR8l'+
) The ALU circuit can be completely transformed to suit Z) (4).

An ALU circuit is shown that is capable of solving the specification problem described in "!S t i l", id: in gl.

'' (addition/subtraction circuit v6 that can be constructed from a multi-layer logic N-path of the well-known 'design' as described in the table)
s o n l/'J: For example, if the multiplier is 7 and the wave is saved -r, L is +i,'pr, or operate 7. > The sentence ``kth + ttx'' has been written one time.

Relief 3 and b (d: AND key F 5θ2", - machining input terminal F gold (ite 1) 11 loss) circuit, 500
(/i-combined. 4゛old'[L
(K'''l:, -J2bi■) 1 yen when shifting 11 is slow at gravel 504!! Correct 7.'.・To flop 506, (
People are itchy and itchy 7 years ago 5 "6,"! I) Connect to the end F R/ of l). Carry C' of the previous 7 notes time (ri lgi<r, tf flop 508 is also fiI, this]tl is 1L norig floor -705178 lj'11:'i4.500 C
From the output terminal, the output terminal is connected to the output terminal.
01 ' Between the J software and the IY extension 1t, the circuit is connected to the C' input terminal of θ().
1lY450 (λ's 1ilIB output is delayed, 7
7]''・70,7/'510, 1 during 1 shift
)■1 Length 1. ((((((((() is supplied to the ii' input terminal f of the circuit 5()0 as a loan from the previous shift time. A:
/doku゛-,-(,5(high speed (F) in the data from No.2
aqt) is applied to the I+' input terminal of circuit i4500. ? The data for tl calculation, i', and river I are connected to the next cell from the R output terminals of circuits 5 to 0, and become R7 input power for the next cell.

Figure 11 + 2) q1'b)) Ethics 2. ), the addition Q, and the addition '1γ and subtraction functions of the subtraction circuit 500. ' is Fj+ from the previous 1° turn and previous shift time
! , 1: Result. , C:'(([This is a key change from the previous shift time.

t3'f4 Fail's shift 1・deV from time].

R is the current calculation result.

C+d is now σ)ki\,ri.

B i = soil ■, 1-(-2 porou.

Addition R=F+R'+C'-s' for i'~value mi=izt: as follows.

"R'C'
B' l circle CBo
0 0 0 0 0 0
0 0 0 1 1 0
10 0 1, 0 1 0
0Q 0 1 1 0
0 0(l i 0 0
1 0 00 1 (11,01
1 011, 001.

(13-], i, 1 0
01 0 0 0 1 0
01 tl (11011 101, 0010 10] 1 1 ° 01 1
0 0 0 1 01,
j O1111 11, + 0. 1. ],
01 1, 1 1. 0 1
January) i'((J-F-R'-1-(2'
-B K k:J Rj(i"t and t are missing 4.・ri.

F R'C'B'
it CBQ 0 0 0
0 0 00 0
0 1 1 0 1
0 (11,0100 0011000 010 (+ 1 I)
IQ ] 0 1.
OO10110000 01], i i, 0
]1 0 0 0
], O (11001011 ), (l J (101
, (11011it 0 0 1 ], 0 0
(,) 0 01 1
0 1. 1 0 11
1 1 0 ],
0 01 1 1,
This invention has been described above with reference to its preferred and actual examples, but is it correct? Numerous other embodiments, modifications and applications which are obvious to all parties may also be included within the scope of the invention described in Patent 1.
l p(Jf21 power.

49 Explanation of IR'S Q' in Figure 11'lf Figure 11 is a block diagram of the 1lls concept processor,
2112 is a simplified diagram of a 20x4 associative array of hills with vertical and horizontal masks, Figure 3 is a logic circuit diagram of a pure cell, and Figure 4 is a series-parallel multiplication:) 2-place logic. Episode 5: Schematic diagram of one hill of 10 locks in the row,
Figure 6 f, -j i? T column 4 (-column arrangement 'C'J,'(4)!''
Soushichiru's1'1- is 1, and Uto Sankan style's pro 1. Figure 8 is 111 (additional;
Modification of the circuit shown in the figure, ;1; g l:
The t0 diagram shows the rows of associative cells that perform rice arithmetic according to the present invention.
The schematic diagram shown in Figure 11 shows this Seimei glue (li/l-
The entire book has a total of 1; 9 logical units, 1, 1, and 9 associative cells.5. -Make it clear by reading and using logic diagrams.

100..., 1K Soryo Ray, 102...Horizontal mask register/9 meta, 104...Vertical mask register, 10
6...Complete1.・I: bli ii! il = t%,
122...Address register, 202...Hill matrix, 204...Cell, 206...Horizontal mask register, 208...llj mask register, 20
9... M mole convex person output Nosta, 210... A type pretend,! 6 Flo,] 0.212...M type Furitsuno Furitsuno 0.214..., Juisan, Rin Juri unit, 222,
228...l Kawasawa switch, 232... 1 in 1'
The length is 306. 1
013, 3 1 0. 320°322
... Fri] no 0 flora: 7°, 3I4... completed doge 5-to, 'l 16...'q device for fu,
4 θ 0 , 4 θ l .

4θ2...Logic calculation unit, 40.7, 404
.

405...1 skin, late Nosta, 406, 407
.

408...Multiplier register, 450.452.454°・G, 56,458,460,462,464...Register, 466.468,470,472°480...
・Total Ti, logic unit 1-5.1.92...-7 logic unit (register), SOO...addition/composition circuit, 502...and date, 506,508°510
・・・Delayed Furino Flo, '□10゜Exit IaI￥Person Agent Iriji Suzue Takehiko～, 3～・4・

Claims (1)

Claims: (1) an array arranged in rows and columns of associative cells consisting of cells configured to perform the sum bit and carry bit all simultaneously), each cell having one The following -1- specific cells are multiplier or multiplicand bits 1i
iJ ; jl or a combination thereof; means for accumulating the guru multiplier bi, 1; and means for multiplying the wave/K number bits and the multiplier bits. , 1) Cell iJ stores 2 pits of the multiplication result (t[so that i': j;'?: During operation, all the cells are disabled. i'i?J's shift time Add -ζγ or subtract the masked wave multiplier/one sentence bit to the result of the sum 'fE fJ' and output the entire current multiplication result by receiving the missing bits j; Sadatsugu Q: Logic unit means and the γ result to the current power as generated simultaneously in adjacent cells for a multiplier of digit length ? an associative processor, characterized in that it comprises: means for joining an adjacent associative cell at the same shift time as its current result is obtained; To make the ward uke 1 and grosshi 5. 911 means are provided for controlling the execution of said commands by the processor, said ilJ ft1 means are also provided for masking means to enable and disable portions of the processor; A means for combining multi-bit command words to store data in a processor as set forth in claim 1. (3) (Skin/Yoga sentence and 7゛(ξClear sentence bit is Hf■
The signal represents the bizotal 1 blur 11 + f signal so that it is multiplied by the processor by the 'p latency time.
SAMURAI 4. The associative processor according to claim II.δ1II15.1-1. 14) If the data field is 2, the catch is 2.
The associative processor according to item 1, which is composed of '[\;t'F Mi search range. (5) 2; 71i Processor described in Section 4 of Patent 1; '1' operating in each cell of the array.
Fjf to cell -hξ1"γ of the 11th residence: Yoshio Zen, %
:The means for connecting the cell to the human power output 11) when the cell is disabled during operation is the means for providing the f peck connection to f, l1nt L, etc., thereby serially 4 (ξ calculation is the position t of the cell in the associative A/A
・j, jlill of patent claims obtained regardless of the person
r(', 4, +: the associative processor described in ii. (n')4-a
(.-2) 2 (Kano 2)... ao20 = -a, Saku n 10 A Q = bn2" + b (n-1) 2 (n') + b (n-
2)2(n')12. bg20=5n2°1B The binary significance of B is determined by the position in the array, and the significant state of B is determined by the time at which the coefficients are shifted in the array. Associative brithissa described. (R) In order to disable the cell containing the uppermost digit pin of the number iη in the mask disable area, the masking means 1) disables the cell each time during the zero multiplication operation; 7. The associative process according to claim 6, wherein the associative process according to claim 6 is provided. (9) The associative processor according to claim 3, further comprising means for specifying the cell f containing the I-digit bit of the multiplicand in the mask-disabled area of the row. +1t) t1iI The means for specifying the cell is a means for supplying the input data bits to the cell. : The means for specifying is the means for setting and unsetting the internal free 1.f. !-jli′(:'F Request (7)
Hil) 111 Section 9 1 范设备的 Association Program o Sesoza O (1 71 to each cell in the playing means 1 to the above
One i, one box lip unit means J)n :ji!
: The carry from the operation is - followed by the subtraction operation and 11[4
It is +1, and 11fst from the increase operation is followed by < jJll :I! Separate carrier and borrow cells configured to be activated either simultaneously or alternately as shown in 2) with both action and rH properties. Means to make money + i #: A < no 11ii Σ enclosure 7) λ1yi IV, the series, ょ゛7°rose 2. -li". tl:>+)'ts h) to each cell in the audience array7
1 Said,,"qJyl! p stage and the previous LJl) cell stage' - the previous shift time or the result of L'? ) = p and , 1) Let the carry C' from the soft time of fl be 17 feet 1 day j tail 4jE4 and -
r
Meng and the above;
1. means for delaying the shift time TEN and fully combining the delayed borrowing B' from the previous shift time; 1. - and the front 111 input 2 from the addition/subtraction circuit, 51-≧7 for the angle F. result Ry, and means for coupling the result R to the next adjacent cell with its R' large input 1.
iii VM No. 12. , iJ"Jlic, t7-) associative program "1-4-large". Associative processor.
Associative processor as described in section. Qr9 Is the masking means of *XX bits associated with each row or column of the array? The multiplicand bit and the multiplier bit are subjected to an AND logic operation on the array cell. [Special features include all means to obtain 6-speed calculation input. 1"
Associative processor according to claim 1, paragraph 15 (). 1τ-, 6 fingers are motion feel 1゛, i'-tough field 4, ・
and a masking field with multiple (4) binary '; 1 order r; i'J (I~. Calculation of each cell, iA Riyu, -tsu I, middle high, 'jJ
j ; In order to perform all the Q calculation operations, enable and disable the f process cells 11 and '11 according to the previous M[J masking yield. Multiply the 2d rider and save by 〆fire, multiply by t, and the high speed rider power against Maseru's calculation logic unit will be 511 cho J + 4t.
,,: 'fJlgo i also teach in parallel and +itJ ti
t: M Maki bits in series [Total 7-. 1-, , ・iin Riko, knitting ・ Samurai: Deriving the IQ 't* results j
−75 term 7 ← λ for Denot length wave control and multiplier of L:
1 so that 94% arithmetic can be carried out simultaneously in the valley cell ((
Calculate ``4'' in cell h at the rotation shift time jf
r'? A high-speed multiplication method for variable role binary numbers, characterized in that the results are combined into adjacent cells. 0 → masking means of the cell which is disabled in the masking process and which manipulates the most significant bits of the group in the cell
Ran stop σ7'1. Z, target:′! 1. The method according to claim 17. (1! Many) The method of claim 18 for identifying cells in the mask-disabled area of a row during the masking process. ■ The carry from the addition operation is compatible with the next subtraction operation, and the subtraction operation A patent in which separate carry and save gases configured to be activated either simultaneously or alternately so as to be compatible with operation are combined. Claims IJfl No. 17
The method described in section. G21) 2 above. The method according to claim 17j, α, wherein the command is expressed as two's complement data.