JPS5942684A - Disconnection id allocating system of sto stack - Google Patents

Abstract

PURPOSE:To access two virtual address spaces even when an STO stack is disconnected, by allocating ID for STO disconnection forcibly in accordance with contents of head addresses of a segment table set to two control registers when the STO stack is disconnected due to a fault or the like. CONSTITUTION:When an STO stack 4 is disconnected and a disable signal goes to logic ''1'', disconnection ID allocating circuits 9 and 10 send disconnection ID, which is different from ID set to the first and the second ID registers 7 and 8, to an out-pointer 11. This disconnection ID is controlled in accordance with the output of a comparing circuit 1. Disconnection ID used for disconnection of the STO stack 4 is not registered in a table TBL. Consequently, two spaces beginning with head addresses of the segment table set to control registers CR1 and CR2 are accessed without hindrance.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a multiple virtual memory system that uses two control registers that contain the segment table start address of a virtual address space and performs address conversion of two spaces. S T OI allocated to each virtual address space in
D (Segment TableOrigin Id
If the STO stack for storing the correspondence between the ``entification (space identifier)'' and the segment table start address is separated due to a failure, etc., an STO that separates and assigns IDs to two virtual address spaces. This relates to a stack separation ID allocation method.

[Technology background]

Figure 1 shows an overview of the multiple virtual memory system, and Figure 2 shows T
FIG. 3 is a diagram showing an outline of an address translation method with an LB function, and FIG. 3 is a diagram showing an outline of an address translation method in which STOIDs are assigned. In the figure, vS is virtual memory, R8 is real memory, CRI is a control register, LA is a logical address, and R
A is the real address, SGT is the segment table,
PGT is the page table, PR is the prefix
register, DS is external page data set, vSO
to vSrL are virtual address spaces, and 4 indicates an STO stack.

In the multiple virtual memory system, as shown in FIG. 1, an independent virtual address space SO to V S n is allocated to each job. Therefore, within one system, a large number of virtual address spaces VSO to V S n exist simultaneously and are controlled by a control program. The virtual address spaces VSO to V S n are divided into two-stage units, segments and pages, and a control program creates a segment table SGT and a page table PGT corresponding to each segment and each page.

The segment table SGT is a virtual address space vS
One is prepared for each segment O to VSn, and stores the entry pointer to the page table of each segment, the length PTL of each page table, and the bit I indicating the invalidity of each pointer.

The page table PGT stores page addresses on the main memory for a plurality of pages belonging to a certain segment, a PID indicating invalidity, and the like. Furthermore, the virtual address space includes a common area and the entire system, in which control programs and tables resident in the main memory, control tables related to the control of the entire system, work areas, etc. are stored.

The control program sets the first real storage address (STO) of the segment table SGT of the virtual address space to be executed in the control register CRI. A logical address (virtual address) LA is given by a segment number SX, a page number PX, and an intra-page displacement.

The conversion from this logical address LA to a real address is performed as follows.

■ Segment table start address STO of control register CRI and segment number S of logical address LA
The segment table SGT is referred to by X and one segment table entry therein is selected.

■ Select one page table entry from the page tape #PGT belonging to the segment table entry using the page number PX of the logical address LA and the page table start address PO of the segment table entry specified by ■. .

■ The page table entry (7:
) H-i) Determine the real address by the displacement within the page of the address and logical address.

In the above ■ to ■, the length STL of the segment table SGT indicated by the control register CRI and the page table PG indicated by the segment table entry
When the segment number SX or page number PX of the logical address LA is larger than the length PTL of T, or when the invalid pit in the entry is "1", a conversion exception occurs and the address conversion is canceled. . In the case of a multi-processor system, since two CPUs have their own real address spaces, the real address spaces of each CPU are converted into absolute address spaces by the prefix function.

Segment table SGT and page table PGT
To use , it is necessary to refer to the main memory twice,
If such conversion were to be performed every time an instruction was executed, system Φ performance would be significantly degraded. In order to prevent this, TLB (T
ranslation-LookasideBuffe
A high-speed memory called r ) is provided. As shown in FIG. 2, multiple sets of logical page addresses (logical address segment number sX and page number PX) and real page addresses RP can be registered in the TLB. If the target real page address RP is registered in the TLB,
The real address RA corresponding to the logical address LA can be found by simply referencing the TLB (■ in Figure 2) based on the segment table start address STO of the control register CRI, the segment number SX of the logical address, and the page number PX (Fig. 2).
Figure 2 ■). If it is not registered in the TLB, the hardware uses the method described above to retrieve the real page address R.
After finding P and registering it in the TLB (Fig. 2 ■), the TLB
This real page address PR is then used to find the real address RA.

In a multiple virtual memory scheme, each program is given a different virtual address space. This means that different programs may have the same logical address. FIG. 3 shows an outline of a method for recognizing differences in virtual address spaces using STOID. 5TOIDα, b or le is its virtual address space VSO, VSI or VSn
It is created using the badge method based on the segment table start address A, B, or N for the segment table. This STO
ID, 1%h or L and logical address operation LAB or LA
Access the TLB using N.

STO stack 4 is segment double top 7)"
It is a high-speed memory that stores the correspondence between L/S A, BIN and STOID d, h, n (1) and leaves C. 5 For the virtual address space to which TOID has been allocated, the segment
Table start addresses A, B, N and STOIDα,
Store b% file in the STO stack. This results in
The same STOI when returning to the original virtual address space
D can be used. New STOIDt-8T
If an entry is evicted because there are no free entries to register it in the O stack, the evicted STO
The ID is invalidated and only TLB entries with the same STOID are invalidated (referred to as a spatial purge TLB). In this way, the entries in the STO stack and the entries in the TLB are always associated with each other.

[Prior Art and Problems] Conventionally, one control register is used, and the start address of the segment table in the execution space is set in the control register. The space is switched by the control program changing the contents of the control register.

In contrast to such conventional multiple virtual storage systems, inter-space communication requirements, that is, sharing a program in multiple spaces,
Two control registers are provided to store the segment table start address in order to move data between two spaces, refer to/update data in different spaces without moving it to a common area, etc. Now you can think about the system you want to use. In such a system, the segment table start address is set in each control register, two IDs are assigned corresponding to the spaces, and two IDs in the first ID register and the second ID register are assigned.
A D register will be provided. However, S
When the TO stack is separated due to a failure or the like, the STO stack entries and TLB entries are associated with each other in the separated state.
ID management will no longer be performed. If STOID management is disrupted, access to the virtual address space becomes difficult.

[Purpose of the invention]

The present invention is based on the above considerations, and is based on the STO stack in a multiplexed storage system in which 5 TOIDs are assigned so that two spaces can be accessed when the STO stack is separated due to a failure or the like. Separation ID
The layout is intended to provide a scheme.

[Structure of the invention]

For this purpose, the STO stack detachment ID allocation method of the present invention has a first control register and a second control register in which the start address of the segment table is stored, and a third control register in which the segment size and page size are stored. a control register; an inpointer that selects either the value of the first control register or the value of the second control register; a hash logic unit that hashes the value selected by the inpointer to create a space identifier; a segment; - STO stack that stores the top address of the table and space identifier; a first ID register and a second ID register that store the space identifier; and the first ID register or the second ID register that stores the space identifier created by the badge-logic section. an in pointer that selects a second ID register, and an out pointer that selects and sends a space identifier of the second LID register or a space identifier of the second ID register, and allocates a detached space identifier on the condition that the STO stack is detached. The STO stack separation ID allocation method has become as follows:
A comparison circuit for comparing the value of the first control register and the value of the second control register, and a separate ID allocation circuit are provided on the output side of the first ID register and the second ID register, and the separate ID allocation circuit includes: On the condition that the STO stack is separated and the comparison result of the comparison circuit shows a match, output a space identifier of the same specific value unrelated to the outputs of the first ID register and the second ID register to the out pointer. However, due to the fact that the STO stack has been separated and the comparison result of the comparison circuit shows a mismatch, the space identifier of a specific different value unrelated to the output of the LID register and the second ID register is outputted. It is characterized in that it is configured to output to a pointer.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a diagram showing one embodiment of the present invention.

In FIG. 4, 1 and 5 are comparison circuits, 2 and 6 are inpointers, 3 is a hash logic section, 4 is an STO stack, 7 is a LID register, 8 is a second ID register, 9 and 10 are separated ID allocation circuits , 11 is an out pointer, CROl
CRI and CR7 indicate control registers. control register C
The first segment table start address is set in RI, and the second segment table start address is set in control register CR7. The segment size and page size are set in the control register CRO. The segment table start address set in the control registers CRI and CIt7 is selected by the inpointer 2, and based on the selected segment table start address, the hash logic unit 3 creates the STOID using the hash method. It will be done. STO stack 4 contains the segment table start address and STOI.
Memorize the correspondence of D. Further, the in-pointer 6 selects the LID register 7 or the second ID register 8,
The STOID created by the hash logic unit 3 is set in the selected LID register 7 or second ID register 8. On the condition that the DISABLE signal is logic "0", the first LID and second ID set in the first ID register 7 and second ID register 8 are disconnected.
Through D allocation circuits 9 and 10! j: Sent to the out pointer 11. From pointer 11,
Select the 1st ID or 2nd ID sent to you and click T L
Send to B. In the comparator circuit 5, when the segment table start address of the control register CRI or CR2 is changed to v1 by the control progera l, the segment table start address and STOID after being rewritten are ST.
It is used to check whether it is registered in the O stack 4. Control register CRI in STO stack 4
or CR7 segment) - If there is an entry that matches the table start address, the same STOID can be used, but if there is no matching entry,
As mentioned above, a new STOID is registered in the STO stack 4. When there is no free entry in the STO stack 4, the oldest entry is evicted, and a new STOID is registered there.

Next, a case where the STO stack 4 is disconnected due to a failure or the like will be described. When the STO stack 4 is detached, D
The I S A B L E signal is made logic "1". D
When the ISABLE signal becomes logic “1”, the separation ID allocation circuits 9 and 10 assign the first
A detachment ID that is completely different from the ID set in the ID register table and the second ID register 8 is sent. The disconnection ID is controlled according to the output of the comparator circuit 1. Comparison circuit 1 compares the segment table start addresses set in control registers CRI and CR7. If the virtual address spaces of the segment table start addresses set in the control registers CRI and CR7 are the same (the comparison results match), the comparison circuit 1 outputs a logic "1", indicating that the two virtual address spaces are the same. If they are different (the comparison results do not match), a logic "0" is output. If the comparator circuit 1 is outputting logic "1", the disconnection I
The D allocation circuits 9 and 10 have the same disconnection ID, e.g.
o 000J is sent to the out pointer 11, but if the comparator circuit 1 is outputting logic "0", disconnection I
From the D allocation circuit 9 and IO, different disconnected LDs, for example "0000" on one side and [ooolj on the other side, are sent to the out pointer. These separated IDs are outside the scope of the STOID created by the badge logic unit 3 using the badge method. As a result, the detachment ID used when the STO stack 4 is detached is never registered in the TLB. Therefore control register CR
The two spaces according to the segment table start address set in I and CR7 can be accessed without any problem.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, ST
When the O stack is detached due to a failure, etc., the ID at the time of STO detachment is forcibly assigned according to the contents of the segment own table start address set in the two control registers, so the STO stack Even if the two virtual address spaces are separated, the two virtual address spaces can be accessed.

[Brief explanation of the drawing]

Figure 1 shows an overview of the multiple virtual memory system, and Figure 2 shows T
FIG. 3 is a diagram showing an outline of an address translation method with an LB function, FIG. 3 is a diagram showing an outline of an address translation method with STOID assignment, and FIG. 4 is a diagram showing an embodiment of the present invention. CROlCRI and CR7...control registers, ■, A.
...Logical address, RA...Real address, SGT...
・Segment table, PGT...page table, PR...prefix register, DS...
external page data set, vSO or vSrL.
...Virtual address space, ■S...Virtual memory, R8...
・Real memory, 1 and 5... Comparison circuit, 2 and 6... In pointer, 3... Hash logic section, 4... STO stack, 7... 1st ID register, 8... th 2 ID registers, 9 and 10... Separate ID assignment circuit, 11...
・Out pointer. 49i

Claims (1)

[Claims] The first address where the start address of the segment table is stored.
a control register and a second control register, a third control register in which the segment size and page size are stored, and the value of the first control register and the value of the second control register. Create a space identifier by hashing the value selected by the inpointer and selecting the inpointer!・Tushiko logic unit, stores the start address and space identifier of the segment table (STO stack, 2nd LID register and 2nd ID register that store the space identifier, and the above-mentioned hash logic unit that stores the space identifier created by the hash logic unit) an in pointer that selects the second LID register or the second ID register, and an out pointer that selects and sends the space identifier of the second LID register or the second ID register, provided that the STO stack is detached; A separation ID allocation method for an STO stack in which a separation space identifier is allocated, the method comprising: a comparison circuit for comparing a value of the first control register and a value of the second control register; and the third LID register. A disconnection ID assignment circuit is provided on the output side of the second ID register, and the disconnection ID assignment circuit connects the first ID register on the condition that the STO stack is disconnected and the comparison result of the second comparison circuit shows a match. and outputs a space identifier of the same specific value unrelated to the output of the second ID register to the out pointer, and on condition that the STO stack is separated and the comparison result of the comparison circuit shows a mismatch, STO stack separation ID allocation method, characterized in that the STO stack is configured to output a space identifier of a specific different value unrelated to the outputs of the LID register and the second ID register to the second outboard ink.