JPS5942524A - Power supply circuit of camera - Google Patents

Abstract

PURPOSE:To make a power source battery usable even when its electromotive voltage drops below a prescribed value and to utilize the residual electromotive force of the power source battery for a long period, by multiplying the electromotive voltage of the power source voltage and obtaining the operating voltage of a microcomputer. CONSTITUTION:When the electromotive force of the power source battery E is at >=2.0V, an analog circuit 1 operates by using the electromotive voltage of the power source battery E as its operating voltage and a CPU2 operates by using the output voltage of a voltage multiplying circuit 3 as its operating voltage. When the power source battery E is consumed and its electromotive drops below 2.0V, a source voltage discriminating circuit 4 detects it to stop the operations of the analog circuit 1 and CPU2 forcibly. The CPU2 is driven through the voltage multiplying circuit 3, so that even if the electromotive voltage of the E drops below a minimum voltage, e.g. 2.5V, this battery which used to be replaced is usable as it is until the electromotive voltage drops below the minimum operating voltage of the analog circuit 1, i.e. 2.5V. Consequently, a waste of the battery consumption is eliminated and economical use is realized.

Description

[Detailed description of the invention]

The present invention relates to a power supply circuit for a camera, and more particularly to a power supply circuit for a camera that uses a power supply battery to supply power to a plurality of circuits having different minimum operating voltages, such as a microconverter and an analog circuit. It is a well-known fact that in recent years, so-called microcomputer-controlled cameras, which have a built-in microcontroller as a central processing unit and control various operations sequentially by this microcomputer, have become commonplace. It is. Generally, microcomputers built into cameras often have a minimum operating voltage of 2.5 to 2.7 V or more due to required operating speed, temperature conditions, and the like. However, the minimum operating voltage of the analog circuits installed in the camera, such as the 1Il11:)Y; circuit, the pressure discrimination circuit, and the photographing information display circuit, is the same as the microcombi 1. - Significantly lower than the lowest operating voltage of the evening, these analog circuits are 2.
Works reliably even near OV. In cameras that have both a microcomputer and an analog circuit, the minimum operating voltage of the microcomputer is higher than that of the analog circuit. The camera is designed to operate reliably according to the operating voltage. Therefore, in conventional cameras using microcomputers, it is necessary to replace the power supply battery at an early stage when more residual electromotive force remains than in cameras using only analog circuits. However, considering that silver batteries, whose prices have been rising recently, are mainly used as power batteries, it is difficult to uniformly dispose of power batteries while still retaining sufficient electromotive force to operate analog circuits. It must be said that this is extremely uneconomical. SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a camera power supply circuit including a voltage amplification circuit that amplifies the electromotive voltage of a power supply battery and supplies it as an operating voltage to a microconbeater. Another object of the present invention is to provide a power supply voltage discrimination circuit, a voltage amplification circuit, and a power supply switching means, and to determine the power supply voltage when the electromotive voltage of the power supply battery becomes lower than the minimum operating voltage of the microcomputer. To provide a power supply circuit for a camera, which supplies the output voltage of a voltage amplification circuit to a microcomputer as an operating voltage by switching a power supply switching means based on the output of the circuit. In the present invention, the current consumption of the microconbeater is on the order of several fractions μ, and the current consumption of the analog circuit (several rnA to several tens of m
This was developed with the focus on the fact that the power consumption is significantly lower than that in A), and has the feature that there is no risk of a significant increase in power consumption even if the microcomputer is operated via a voltage amplification circuit. Hereinafter, the present invention will be explained based on illustrated embodiments. FIG. 1 shows a camera showing an embodiment of the present invention. ff. The source circuit is shown. While the lh power supply circuit and analog circuit 1 of this embodiment are directly connected to the lj source EVC, a microcomputer (hereinafter referred to as CP
U,! :Abbreviated. ) 2 is connected to a voltage doubler circuit 3 which is a voltage amplification circuit. Therefore, the analog circuit 1 consists of a DL optical circuit that inputs the subject brightness, an A-TJ conversion circuit that converts analog values into digital values, a shooting information display circuit that displays shutter speed, etc. Driven directly by electromotive voltage, CP
U2 is operated by the output voltage of the voltage doubler circuit 3, which doubles the electromotive voltage of the power source battery E. Also,
A power supply voltage discrimination circuit 4 is connected to both ζ1□'It of the power supply battery IC, and this power supply voltage discrimination circuit 4 detects that the electromotive voltage of the power supply battery E is close to the lowest operating voltage of the analog circuit 1, for example. 2. It serves to detect that the voltage has become OV and stop the operation of the analog circuit 1 and CPU 2. In the camera power supply circuit of this embodiment configured as described above, the electromotive voltage of the power supply battery E is 2. In the normal state of OV or more, the analog circuit 1 operates by receiving the electromotive voltage of the power supply battery E as the operating voltage, and the CPU 2 operates by receiving the output voltage of the voltage doubler circuit 3 as the operating voltage. . Then, the power supply battery E is exhausted and its electromotive voltage increases to 2
．． When the voltage drops below 0V, the power supply voltage discrimination circuit 4 detects this and forcibly stops the operation of the analog circuit 1 and CPU 2. This is done to prevent the camera from malfunctioning or displaying incorrect information due to a drop in the electromotive voltage of the power supply battery E. According to the camera power supply circuit of this embodiment, since the CPU 2 is driven through the voltage doubler circuit 3, the power supply battery E
The electromotive voltage of is the lowest operating voltage of CPU2 (for example, 2,5
Even if the electromotive force drops below the analog circuit 1's minimum operating voltage (e.g. 2.OV), the old battery 11, which was replaced with a conventional power supply battery, will
Vm pond can be used as is. Therefore, the electromotive force of the power source battery can be used effectively, and there is no waste of battery consumption, making it extremely economical. By the way, the voltage doubler circuit 3 shown in the embodiment of FIG.
Since the circuit 3 amplifies the power supply voltage twice and supplies it, in principle, the temperature is about 2 degrees Celsius compared to when the same circuit 3 is not used.
Seven times as much power will be consumed by CPU2. For this reason, in the tIL source circuit of this embodiment, although the current consumption in the CPU 2 is extremely small, the power consumption in the normal state increases, which may lead to the premature depletion of the power supply battery E. There is. FIG. 2 shows that in order to solve the problem of the power supply circuit of the embodiment shown in FIG. Voltage is CP
Only when the CPU drops below the minimum operating voltage of U2
2 is connected to a voltage doubler circuit 3 to reduce power consumption. The power supply circuit of the camera of this embodiment is provided with two power supply voltage discrimination circuits 5 and 6, a first and a second, respectively.
The first power supply voltage determination circuit 5 is a circuit for detecting the power supply voltage that starts the operation of the voltage doubler circuit 3, and its determination voltage is a voltage slightly higher than the minimum operating voltage (approximately 2.5V) of the CPU 2. It is set to Vct. The second power supply voltage determination circuit 6 is a circuit for detecting the power supply voltage that forcibly stops the operation of the camera, and its determination voltage is the lowest operating voltage of the analog circuit 1 (approximately 2.OV )
The voltage is set to a slightly higher voltage VC2. The first and second power supply voltage discrimination circuits 5 and 6 are
The control signal input terminals thereof are respectively connected to the power control signal output terminals of the CPU 2, and receive the power control signal PW. Then, the power supply control signal PW is
Both power supply voltage discrimination circuits 5 and 6 operate in the L° level state, and when the power supply control signal PW reaches °I(' level, both circuits 5 and 6 stop operating. The reference voltage input terminals of the power supply voltage discrimination circuits 5 and 6 are respectively connected to the output terminal of the reference voltage circuit 7, and receive the reference voltage Vref.The reference voltage circuit 7 discriminates the power supply voltage. A known circuit that generates a reference voltage for controlling the
The power supply control signal PW is applied to the power supply control signal PW. Therefore, the iQX output circuit 7 operates or deactivates in accordance with the level of the power supply control signal PW, similarly to the power supply voltage discrimination circuits 5 and 6.
I'm starting to feel like J. The output terminal of the above-mentioned first power supply '11 likelihood pressure determination circuit 5 is double?
l (connected to the control signal input terminal of the output circuit 3, and when the power supply voltage drops below the judgment voltage VC1, the voltage doubler circuit 3
The circuit 3 is operated by applying an amplification command signal As to the circuit 3. The voltage doubler circuit 3 has a clock signal input terminal connected to the clock signal output ring of the CPU 2,
It receives the clock aunt Φ output from the CPU 2 and amplifies the '''C power supply voltage by two times in synchronization with it.The output terminal of the voltage doubler circuit 3 is connected to the other power supply selector switch SW2. The operating voltage supply end of the CPU 2 is connected to the power supply battery E via one of the power supply selector switches SW.
It is also connected to the negative terminal of. The one and the other power supply changeover switches SWI and SW are power supply changeover means for selectively connecting the CPU 2 to the power supply battery E or the voltage doubler circuit 3, and are outputs of the first power supply voltage discrimination circuit 5. Depending on the situation, one of the switches SWI or SW is turned on and the other is turned off. That is, in a state where the first power supply voltage discrimination circuit 5 detects that the power supply voltage is equal to or higher than the determination 7u voltage Vc+, the switch SW is turned on;
Switch SW. is turned off, and the 17 source voltage is directly supplied to the CPU 2 from the power supply battery E as an operating voltage.
When it is detected that it is 1 or less, switch SW1
is turned off, switch SW is turned on, and a voltage obtained by doubling the power supply ME voltage is supplied to the CPU 2 from the voltage doubler circuit 3 as an operating voltage. The output terminal of the second power supply voltage discrimination circuit 6 is connected to the control signal input terminal of the CPU 2 and the analog circuit 1, respectively, and when the voltage of the power supply Wf falls below the determination voltage VC2, the operation of the electric circuit is stopped. In order to do so, a battery check signal BC of the °H' level is applied to the CPU 2 and the analog circuit 1. l I, T I
When the battery check signal BC of the L novel is applied,
The CPU 2 is reset, the operation of the CPU 2 is stopped, and the power control signal P output from the CPU 2 is
W becomes the degree 11' level, and the first and second power supply voltage discrimination circuits 5 and 6. Reference voltage circuit7. At the same time, the level shift circuit 8 also stops operating. Further, by applying the battery check signal Be, the analog circuit 1 also stops operating. The CPU 2 is connected to the analog circuit 1 via a level shift circuit 8. Level shift circuit 8
is a circuit for connecting circuits that operate with different power supply voltages, and is already known. CPU
When voltage doubler circuit 2 and voltage doubler circuit 3 start operating at an operating pressure twice as high as the supplied power supply voltage, the operating voltage of CPU 2 becomes higher than that of analog circuit 1.
When transmitting a signal from U2 to analog circuit 1, it is necessary to lower the voltage and supply it, and analog circuit 1
When transmitting a signal to U2, it is necessary to supply a high voltage. Level shift circuit 8 is provided to automatically shift this voltage level. As described above, the analog circuit 1 is a circuit consisting of a photometric circuit, an A-D conversion circuit, a photographing information 1 display circuit, and the like. Further, an information input circuit 9 is connected to an input terminal of the CPU 2. This circuit 9 is a circuit for inputting photographic information such as film sensitivity, aperture value, shutter speed, etc. to the CPU 2. Further, CP and U2 include a display switch SW, main switch SW4 . One end of each of the trigger switch SW and self-switch SW6 is connected to each other. Each of the switches SW8 to SW8 is connected to the positive terminal of the power supply battery 3-character connection E, and receives an operating voltage VDD. The display switch SWs is a self-resetting switch. When A is closed, CPU 2 starts operating and CP
The power supply control signal PW output from U2 becomes "L level", and the analog circuit 1, the first and second power supply voltage discrimination circuits 5 and 6, the reference voltage circuit 7, and the level shift circuit 8 This causes the camera to display shooting information, etc. After this, the display switch SW3 opens due to its own return behavior, but the 5-source control silk 1 signal PW switch SW,
For example, I L P for about 10 minutes from 1 month closed
The level is maintained, and the display of shooting information, etc. continues during this time. Further, the main switch SW4 is a switch provided to be linked to the movable reflection mirror of the -eye reflex camera, and is closed immediately before the mirror completes its upward movement, and after the exposure is completed, the mirror starts its downward movement. This is a switch that opens when completed. Furthermore, a trigger switch SW. is a switch that closes when the movable reflective mirror completes its upward movement and the shutter front curtain starts.
When the CPU 2 closes, the CPU 2 starts counting the exposure time. Furthermore, the self-switch SW6 is a switch for instructing the camera to perform a self-timer operation, and when the switch SW6 is closed, the CPU 2 starts the exposure operation after the self-timer operation ends. Further, the CPU 2 connects a switching transistor Q for magnet control through a resistor R6. is also connected. This transistor Q. is formed of an NPN type, and its base is connected to one end of the resistor Ro, its emitter is connected to the negative electrode of the power supply battery E, and its collector is connected to one end of the coil of the shutter trailing curtain holding magnet M3. The other end of the Mg coil (magnet for holding the shutter rear curtain) is connected to the positive electrode of the power supply battery E, and receives an operating voltage VDDO. When the rear curtain hold signal of °H level is output from the CPU 2, the transistor Q is turned on, magnet Mg is excited, and the shutter rear curtain is held. Furthermore, when the exposure is completed and the trailing curtain hold signal is inverted to the °L° level, the transistor Q is activated. is turned off, the magnet Mg is demagnetized, and the shutter trailing curtain is moved. Therefore, the exposure operation is completed. Incidentally, since the overall control flow of the camera is not the gist of the present invention, a detailed explanation thereof will be omitted for the time being. FIG. 3 shows the power supply circuit of the embodiment shown in FIG. 2 in more detail. In this figure, the first power supply voltage discrimination circuit 5 includes transistors Q3 to Q, 6. Resistance R1
, ~R, and a capacitor C1l+C4. -R11j of the resistor R1 which becomes the control signal input terminal of the pressure discrimination circuit 50 to the first power supply 1 is connected to the control signal of the CPU 2 (iT
It is connected to the output terminal of the power supply
It is designed to receive an application of W. And the resistance ratio,
The other chant is 1. It is connected to the collector and base of the IFNPPNP type transistor Q3. The emitter of the transistor Q3 is connected to the operating voltage supply line E drawn from the positive electrode of the power supply battery E, and receives an operating voltage VDD. Also, the emitter of the base of +- transistor Q3 is line E! P N P ! connected to P N P ! ! l! ! ) transistor Q4 e Ql
+ Qlo eQ201 is connected to each base of Q22 and Q2°, respectively. Transistor Q4 is
The collector of the transistor Q is connected to the collector and base of the NPN transistor Q, and the emitter of the transistor Q is connected to the operating voltage supply line E drawn from the negative terminal of the power supply battery E, and the emitter is connected to the positive voltage Vsst.
are taken. And the base of transistor Q6 is
It is connected to the base of transistor Q7. Also,
Transistor Q is connected to the collector and base of transistor Qs+ in second power supply voltage discrimination circuit 6, the collector of which will be described in detail later. The resistors It and R,s are connected in series, and the lines E2. E, is inserted between them to form a voltage divider circuit,
The connection points of both resistors R2 and II are connected to the base of the NPNPN transistor Q and the cap of the NPN transistor QI4, respectively. The collector of transistor Q, is connected to the collector and base of PNP transistor Q+Ql, and the collector of transistor Q,. The emitter of is line 1! Connected to i2. Further, the base of the transistor Q+o is connected to the base of the transistor Q+t, which together with the transistor Q+o form a current mirror circuit. On the other hand, the transistor Q,
The emitter of is connected to the collector of the transistor Q7. This transistor Q7 is formed of an NPN type transistor, and its emitter is connected to line E.
Its collector is connected not only to the emitter of transistor Q mentioned above but also to the emitter of NPNPNP transistor Q. The base of the transistor Q is connected to the output terminal of the reference voltage circuit 7 and receives the reference voltage Vref, and is also connected to the line El through the capacitor C3.
and the collector is connected to the collector and base of a transistor Q + + (of the P NP type). The emitters of the transistors Q and I are connected to the line E2, and their bases are connected to the base of the transistor Q and the transistor QI4, which together with the transistor Q8 form a current mirror circuit. has its emitter connected to the line E1, and its base connected to the emitter of the transistor Qt< through a resistor R14.The transistor Q1 is formed of a PNP type transistor, and its emitter is connected to the line E, The collector is connected to the collector and base of an NPN transistor Q+s, respectively.The transistor 'Ls is
The emitter is connected to line E, and the base is NP
It is connected to the base of N-type transistor Q+a. The emitter of the transistor Q+e is connected to the line E1, and the collector is connected to the collector of the transistor CLs. The transistor Q+s is formed of a PNP type transistor, and its emitter is 2in E,
It is connected to the. The connection point between the collector of the transistor QCs and the collector of the transistor Q+a is PN
Connected to the bases of PNPN transistors 7 and Ql8, respectively. Transistor Q 17 has its collector connected to line E, and its emitter to transistor Q t . connected to the base of. Transistor Qss has its collector connected to line E, and its emitter connected to the collector of transistor Q+o. Further, the emitter of the transistor Q1s is connected to the output terminal of the amplification command signals A and S of the tenth power supply voltage discrimination circuit 5 and l/I.
The Nandt gate (34 wind power input

[;Connected to 1.1. 10.Ki Tojinjisuta Q. is the collector and emitter of the transistor QyI (the second terminal):
The PNP type transistor Q21 has its collector connected to the base of the NPN type transistor Qts. Transistor Q, ff 8 has an emitter connected to line J,
The collector is connected to the collector of the transistor Q,2, and is also connected to the line E1 via the noise prevention capacitor C4. Collector of transistor Q22 and transistor Q2
The contact point with the collector of 8 is connected to the base of NPN transistor Q, t4. ) The collector of the resistor Q24 is connected to the line 1 bow, J+, and the emitter is connected to the transistor (
9,4, follow the resistor 1t, and connect the transistor Q.
A transistor Q is connected to the base of 20 through a resistor l
ts base, respectively. Transistor Q! ! 1 is formed of an NPN type transistor, the collector of which is connected to the base of transistor Q2g,
The emitters are connected to lines E, respectively. The transistor Ql is an NpNm switching transistor that serves as a switch 5W1 (see FIG. 2) to the power supply (υ11), and has an emitter connected to a 2-in H8, and a collector connected to the negative side of the CPU 2 and the level shift circuit 8. The base is connected to the collector of the transistor Q2 and the collector of the transistor Q26. Another switching transistor Q27 is connected in parallel to this transistor Q2g. That is, this transistor Qzy is the same as the transistor Qts (NPN type), and its emitter is connected to the line El, and its collector is connected to the negative operating voltage supply terminal of the CP 112 and the level shift circuit 8, respectively. The base of the transistor Q3 is connected to a point A (see FIG. 2) on the line connecting one end of the display switch SW and the CPU 2 through a resistor R7. is turned on when the display switch SW3 is closed, and the CPU 2
Connect the negative operating voltage supply end of C to line E,
)' serves to start the operation of U2. Further, the transistor Qto serves as the power supply (power switch SW, (see FIG. 2)).
A type switching transistor whose emitter is connected to the MO8 type '111 in the voltage doubler circuit 3, which will be detailed later, and to the source of the field effect transistor Q2, and whose collector is connected to the CPIJz and the negative operation 1 of the level shift circuit 8.
．． [The pressure supply Mizui and the two are connected respectively. In this way, the borrowed @1 power supply))1:pressure I'll separate circuit 5 outputs the command signal F when CI'U2 is in a small operation.
It does not operate when W is °IJ level, and C, I'1JI
J2 is in the operating state. [Power control signal PW is °1
) "When the level is reached, the discrimination operation starts. That is, 11
1. When the source control signal PW is at the °11" level, l.
Ranjisk Q3 is turned off, and each transistor connected to the same transistor Qs (Si, Qs * C1', 191 Qto + Qt * and Q
26 are also turned off, and the switching transistors Qys and Q, as well as the transistor Q + s are turned off. are also turned off. Therefore, the first power supply voltage discrimination circuit 5 does not perform a power supply voltage discrimination operation. Also,
When the power supply control signal PW reaches the L9 level, the transistor Q3 turns on, and the transistor Q4 * Qs +
Q+o+Q! . . Qtm and Qta are each turned on. When transistor Q4 turns on, transistor Q also turns on, transistor Q7 turns on, and transistor Q7 has transistors Q3 and Q4 N and transistors Q6 and Q.
The current mirror effect between , causes a constant collector @1 current to flow, determined by the value of the resistance ratio, . This collector current is the sum of the current flowing through the transistor Q8 and the current flowing through the transistor Qo, and since this sum is constant, the power supply voltage discrimination circuit 5 determines the power supply voltage applied to the base of the transistor Q6. ,
Resistance ratio 2.几. The divided voltage 'Vthz by the transistor Q9 (7)
The following two operations are performed depending on the level of the reference voltage Vref applied to the base. (la) When the divided voltage Vthl is higher than the reference voltage Vref, that is, when the 1%i voltage is higher than the judgment voltage Vci, in this case J↓), the current flowing through the transistor Q8 flows into the transistor Q. As a result, the current flowing through transistor Q+6 is l
-The current will be greater than the current flowing through transistor QI3. Therefore, the difference current between the two currents is the transistor QI7 r Q+s
flows out from the base of both transistors Q+? y
Q+s turns on. When transistors Q and H7 are turned on, transistors Q21+ and Q and ts are turned on, and transistor Q0 is turned off and transistors Q and Q are turned on. At the same time, the transistor Q2g is turned on due to the turning off of the transistor CJ2n. Therefore, c)) The negative operating voltage supply terminal of U2 is connected to the negative electrode of the power supply battery E, and the CP
U2 operates using the electromotive force of the power source battery 1 as the operating voltage. On the other hand, when the l transistor Q4 is turned on, the emitter potential of the transistor Qrs becomes a low level, and the operation of the voltage doubler circuit 3 is stopped as will be described in detail later. (1b) When the divided voltage Vth 1 is lower than the reference voltage Vre f, that is, when the power supply voltage is less than the judgment direct voltage ■c1, in this case, the current flowing through the transistor Q8 is higher than the current flowing through the transistor Q. As a result, the current flowing through transistor Q+a becomes smaller than the current flowing through transistor Qlj. Therefore, the difference current between the two currents is the transistor Q+71Q+
s, and both transistors are turned off. When transistor Q+7 turns off, transistor Q
21 + Q2g is turned off, transistor Qt4 is turned on, transistor Q2° is turned on, and transistor Q28 is turned off by turning on transistor Qya. Therefore, the voltage supply terminal of the negative side of CPU2 is
The CPU 2 is connected to the output terminal of the voltage doubler circuit 3 which has started operating as described later, and the CPU 2 starts to operate using the output voltage of the voltage doubler circuit 3, in which the power supply voltage has been amplified twice, as the operating voltage. Further, by turning on the transistor Q24, the transistor Q+4 is also turned on, and the base potential of )7:'cis:9Q@ is lowered, and the first power supply voltage discriminating circuit 5 stops the subsequent discriminating operation. On the other hand, when the transistor QCs is turned off, the emitter potential of the transistor Q+a reaches the level 'H', which is transmitted to the voltage doubler circuit 3 as the amplification command signal As, and the operation of the voltage doubler circuit 3 is started as described later. Note that the power supply circuit in this example is designed to save power (
The display switch SW, (see FIG. 2) is only activated for about 10 minutes, for example, after closing. That is, when the display switch SW3 is closed, the electric current fSr at point A
becomes high and the transistor Q! 7 is turned on, and as a result, the negative operating voltage supply 1 of the CPU 2 is connected to the power supply battery 1.
When connected to the negative pole of the bow, the operation of the CPU 2 is started. The display switch SWs is a self-resetting switch, so it will open if the operating force is removed, but at this point, the CPU2
Since the power supply control signal FW of CP TJ2 becomes l L l level, the transistor Q28 is turned on.
The state of supply of operating voltage to the CPU 2 is self-maintained for about 10 minutes by a timer built into the CPU 2. After this time has elapsed, the power supply control signal PW is inverted to the "H" level.
As a result, self-holding is released, and the CPU 2 and various circuits 1, 5 to 8 around it stop operating. The second power supply voltage discrimination circuit 6 includes a transistor Qs+
~Q40 and resistor TL8. R, the configuration is almost the same as the discriminating section of the first power supply voltage discriminating circuit 5. That is, the collector of the NPN transistor Qs+, which serves as the control signal input terminal of the second power supply voltage discrimination circuit 6, is connected to the transistor Q in the first power supply voltage discrimination circuit 5.
The emitter of transistor Q8I is connected to line E. , and its base is connected to its own collector as well as to the base of an NPN transistor Q34. In addition, the above-mentioned resistors ``(, 8 and R, .
Connected to the base of the ss. Transistor Qs
The collector of transistor Q112 is connected to the collector and base of transistor Q42 (IJ N P type), and the emitter of transistor Q112 is connected to line E2. Also, the base of the transistor Q0 is connected to the base of the transistor Q0.
It is connected to the base of a PNP transistor Qsy which forms a current mirror circuit together with 32. On the other hand, the emitter of the transistor Qss is the transistor Q
, 4 are connected to the collectors. This transistor (
i, 4 is formed of an NPN type transistor, and its emitter is connected to the line I, and its collector is not only the emitter of the transistor Qss, but also the emitter of the transistor Qss.
It is also connected to the emitter of the NPN transistor Qso. The base of the transistor Qse is connected to the output terminal of the reference voltage circuit 7 and receives the application of the ``'C reference voltage Vref, and the collector is connected to the collector and base of the PNP type transistor Q35. Q
The emitter of ss is connected to line E, and the emitter of ss is connected to the base of a PNP transistor Qso, which together with transistor Q86 forms a current mirror circuit. The transistors Q and I have their emitters connected to the line E, and their collectors connected to the collector and base of the NPN transistor Qss, respectively. The emitter of transistor Q3g is on line E! , and its base is connected to the base of the NPN transistor Q40. The transistor Q40 has its emitter connected to the line E, its collector connected to the collector of the transistor Qso, and the transistor QI1.
The emitter of 9 is line E! It is connected to the. and,
The connection point between the collector of the transistor Q0 and the collector of the transistor Q4°, which is the output end of the second power supply voltage discrimination circuit 6, is connected to the control signal input end of the CPU 2 and the analog circuit 1, respectively. The second power supply voltage discrimination circuit 6 configured in this way does not operate when the CPU 2 is inactive and the power supply control signal PW is at the °11' level, similarly to the first power supply voltage discrimination circuit 5 described above. , U2 is activated and the power supply control signal 1)
When W reaches °L level, the discrimination operation is started. That is, when the power supply control signal PW is at the °14' level, the transistors Q, , Q in the first power supply heavy pressure determination circuit 5
, turns off, which turns off transistor Qs, and turns off transistor Q84 as well. Therefore, all the transistors Q sr to Q of the second power supply voltage discrimination circuit 6
40 is turned off, and the power supply voltage discrimination circuit 6 does not perform a power supply voltage discrimination operation. In addition, the power supply control signal PW
When it reaches the I L l level, transistor Qs=Qs in the first power supply heavy pressure discrimination circuit 5 is turned on, transistor Qs+ is turned on, transistor Q84 is turned on, and a constant current begins to flow through the transistor Q84. . Therefore, the power supply cloth pressure discrimination circuit 6 detects the resistance n of the power supply voltage applied to the base of the transistor Qms.
rt. The divided voltage ■th2 and the transistor Q11
The following two operations are performed depending on the level with respect to the reference voltage Vref applied to the base of 6. (2a) When the divided voltage Vth2 is higher than the reference voltage Vref, that is, when the power supply voltage is higher than the determination voltage VC2,
In this case, the current flowing through the transistor Qss is larger than the current flowing through the transistor Qsa, and as a result, the current flowing through the transistor Q40 is larger than the current flowing through the transistor Qso by γ)1. . Therefore, the collector potential of transistors Q and 4o is e
It becomes L l level, this is the power supply TV, and the voltage is the judgment voltage V
It is transmitted to the CPU 2 and the analog circuit 1 as a bad battery check signal I3C indicating that there is C2 or more, and the CPU
2 and analog circuit 1 continue operating. (2b) When the divided voltage Vtbz is lower than the reference voltage Vref, that is, when the power supply voltage is lower than the determination voltage VC2, in this case, the current flowing through the transistor Qsg is smaller than the current flowing through the transistor Qaa, As a result, transistor Q,. The current flowing through the transistor Qso is smaller than the current flowing through the transistor Qso. Therefore, the collector potential of the transistor Q3 becomes the °H level, which is input to the CCPU 2 and the analog circuit 1 as a battery check signal BC indicating that the power supply voltage is below the judgment voltage VC2, and the CPU 2 and the analog circuit 1 are activated. stop. The voltage doubler circuit 3 includes N-channel MO8 type field effect transistors Q, ,Q, and CMOS inverters G, -G.
, Nant gate G4, and capacitor CI. C1. One input terminal of the Nandt gate G, which serves as a control signal for the voltage doubler circuit 30, is connected to the transistor Qsa in the first power supply voltage discriminating circuit 5.
is connected to the emitter of the Nantes gate (i4's other input vIM is connected to the clock signal input terminal of the CPU2
connected to the clock signal output terminal of the The output terminal of the Nant gate G4 is connected to the inverter () and the input terminal of G3, respectively, and the output terminal of the inpark G, is connected to the gate of the transistor Q, and the inverter (il
are connected to the input terminals of each. The output line 1 of the inverter (3) is connected to the gate of the transistor Q, and the output terminal of the inverter Gg is connected to the capacitor C,
through the source of the °C transistor IQ+ and the transistor Q,
It is also connected to the connection point with the drain of. Also, the drain of transistor Q is connected to line EI,
The source of the transistor Q, which is the output terminal of the voltage doubler circuit 3, is the capacitor C! jtt is connected to the positive electrode of the Ri pond E through the transistor Q! . is connected to the emitter of In addition, inverter () and G
, are connected to the sources of transistors Q and Qt, respectively. Next, the operation of the voltage doubler circuit 3 constructed in this way will be explained with reference to the time charts shown in FIGS. 5(a) to 5(f). First, this voltage doubler circuit 3 does not operate when the power supply voltage is equal to or higher than the determination voltage VC1 of the first power supply voltage determination circuit 5. That is, when the power supply voltage is higher than the judgment type 1 voltage VC], the transistor Q+s in the first power supply voltage discrimination circuit 5 is turned on, and the Nant gate G4 is turned on.
Since one input terminal of is at the "L9 level," the same game)
4 is closed, and the output remains at the °H' level regardless of the level of the clock signal Φ (see FIG. 5(a)) applied from the CPU 2 to the other input terminal. Therefore, the voltage doubler circuit 3 does not perform voltage amplification operation. The power supply voltage is the first power supply voltage discrimination circuit 50 judgment voltage Vc+
When the voltage drops below 7°, the transistor Q,s turns off and one input terminal of the Nantes gate q4 becomes 7°. As a result, the Nant gate G is opened, and an inverted signal of the lock signal Φ is outputted from its output terminal as shown in FIG. 5(b). This inverted signal Φ is applied to the gate of the transistor Q as a signal 0 multiplex (see FIG. 5(C)) through an inverter G, and is applied to the gate of the transistor Q as a clock signal Φ (see FIG. 5(a)) through an inverter (). ) is applied to the =CIA of the capacitor CI. Further, the signal Φ1 is converted into an inverted signal Φ (see FIG. 5 (dl)) through an inverter G and a transistor Q2.
is applied to the gate of When the upper MC clock signal Φ is at the °1 level, the signal, becomes the °Il' level, turning on the transistor Q1, and the inverted signal, becomes the °L level, turning on the transistor Q.
! turns on. Therefore, the drain 'FIT pressure V(!M (see el) of the transistor Q increases to Vss+ at the negative electrode of the power supply battery E. Also, the potential at one end of the capacitor C1 is By applying the signal Φ, the positive electrode of the power supply battery E takes the potential VDD.Therefore, the capacitor C2 has a 'tlL source voltage electromotive force,
A corresponding charge is charged. Next, when the clock signal Φ is inverted to °L level, the signal 0 overlap becomes +L level.
1 level, the signal Φ becomes 'II' level, transistor Q is turned off, and transistor Q2 is turned on. Further, the potential at one end of the capacitor C1 becomes the potential Vsst at the negative electrode of the power supply battery E due to the application of the signal Φ. Therefore, by maintaining the charged IWZ pressure of the capacitor CI, the drain mixed voltage VCM of the transistor Q2 takes a potential V8S2, which is lower only outside the charging voltage, with the potential Vss+ as a reference (see FIG. 5(e)). . As mentioned above, the charging voltage is equal to the power supply voltage, so the potential VSS2
is a potential lower than the potential Vsst only by the voltage outside the power supply voltage. That is, the difference between the potentials VDD and VSS2 is twice the difference between the potentials VDD and Vss+. Now, transistor Q
, is on, this potential VSS2 is directly applied as the source potential of the transistor Q2, and is applied to the other end of the capacitor C2 whose one end is at the potential VDD. Therefore, the capacitor C7 is charged with a potential difference of 2 (g) of the power supply voltage.
As mentioned above, the transistors Q and -Qt are repeatedly turned on and off, and the transistor Q becomes the output terminal of the voltage doubler circuit 3.
A signal Vss having a potential of approximately VSS2 including ripples as shown in FIG. 5(f) is obtained across the source No.2. Therefore, when the voltage doubler circuit 3 operates, together with the turning on of the transistor Q2, the CPU 2 and the level shift circuit 8 are biased and operated with an operating voltage twice the power supply voltage. In addition, in FIG. 3, the power supply circuit F68 and the operating voltage supply voltage of the analog circuit 1 are always connected to both the positive and negative poles of the power supply battery E. Although not particularly shown, the power supply control signal PW is also input to the reference voltage circuit 7, and the circuit 7 is configured to control the temperature operation by this signal PW (see Fig. 2). ). FIG. 4 is an electrical circuit diagram showing an example of the analog circuit 1 in more detail. The analog circuit 1 of this example is a display circuit for displaying photographic information by light emission, and includes light emitting diodes Ll to Ln as display elements and resistors r r to
R+o+n, a display decoder 11, and NAND games) T and -Tn. The display decoder 11 is connected to a level shift circuit 8 (see FIG. 3), and receives display information from the CPU 2 via the same circuit 8. Each output terminal of this display decoder 11 is connected to a Nant gate T
, ~Tn, respectively, and the second power supply voltage discrimination circuit 6 (see FIG. 3) is connected to the other input terminal of the Nant gates T and ~Tn via a NOT terminal.
A battery check signal BC output from the terminals is applied to each of the terminals. And Nantes Gate T1
The output terminals of ~Tn are connected to the cathodes of the light emitting diodes L1 to Ln through resistors R1 to R1, respectively, and the operating voltage VDD is applied to the anodes of the light emitting diodes L1 to Ln, respectively. In the display circuit configured in this manner, when the power supply voltage is equal to or higher than the judgment voltage VC2 of the second power supply voltage discrimination circuit 6 and the bacteria check signal BC is at the 'L' level, the other of the NAND games )T and -Tn The input terminals of are respectively °L'
level, each gate T, -Tn opens, and an inverted signal corresponding to the output of the display decoder 11 is transmitted to the Nantes gate T.
1 to Tn output terminals. Therefore, depending on the level of this output, the corresponding light emitting diodes L, -Ln are turned off or turned on, and photographing information is displayed. Furthermore, when the power supply voltage becomes equal to or higher than the judgment voltage VC2 and the battery check signal BC becomes 1 level, the other input terminals of the Nant gates T and ~11'In each become the same level, and each Gate T,
~1゛. is closed, the outputs of these gates T, ~Tn are all at the °1■' level, and the light emitting diodes L, ~Tn are all at the °1■' level.
Ln does not light up and photographing information is not displayed. As described above, the power supply circuit of the camera of this embodiment is configured. Next, the operation of this power supply circuit will be explained again. First, when the camera stops operating and closes the display switch SW, the potential at point A increases, so
Transistor Q! F is turned on. Then, the negative operation-pressure supply end of the CPU 2 is connected to the negative electrode of the power supply battery E.
(,'P[J2 starts operating. When CPU2 starts operating, the power supply control signal PW becomes l L level, so the analog 4G circuit 1. level shift circuit 8. first and second power supply voltage The discrimination circuits 5 and 6 and the reference voltage circuit 7 also start operating.Furthermore, based on the output of the first power supply voltage discrimination circuit 5, it is determined that the power supply voltage has reached the judgment pressure V.
In a normal state where c1 or more exists, the transistor Q2g serving as a power supply switching means is turned on and the transistor Qte is turned off. After that, when the operating force is removed from the display switch SW, the switch SW8 opens due to its own behavior, but since the transistor Q28 is on, the CPU2
The various circuits 1, 5 to 8 surrounding the circuits 1, 5 to 8 maintain their operating states. Next, when the power supply voltage drops to the determination voltage VC1 or higher, the first power supply voltage determination circuit 5 detects this and turns on the transistor Q24, thereby turning on the transistor Q! 8 is turned off and transistor Q20 is turned on. At the same time, by turning off the transistor Q+i, the amplification command signal As of °H level is supplied to the voltage doubler circuit 3, and the voltage doubler circuit 3 starts the amplification operation. Therefore, the CPU2 is disconnected from the negative electrode of the power supply battery E by turning off the transistor CL6, while the transistor Q! When +1 is turned on, it is connected to the □voltage circuit 3 that started operating, and it starts operating at an operating voltage that is twice the power supply voltage. In addition, the level shift circuit 8 detects the switching of the 90 operating voltage and shifts the voltage level of the signal exchanged between the CPU 2 and the analog circuit 1 by one point. As a result, the CPU 2 and the analog circuit 1 continue to operate as if the low source voltage were higher than the determination voltage VCI. Next, the power supply voltage further decreases to 1 (constant voltage 1 voltage Vc
If it becomes below z, the second power supply voltage discrimination circuit 6 detects this and inputs a voltage check signal BC of 'H level' to the CPU 2 and the analog circuit 1. Upon receiving this battery check signal BC, CP'U2 and analog circuit 1 stop operating, and CPU2 inverts power supply control signal PW to the '11' level. As a result, the first and second power supply voltage discrimination circuits 5 and 6. The reference voltage circuits 7 are also stopped from operating. The camera and the main filter are connected to each other. In the power supply circuit of this embodiment, the implementation shown in FIG. Compared to the circuit in the example, one more low source voltage discrimination circuit is required, but the current consumption in this discrimination circuit can be suppressed to several tens of μ or less, so from the viewpoint of the overall current consumption, As described above, according to the present invention, microcomputers have a higher minimum operating voltage in °C than ordinary analog circuits, but their current consumption is extremely small. is operated through a voltage amplification circuit at all times or at appropriate times, making it possible to effectively utilize the residual electromotive force of batteries over a long period of time, which was previously discarded early. An economical camera power supply circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a power supply circuit of a camera showing one embodiment of the present invention. FIG. 2 is a block diagram showing the structure of a power supply circuit of a camera showing another embodiment of the invention. FIG. 3 is an electrical circuit diagram showing in more detail the power supply circuit shown in FIG. 2, and FIG. 4 is an electrical circuit diagram showing an example of the analog circuit shown in FIGS. Circuit diagram, Figure 5(a)
〜(fl is ``2 Memory 3 represents the waveforms of various signals in the voltage doubler circuit shown in the figure -1 time chart O 1... Ambiguous... Analog circuit 2... Microcomputer (CPU) 3.
...... Double pressure circuit 1''1'l (y+j pressure amplification circuit) 5 ...... First 71i, source '1-if, l
Upper edition separate circuit J)...Power battery Qts+ Qza...Switching transistor (Tunyuan switching switch SW, SW,...'+'HL source September yuki switch (jx ;, source switching means) Vct ... publication foot ↑ 1L pressure (microcomputer's most important i!il)
(W, pressure) Patent D 11 people Orinokus Optics” Nigyo Co., Ltd. Shichito Fujikawa ゛()

Claims (2)

[Claims] (1) In a camera equipped with an i-microcomputer that sequentially controls camera operations, an analog circuit that operates even below the minimum operating voltage of this microcomputer, and a power supply battery that supplies operating voltage to the camera's electric circuit. A power supply circuit for a camera, characterized in that a voltage amplification circuit is provided for amplifying the electromotive voltage of the power supply battery and supplying the microcomputer as an operating voltage. (2) In a camera equipped with a microcomputer that sequentially controls camera operations, an analog circuit that operates even below the minimum operating voltage of this microcomputer, and a power battery that supplies operating pressure to the camera's electric circuit, a power supply voltage discrimination circuit that determines whether the electromotive voltage of the power supply battery is lower than the minimum operating voltage of the microcomputer; a voltage amplification circuit that amplifies the electromotive voltage of the power supply battery; The battery or the voltage amplification circuit is selectively connected, and when the electromotive voltage of the power supply battery becomes lower than the minimum operating voltage of the microconbeater, the voltage is determined based on the output of the power supply voltage discrimination circuit. A power supply circuit for a camera, comprising: power supply switching means for connecting the voltage amplification circuit to the microcomputer and supplying the output voltage of the amplification circuit to the microcomputer as an operating voltage.