JPS5942498B2 - Analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter (A/D converter), and its purpose is to sequentially A/D convert a large number of analog input signals with a very small increase in the number of component circuits, and to convert the same or An A/D that can obtain digital values on different output lines without sacrificing accuracy, and even if the measurement time is relatively short, the monotonically increasing nature of the output digital signal value is maintained in response to the monotonically increasing analog input signal. is to obtain a converter.

In addition, the present invention provides a high-precision A/D converter that is not affected by changes in element characteristics due to temperature changes, aging, etc. on a single chip.
The configuration is such that it can be realized with MO8IC, and does not affect the accuracy of variation conversion in the CMO8 manufacturing process.

When the A/D converter of the present invention is installed in an automobile or the like and used in an electronic circuit that controls the engine state based on the temperature of cooling water, etc., it is extremely unaffected by noise generated from the engine, etc. By making the power supply to the detection sensor and the power supply to the A/D converter the same, the digital output value does not change even if the power supply voltage fluctuates.

Furthermore, according to the present invention, digital output value processing, calculation,
This realizes an A/D converter suitable for easy integration in the same chip as a digital signal processing section that performs determination and the like.

An example of a conventional delta modulation type A/D conversion circuit is shown in FIG. 1, and examples of signal waveforms at each part thereof are shown in FIG. 2.

The operation of this circuit will be explained. First, apply the analog voltage ■1N to be converted into a digital value to the (+) side input terminal 2 of the differential amplifier 1, and add a resistor 4 to the (hot side input terminal) of the external power.
(R1) and a capacitor 3 (C1), the reference voltage +■
□ Or -vFL is applied.

This reference voltage is electronically switched alternately by a switch 7, and the contact of the switch 7 is connected to the "H" level of the output Q of the D flip-flop 5.
Controlled according to 'L'.

The state of the output Q of this D flip-flop 5 is shown in FIG.
As the output voltage of the Nodotoku differential amplifier 1 reaches the threshold value of the D input terminal and becomes smaller than it, it becomes 'H' depending on the sampling timing of the clock pulse (Fig. 2a).
♂゛Also, if the voltage at the (@ input terminal of the differential amplifier 1 is vc, then this value is the voltage applied to the 11i voltage■, N
When it is smaller than , the output of amplifier 1 is set to be higher than the threshold value of D input, and as a result, Q becomes 1lH1l depending on the clock sampling timing,
Switch 7 is connected to the 8 side.

This state is maintained as long as the output voltage of the amplifier 1 does not become smaller than the threshold value of the D input.

During this time, as shown in FIG. 2b, the capacitor 3 (C1) is charged in the direction of 10R through the resistor 4 (R1), so VC continues to increase with time until a certain time t.

A little before ■ exceeded 1N. Therefore, the output of the differential amplifier 1 is inverted, and the output Q of the D flip-flop 5 is at the next clock timing t.

The state changes to "LI".

Q becomes aLl 7, switch 7 is connected to terminal 9, i.e. -V
The charge charged in C1 is connected to R, side and goes in the direction of -vR, through R1, and T discharge1i L,'initial f, -2s6·VC decreases with time and becomes smaller than vlN. Then, the output of the differential amplifier 1 becomes positive again, and at the next clock sampling timing, Q becomes 1H1 and the switch 7 is connected to the terminal 8, that is, the +vR side again.

Once the measurement time is determined, these two states are repeated during that time, but since the differential amplifier is extremely sensitive, the value of vc is a sawtooth shape with a small amplitude above and below 1N. It becomes a wave.

Here, the Q output of the D flip-flop 5 instructs the up/down counter 6 to amplifier down, and the amplifier/down counter 6 counts up and down the clock in the measurement frequency circuit, respectively, and the result is A.
/D conversion output.

10 is the clock signal terminal in Figure 2a, 11 is the start/
This is a stop control signal terminal, shown in FIG. 2d, and shows an example of its measurement period.

The amplifier period t and the down period t2 in the amplifier down instruction correspond to the rising period and falling period of the sawtooth wave, respectively.

The ratio of tl and t2 is equal when ■1N is the midpoint between +vR and -■R, and when vlN is higher than this, 11>1. and when it is low, tl<t2.

Now, if the number of pulses at tl is m% and the number of pulses at t2 is n, then the count amount of the up/down counter in one cycle of the D flip-flop 5 is (mn), and the value integrated over the measurement time is A. /D conversion amount.

Note that 12 to 15 are output terminals.

The above is an overview of the operation of the delta modulation type A/D converter path.

One drawback of the above circuit is that although the timing of the start and end of the measurement period is synchronized with the clock, it is completely asynchronous with the switching timing of the Q output of the D flip-flop 5.

(See Figure 2 d) Therefore, since the starting point of the measurement period is at a different position, the count in the first period of the flip-flop 5 is not necessarily (m-n), and in the worst case (-n).
) only.

Also, at the end of the measurement, only the worst case (m2) is obtained for the same reason.

Therefore, the characteristics may have poor monotonicity.

In FIG. 2, α and β indicate the time lag in that case.

This drawback has the disadvantage that, although the error can be reduced by extending the measurement time sufficiently, the error increases if the measurement time is shortened.

Another drawback of the circuit system shown in FIG. 1 is that it becomes a problem especially when a plurality of input analog signals are switched and converted using a multiplexer or the like, or when the analog value of the input signal differs significantly from sampling to sampling.

That is, now, the input voltage at the time of the first measurement is vlNl,
Let the input voltage at the second measurement be v1N2, and v1N2-
(2) Suppose that 1N2 is a value of the same order as vlN or v1N2.

At the end of the first measurement, capacitor 3 (C1)
is charged to a potential close to vlNl, and therefore, the initial state potential of the capacitor 3 (C1) during the second measurement, that is, when v1N2 is A/D converted, is approximately VlNl.

For this reason, the potential of the capacitor 3 changes from around 1N1 to v
The period until it changes to around 1N2 is flip-flop 5.
The output continues to be in the 'H' state, and during this time the up/down counter continues to count up.

After this, when the potential of the capacitor 3 slightly exceeds v1N2, the above-mentioned steady state is entered for the first time, and the up/down counter repeats the up and down states and performs normal operation.

In this way, until the steady state is reached, in order to bring the potential of the capacitor 3 closer to the input potential, only up or down counts are performed, and this count is
0 superimposed as an error on the A/D converted digital value.The present invention attempts to solve such a problem, and the present invention will be described below using examples.

FIG. 3 shows one embodiment of the invention.

FIG. 4 is an explanatory diagram of waveform examples of various parts in the embodiment of FIG. 3.

In FIG. 3, 10L102 are input terminals for analog signals to be independently converted into digital signals;
03 is an analog multiplexer, 1104 is an input terminal for a switching signal that switches the multiplexer 103, 105 is a differential amplifier, 106 and 107 are capacitors and resistors that constitute an integrating circuit, respectively, 108 is a terminal that supplies a reference voltage VCC, 109 .110 is a P-channel MO8FET and an n-channel MO8-FET that constitute an electronic switch that connects or disconnects the input of the integrating circuit consisting of 106 and 107 to Vcc or ground, 111 is a D flip-flop, 112 is an inverter, and 113 is an inverter. Up/down counter; 114 is an input terminal for a load signal to be supplied to the up/down counter 113; 115 is an inverter 112;
and an input terminal for a clock supplied to the counter 113, 116 is a D flip-flop, 117 is an input terminal for a start/stop signal supplied to the D input of the flip-flop 116, 118 and 119 are 4-bit latch circuits, respectively; 121 are launch circuits 118.
Input terminal of strobe supplied to 119, 122-12
5 and 126 to 129 are latch circuits 118,
This is an output terminal for taking out the output of 119.

Also, in comparison with the circuit in Figure 1, 105 months and 106 months are 3 months.
, 107 becomes 4, 109 and 110 become 7, 111 becomes 5
, 113 becomes 6, 115 becomes 10, 117 becomes 11,
They correspond to each other.

Next, the operation of the embodiment shown in FIG. 3 will be explained using FIG. 4.

When the switching signal shown in FIG. 4B is applied to the terminal 104 and the signal is 1H'', the analog potential vA of the terminal 101 is output 0.
is applied to the (+) input of the amplifier 105, and (B
) is 1L1, the analog potential of terminal 102 is V
B appears at output O and is applied to the (+) input of amplifier 105.

Now, VA > VB, and CB) is lL′” to wHl
Considering the case where the voltage changes to , the potential of the capacitor 106 is near VB, and on the other hand, the output O of the amplifier 103 becomes vA, so the output of the amplifier 105 becomes 1H1. The output Q of is wHl, Q is 1L@, FET 109 is ON, 11
0 becomes OFF, capacitor 106 starts charging towards Vcc through 107, and capacitor 106
The potential of increases.

Now, the allowable range of analog potentials vA and VB is set to 0.2 Vc.
c ~0.8 Vcc, capacitor 106
The time required for the potential of F to change this tolerance range is F
If the Q kJ of ET109゜110 is selected to be sufficiently small due to the low resistance, it will be approximately 1.4C2R2, so the time after the switching signal changes, that is, 1.4C.
Delay by 2R2 (start/stop signal of 0 becomes H)
"I'll do it.

In this way, you can start/start until the system enters steady state.
The stop signal is kept at 'L', and the counter 11
3 is in a disabled state, no counting operation is performed, and the occurrence of errors caused by counting during an unsteady state in FIG. 1 is eliminated.

This charge/discharge circuit indicates that when the input voltage is equal to the center voltage, the charging time and discharging time are equal, and when the input voltage is higher than the center voltage, the charging time is longer than the discharging time, and when the input voltage is lower than the center voltage, the charging time is equal to the discharging time. is set so that the charging period is shorter than the discharging time.

Furthermore, unlike the conventional example, this embodiment uses a D flip-flop 116 to provide a start/stop synchronization circuit, and instead of directly inputting the start/stop signal to the en-aple terminal of the counter 113, it inputs the start/stop signal via the D flip-flop 116. connected, flip-flop 11
The Q output of the flip-flop 111 is connected to the rank terminal No. 6.

Therefore, the signal applied to the E terminal for controlling the movement of the counter 113 is the output signal of the flip-flop 111, that is, the charge/discharge control signal of the integrating circuit "discharge → charge °'
It changes in accordance with the switching timing.

This situation is shown in FIG. 4E. After the specified time, start/
When the stop signal changes from 1H'' to 1L'', the subsequent switching signal, that is, the output Q of the flip-flop 111 becomes I
At the timing when IL" changes to H, the output of the clock input terminal 115 also changes from lHl to 1L", and the counter 1
13 stops counting, the A/D conversion of the analog signal ■ is completed, and the contents are the outputs Q1 to Q4 of the counter 113.
It is raining.

Although the present embodiment shows the case of 4-bit output, this is for the purpose of simplifying the explanation and drawings, and the present method can easily realize higher-precision conversion.

In this way, by synchronizing the start/stop signal with the output of the flip-flop 111, whose cycle and timing are determined by the magnitude of the input analog signal, and supplying it to the up/down counter, errors caused by conventional asynchrony can be avoided. This eliminates A/D conversion with good monotonicity.

■After the A/D conversion in step 9 is completed, the switching signal at terminal 104 becomes 'H'.
” changes to l L I, and the timing of A/D conversion of the analog signal vB applied to the terminal 102 begins.

At the same time that the switching signal at the switching terminal 104 changes from H1 to 1L'', a strobe pulse is applied to the strobe terminal 120 of the latch circuit 118, the output of the counter 113 is transmitted to the terminals 122 to 125, and the next strobe is applied as it is. The digitally converted value of VA is output to terminals 122-125.

Similarly, after the A/D conversion of VB is completed, the switching terminal 10
At the same time as the switching signal No. 4 changes from L1 to IHL, a strobe pulse is applied to the strobe terminal 121 of the latch circuit 119.
and the digitally converted value of VB is applied to terminal 12.
6 to 129.

The load signal whose waveform is shown in FIG. 4H is connected to the load terminal 114.
is applied to preset the up/down counter 113 to a predetermined value, and the start/stop signal is lL.
It is applied just before changing from W to 'Ha. For example, if you want to convert it into a digital value as an analog value measured from the system ground, only the MSB of Q1 to Q4 should be "H".
The other bits may be set in advance to lLW.

At this time, when the analog input is 0.5Vcc, the up-count number and down-count number are the same, and the output of the counter 113 at the end of measurement is "H", "L", and "L".
``L1, full scale ``H''``H''``H'
"H" (D is the midpoint, which is the midpoint of the measurement range 0.2Vcc=0.8VCC described above.

That is, the load pulse 114 initializes the counting circuit to the center voltage at the start of charging.

Next, analog multiplexer 103 and differential amplifier 1
Examples of configurations using the CMO 8 of 05 are shown in FIGS. 5 and 6, respectively.

Next, the operation of these circuits will be explained.

In FIG. 5, when the switching signal input terminal 104 is 1H1, the P-channel transistor T1 and the n-channel transistor T2 are turned on, and the P-channel transistor T
3 and n-channel transistor T4 are turned off, the input of terminal 101 is transmitted to output O, and the input of terminal 102 is disconnected.

Conversely, when terminal 104 is 1L1, the input of 102 is output 0.
and the input of 101 is disconnected.

In this way, an analog multiplexer is configured by CMO8.

Note that each substrate of the P-channel transistor and the n-channel transistor is connected to the highest voltage and the lowest voltage of the system, respectively.

In FIG. 6, T7. T8 is P that constitutes the differential amplification section.
Channel transistor pair, T5. T6 is T7. A current mirror circuit that supplies a constant current to the circuit of T8, R3 is a resistor that determines the current value of the constant current, and T9°Tlo is a current mirror circuit that supplies a constant current to the circuit of T8. T
8 active loads.

The output of this differential amplifier is taken out from the drain of T8,
It is further amplified by a circuit consisting of an n-channel transistor Tll and a load resistor R4, and becomes an output.

As an example of how to configure R3 and R4, P
There is a way to make it using the same process as the well layer.

In this case, the sheet resistance value of the P-well layer is usually around 5KQ/mouth, while R3 and R4 are from several 1KΩ to several 10KΩ.
Since the resistance is 0Ω, it is convenient in terms of size and integration into an IC.

Then, using the clock, a switching signal to terminal 104, terminal 1
Start/stop signal to 17, terminal 120.121
An example of a circuit for generating a strobe signal to terminal 114 and a load signal to terminal 114 is shown in FIG.

201 is an X frequency divider whose output is inverted at the rising edge of the input terminals 202 to 207 to which a clock is applied; 210
~213 is N, A N D gate, 214 ~ 216
is an AND gate, 104°111.120,121
, 114 are input terminals for inputting switching signals, start/stop, strobe 1, strobe 2, and load signals, respectively.

This circuit provides various control pulses as illustrated in FIGS. 4B, D, F, G, and H.

Figure 7 shows an example of a configuration using a frequency divider array and gates, but there are various other configuration methods. For example, start/stop signals, load signals, etc. are implemented using delay circuits. It is also possible to generate the switching signal by delaying the detection of the rising and falling edges of the switching signal.

In the circuit of FIG. 3, fully explained 103 and 105
The other circuits, except for the integration circuits 106 and 107, are already C
All of the circuits are digital circuits that are realized with MO8, so this circuit can be implemented with CMO8 with only a few external components.
It can be configured as a chip.

Resistor 107 in the integrating circuit needs to be selected to be sufficiently larger than the on-resistance of FET 109, 'NO, and is usually selected to be about IMΩ, so it is not necessarily advantageous to include it in the IC chip, but it may be difficult to prevent fluctuations in Rρ value, temperature changes, etc. Since it does not directly affect the conversion accuracy, it is of course possible to incorporate it into the IC chip.

In this embodiment, the case is shown in which there are two types of analog input signals, vA and VB, and two types of digital output terminals, but even if there are three or more types, only the analog multiplexer and seven latch circuits need to be added.

In addition, in the case of a configuration in which the necessary digital processing is performed on the digital value obtained until the next load signal arrives, the latch circuit is not necessary and only the number of analog multiplexer circuits is increased. Just let it happen.

This means that a system that repeatedly detects various temperatures, etc. and performs various controls can be constructed with an extremely small number of circuits, and can be integrated into a single chip, which is extremely effective.

Moreover, in the present invention, the characteristic values of the CMO 8 affect the conversion accuracy, but in the above embodiment, the variation in the threshold voltage vT of the differential transistors T7 and T8 in FIG. variation and FET109
, 110, the variation in on-resistance is very small.

Among these, the variation in the threshold voltage vT of T7 and T8 is extremely small and can be ignored if they are made close to each other in the same chip.

Further, the gain of the amplifier 105 should be set so that a sufficient value can be obtained at the limit of variation, and the gain of the FET 109,
As for the on-resistance of 110, there is no problem in practice as long as it has a sufficient ratio with R2 even in the worst case.

In addition, when an analog multiplexer is generally configured with MOS transistors, in order to lower the on-resistance,
In many cases, a significantly large chip area was required, but in this example, the differential amplifier was constructed with MOS transistors, so the input impedance was extremely high, and therefore the on-resistance of the multiplexer was only a few Ω. , the required area may be extremely small.

Further, by configuring these in the same chip, the parasitic capacitance is also reduced, which is even more advantageous.

Another feature of the invention is that it is extremely robust to extraneous noise.

That is, in the above embodiment, the clock is nH
Only the noise at the moment when the signal changes from "W" to "L" is a problem, and the noise that occurs at other times is not a problem at all.

Furthermore, even if noise is added at the moment when the above-mentioned clock changes from 'H' to 1L@, it will only change the output digital value by one count, and the influence on the entire digital output value will be extremely small.

This shows that it is extremely useful for use in conditions such as automobiles where intermittent but large-value noise often exists as a background.

Another feature of the present invention is that when converting the temperature detected by a thermistor into a digital value, a stable digital value can be obtained even in an environment where the power supply voltage fluctuates significantly, such as in an automobile power supply.

FIG. 8 shows one application example, in which a temperature detection thermistor 300
is connected to the same power supply terminal 304 as the A/D converter 303 via a standard resistor 301, and a change in the power supply causes the VCC of the A/D converter 303 to change at exactly the same rate as the thermistor output voltage, so the output The digital value at terminal 305 does not change at all.

Still another feature of the present invention is that it can be integrated into the same chip as the digital signal processing section. In this case, the clock and control pulse generation section that drives the digital section and the A/D conversion section can be integrated into the same chip. Not only can the clock and control pulse generation sections be shared, but the latch circuit section can be eliminated as mentioned above depending on the configuration of the digital section, resulting in a significant reduction in circuitry, chip area, and cost. There is.

As described above, the present invention is an A/D with excellent performance.
A converter is provided.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional A/D converter for explaining the present invention, a=d in FIG. 2 is a signal waveform diagram of each part in FIG. 1,
FIG. 3 is a block diagram of an EA/D converter according to an embodiment of the present invention, FIGS. 4A-H are signal waveform diagrams of each part of FIG. 3, and FIGS.
The diagrams are a specific circuit diagram of a part of the embodiment shown in FIG. 3, and a specific circuit diagram of a part of the embodiment shown in FIG.
The figure is an example of a circuit for generating various control signals from ranks, and FIG. 8 is a schematic diagram of an example of the application of the present invention. 101, 102... Analog signal input terminals,
103...Multiplexer-1104...
...Switching signal input terminal, 105...Differential amplifier, 106,107...Capacitor, resistor, 1
08...Reference voltage supply terminal, 109, 110.
...FET, 111...Flip-flop, 113...Amplifier down counter, 116
...Flip-flop, 11T...Start/stop signal input terminal, 118, 119...
... Latch circuit, 120, 121 ... Strobe input terminal, 303 ... A/D converter.

Claims (1)

[Claims] 1. An input switching circuit that includes an analog multiplexer and switches two or more input signals; and a comparison between the input voltage switched by the input switching circuit and a reference voltage that is the output of a charging/discharging circuit. a comparator circuit that outputs bi-level when the input signal is higher than the reference voltage and outputs low-level when the input signal is lower than the reference voltage; a synchronous circuit that outputs a signal corresponding to the output of the comparison circuit, a charging/discharging circuit that supplies a voltage corresponding to the output of the first synchronous circuit to a resistor for the charging/discharging circuit, and a start/stop signal that determines the counting period to the synchronous circuit. A start/stop circuit uses the output as a clock to reset the timing and instructs the counting period of the counting circuit, and a start/stop circuit that initializes the counting circuit to the center voltage at the start of counting and counts in the forward direction when the output of the synchronous circuit is at bi level. , a counting circuit that counts in the reverse direction when the output of the synchronous circuit is at a low level, counts the charging period as one cycle, and counts it as an average of the period of the output of the start-stop synchronous circuit of the first period, and a counter that corresponds to the number of input signals of the first period. An analog/digital converter comprising: a latch circuit that sequentially holds the output of the counting circuit; and when the period ends, the state of the output of the counting circuit is output as a digital output as an output of analog-to-digital conversion. converter. 2 All circuits except charge/discharge circuit are integrated into 1 chip CMO8
The analog-to-digital converter according to claim 1, characterized in that it is implemented as an IC. 3. The analog-to-digital converter according to claim 1, wherein the start/stop control signal is generated using a clock or its original signal. 4. Claim 1, characterized in that the start/stop control signal generation circuit generates the start/stop control signal for the counting circuit with a delay of at least a time constant of the charging/discharging circuit from the start of operation of the charging/discharging circuit. The analog-to-digital converter described in .