JP2000114896A - Circuit and method for controlling gain - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce temperature dependence in the gain of a gain control circuit. SOLUTION: A clock signal from an oscillator 1 is inputted to a frequency divider circuit 2 and a constant number (gain control constant) from the outside is inputted from a constant input device 7 to the frequency divider circuit 2. The frequency divider circuit 2 divides the frequency of the clock signal from the oscillator 1 according to the constant from the constant input device 7 and the frequency divided clock signal is respectively inputted to equivalent resistors 3 and 4 composed of switched capacitors. The equivalent resistors 3 and 4 are variable resistors to change resistance corresponding to the frequency of a clock signal to be driven and the gain of this circuit is determined by the resistance ratio of the variable resistance values, namely, the frequency dividing ratio of the frequency divider circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain control circuit and a control method thereof, and more particularly to a gain control circuit using a switched capacitor circuit as a resistance element for determining a gain of an amplifier and a control method thereof.

[0002]

2. Description of the Related Art Conventionally, this kind of gain control circuit has been used for the purpose of giving an arbitrary gain to an input signal as shown in, for example, Japanese Patent Application Laid-Open No. 7-40652. FIG. 11 is a block diagram showing an example of a conventional gain control circuit. In FIG. 11, an input signal is input to a base of a transistor 11, and a collector of the transistor 11 is connected to a DC power supply via a resistance element 20. The circuit composed of the transistor 11, the resistance element 20, and the variable resistance element 16 is a common-emitter amplifier circuit that amplifies an input signal and outputs a signal from a collector.

The variable resistance element 16 is a variable resistance element called a PIN diode, and its resistance value changes in inverse proportion to a flowing DC current value. Transistor 11
Is connected to the variable resistance element 16 and the collector of the transistor 13 forming a differential circuit. One of the variable resistance elements 16 is grounded via a bypass capacitor 15 and connected to the collector of the transistor 12 forming a differential circuit.

[0004] Transistors 12, 1 constituting a differential circuit
The collector current 3 can be controlled by the respective base voltages. The gain control voltage in the gain control circuit is input to the base of the transistor 12. The base of the transistor 13 is grounded via the DC power supply 19. The emitters of transistors 12 and 13 are connected to resistance elements 18 and 17 respectively.
Is connected to the constant current source 14 via the. The power supply 14 is a constant current source circuit for flowing a constant current, and one terminal is grounded.

Next, the operation of this circuit will be described. The input signal input to the transistor 11 is amplified and then output from the collector. As described above, the circuit composed of the transistor 11, the resistance element 20, and the variable resistance element 16 is a common-emitter amplifier circuit centered on the transistor 11.

The gain of this circuit is determined by the AC resistance ratio between the collector resistor 20 and the variable resistor 16. The resistance value of the variable resistor 16 changes in inverse proportion to the DC current flowing through the resistor, and the current flowing through the variable resistor is the collector current of the transistor 12. The current flowing through the constant current source 14 is the sum of the collector currents of the transistors 12 and 13 and is always constant. Therefore, the current flowing through the variable resistor 16 is the transistor 1
It is determined by the difference between the DC voltages input to the bases of 2 and 13.

In this circuit configuration, the base of the transistor 13 is connected to the DC power supply 19 so that the voltage of the base is constant, while the base of the transistor 12 is used as a gain control terminal of the gain control circuit. Therefore, in the present circuit, by changing the base input voltage of the transistor 12, that is, the gain control terminal voltage, and controlling the DC current flowing through the variable resistance element 16 whose resistance value changes in inverse proportion to the DC current flowing therethrough, The gain control is realized by changing the resistance ratio between the resistor 20 and the variable resistor 16 in the common-emitter amplifier circuit.

Next, another example of the prior art will be described. Conventionally, this type of gain control circuit is described in, for example,
Moon, International Journal of Electronics, Vol. 62, No. 3, pp. 417-424 (Int
international Journal of Ele
ctronics Vol. 62, No. 3, p. 41
7-24) "for the purpose of giving an arbitrary gain to the input signal.

FIG. 12 is a block diagram showing an example of a conventional gain control circuit. In FIG. 12, reference numeral 29 denotes an operational amplifier, and switch circuits 21, 22, 23, 31, 32,
Reference numeral 33 denotes a MOS switch realized by an analog MOS transistor. The impedance elements 24, 25, 2
Reference numerals 6, 34, 35, and 36 denote passive elements, for example, impedance elements realized by resistors and capacitors. The input signal Vin is connected to a switch 21. One terminal of the switch 21 is connected to the operational amplifier 2 via an impedance element 24.
9 inverting input terminals. The non-inverting input terminal of the operational amplifier 29 is grounded.

As shown in FIG. 12, m switches and impedance elements on the input side are connected in parallel to the input terminal Vin and the inverting input terminal of the operational amplifier 29 as one set. The inverting input terminal of the operational amplifier is connected to the switch 31.
To the output terminal of the operational amplifier via the impedance element 34, that is, the Vout terminal. Similarly to the input side, on the feedback side, n switches and impedance elements are connected in parallel to the inverting input terminal of the operational amplifier 29 and the output terminal of the operational amplifier as one set. The switch control circuit 39 is a circuit for controlling on / off of switches connected to the input side and the feedback side, and a control signal from the switch control circuit 39 is connected to each switch.

Next, the operation will be described. The circuit shown in FIG. 12 has a configuration of a typical inverting amplifier circuit. The gain of this circuit is such that the input impedance connected between Vin and the inverting input terminal of the operational amplifier 29, and the output terminal of the operational amplifier 29 are inverted. It is determined by the ratio with the feedback impedance connected between the input terminals. If the input impedance connected between Vin and the inverting input terminal of the operational amplifier 29 is Zi, and the feedback impedance connected between the output terminal and the inverting input terminal of the operational amplifier 29 is Zf, the input / output relationship of this circuit is Vout = − (Zf / Zi) · Vin (1)

Now, suppose that, of the m switches on the input side, only switch 21 is on and all the other switches are off by a control signal from the switch control circuit. , Switch 3
Assuming that only 1 is on and all others are off, the input / output relationship of this circuit is as follows from equation (1): Vout = − (Zf1 / Zi1) · Vin (2)

If the input impedances 24, 25,
26, ie, Zi1, Zi2,..., Zim, and the impedances 34, 35, 36 on the feedback side, ie, Zf1, Zf2,
.., Zfn all have the same impedance value, the input / output relationship of this circuit is given by Vout = −Vin from equation (2), and the amplifier circuit has a gain of 1.

Next, an example in which the gain control is different from the above will be described. Now, suppose that among the m switches on the input side by the control signal from the switch control circuit, the switch 21
And switch 22 are on and all other switches are off, and among the n switches on the feedback side, only switch 31 is on and all others are off, the input / output relationship of this circuit is From equation (1), Vout = − {Zf 1 / (Zi1‖Zi2)} · Vin (4) Note that “‖” indicates a parallel combined resistance value.

Assuming that the input impedances 24, 2
, Zi1, Zi1, Zi2,..., Zim, and the feedback-side impedances 34, 35, 36, ie, Zf1, Zf.
Assuming that the impedance values of 2,..., Zfn are all the same, the input / output relationship of this circuit is as follows from equation (4): Vout = −2Vin (5) Become.

As described above, in a typical inverting amplifier circuit configuration like this circuit, the ratio between the impedance value connected to the input and the impedance value forming the feedback circuit is controlled by the switch control circuit. The gain can be arbitrarily varied by setting the switch on / off by a signal.

[0017]

A problem of the first conventional example is that the temperature dependence of the circuit gain is large.
If the temperature dependence of the gain is large, accurate gain control cannot be performed where the temperature fluctuation is large. The reason is that the above-described circuit uses a passive resistance element, and the passive resistance element generally has a large temperature coefficient. Therefore, in the conventional gain control circuit which controls the gain by the resistance ratio, the fluctuation of the gain due to the temperature fluctuation becomes large.

A problem of the second conventional example is that the capacitive output load of the operational amplifier is large. If the capacitive load is large, the band becomes narrow as a gain control circuit, and it cannot be applied to the high band field. The reason is that a plurality of switches constituted by MOS transistors are connected in parallel to the output.

Japanese Patent Application Laid-Open No. Hei 5-7117 discloses an example of an automatic gain control amplifier using a switched capacitor circuit as a resistor for determining the gain of the amplifier. In this example, a circuit configuration has been proposed for automatically minimizing the fluctuation of the output level when the level of the input signal changes. That is, the peak of the output signal of the amplifier is detected, the voltage-controlled oscillator is controlled with the inverted value of the detected voltage, and the oscillation clock is used as the drive clock signal of the above-mentioned switched capacitor circuit. When the value becomes large, the oscillation frequency of the voltage controlled oscillator is controlled to vary the period of the drive clock signal of the switched capacitor circuit, thereby controlling the equalization resistance value. The control of the resistance value automatically controls that the gain of the amplifier is suppressed and the output signal level becomes large as a result.

As described above, the switched capacitor circuit is used as the resistor for determining the gain of the amplifier, and the frequency (period) of the oscillation clock of the voltage controlled oscillator is continuously controlled in accordance with the input signal level. As a result, an automatic gain control amplifier having good characteristics can be obtained by continuously controlling the equalization resistance value of the switched capacitor circuit.

However, according to the technology disclosed in the above publication,
Since the equalization resistance value of only one of the switched capacitor circuits functioning as a resistor element for determining the gain of the amplifier is controlled by changing the period of the output clock signal of the voltage controlled oscillator, the gain of the amplifier is equal to the resistance value. (The gain of most amplifiers is the same), the absolute accuracy of the amplification gain is not good, and there is also a problem that it has temperature dependence.

An object of the present invention is to provide a gain control circuit whose circuit gain is hardly dependent on temperature fluctuation.

Another object of the present invention is to provide a gain control circuit having good absolute gain accuracy.

Still another object of the present invention is to provide a gain control circuit having good linearity in gain control.

Another object of the present invention is to provide a gain control circuit which reduces the area occupied by a circuit when a switch-switching type configuration is provided in an IC (integrated circuit).

Still another object of the present invention is to provide a gain control circuit in which the output load of a drive circuit for driving a switch is reduced when a switch switching type configuration is provided in an IC.

[0027]

According to the present invention, there is provided a gain control circuit for determining a gain of an amplifier based on a ratio of resistance values of first and second resistance elements, wherein the first and second resistance elements are determined. First and second switch capacitor circuits each functioning as a second resistance element, and first and second drive clock signals for driving each of the first and second switch capacitor circuits are generated. A gain control circuit comprising: a clock signal generating unit that controls the period ratio of the first and second drive clock signals;

The clock signal generating means includes: an oscillator that oscillates a clock signal having a fixed period; a frequency divider that divides the clock signal having the fixed period to output the first and second drive clocks; It is characterized by having.
Further, the control means includes frequency division number setting means for setting first and second frequency division numbers in the frequency divider for generating the first and second drive clocks, respectively. I do.

Further, the frequency division number setting means is capable of inputting a constant for setting the first and second frequency division numbers from the outside. Further, the period ratio is determined by a ratio of the two constants.

According to the present invention, the gain of the amplifier is determined by the ratio between the resistance values of the first and second resistance elements, and the first and second switched capacitors are used as the first and second resistance elements. A gain control method for a gain control circuit, wherein the first and second switched capacitor circuits are driven by first and second drive clock signals, respectively, using the first and second switched capacitor circuits. The gain control method is characterized in that the gain is determined by the period ratio of each drive clock of the two switched capacitor circuits.

Further, the present invention is characterized in that the period ratio of the first and second drive clocks is set by an external setting. Further, a clock signal having a constant period is divided by a frequency divider with first and second frequency division numbers, respectively, to obtain the first and second drive clocks, and a ratio of the first and second frequency division numbers. Is set externally.

According to the present invention, in a gain control circuit for determining a gain by a resistance ratio, each resistance element is constituted by an equivalent resistance composed of a switched capacitor. Therefore, it is not necessary to use a resistance element of a general passive element. Further, the fact that the equivalent resistance value of the switched capacitor is determined by the cycle for driving the switched capacitor and the capacitor value is used. Therefore, in the present gain control circuit that realizes the gain control by the resistance ratio, the gain can be changed by controlling the cycle of the clock signal for driving the switched capacitor.

In the present invention, since it is not necessary to use a general passive resistor, a chip area occupied by the circuit can be reduced when the present circuit is configured as an IC. Further, the gain control is realized by changing the cycle for driving the switched capacitor, that is, changing the frequency division ratio of the frequency dividing circuit. Therefore, the gain can be controlled relatively easily and accurately.

[0034]

Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of the first embodiment of the present invention. The equivalent resistances 3 and 4 are equivalent resistances constituted by a switched capacitor type circuit described later. The oscillator 1 is a unique frequency generation source, and inputs a clock signal to the frequency dividing circuit 2. The frequency dividing circuit 2 is a digital frequency dividing circuit that divides the clock signal from the oscillator 1 in accordance with the frequency dividing information (N, M) from the constant input circuit 7 and multiplies the equivalent resistance 3 by 1 / M. Clock signals φ1 and φ2 obtained by frequency division and clock signals φ3 and φ4 frequency-divided by 1 / N times the equivalent resistance 4 are input. The input signal Ein is connected to the inverting input terminal of the operational amplifier 5 via the equivalent resistor 3, the non-inverting input terminal of the operational amplifier 5 is grounded, and the output terminal Eout is connected to the operational amplifier 5 via the equivalent feedback resistor 4. Connected to inverting input terminal.

Next, the detailed configuration of the equivalent resistors 3 and 4 in FIG. 1 will be described with reference to the drawings. 2 and 3 are detailed circuit diagrams of the equivalent resistors 3 and 4 in FIG. In FIG. 2, M1 and M3 are N-channel MOS transistors, and M2 and M4 are P-channel MOS transistors. Source S of each transistor M1, M2
And the drain (D) are connected, and the sources and drains of the transistors M3 and M4 are connected. These are analog switches composed of P / N complementary MOS transistors generally used in the past. The sources of the transistors M1 and M2 are connected to the input signal (Ein) in FIG.
The drain of M2 is connected to the capacitor C1 and the transistor M
3, M4.

The gates of the transistors M1 and M2 are provided with the divided clock signals φ1 and φ from the frequency dividing circuit 2 in FIG.
2 are respectively input. The sources and drains of the transistors M3 and M4 are respectively connected in parallel to both terminals of the capacitor C1, and the drains of the transistors M3 and M4 connected to one terminal of the capacitor C1 are connected to the operational amplifier in FIG. 5 inverting input terminals. The divided clock signals φ2 and φ1 from the frequency dividing circuit 2 in FIG. 1 are input to the gates of the transistors M3 and M4, respectively.

In FIG. 3, transistors M5, M6,
M7 and M8 and the capacitor C2 are exactly the same as the transistors M1, M2, M3 and M4 and the capacitor C1, respectively, in FIG. M5 and M7 are N-channel MOS transistors, and M6 and M8 are P-channel MOS transistors. Each transistor M
The sources and drains of the transistors M5 and M6 are connected, and the sources and drains of the transistors M7 and M8 are connected.

The sources of the transistors M5 and M6 are connected to the inverting input terminal of the operational amplifier 5 in FIG. 1, and the drains of the transistors M5 and M6 are connected to the capacitor C2 and the sources of the transistors M7 and M8. The divided clock signals φ3 and φ4 from the frequency dividing circuit 2 in FIG. 1 are input to the gates of the transistors M5 and M6, respectively. The sources and drains of the transistors M7 and M8 are respectively connected in parallel to both terminals of the capacitor C2, and the drains of the transistors M7 and M8 connected to one terminal of the capacitor C2 are connected to the operational amplifier in FIG. 5 is connected to the output terminal (Eout). The divided clock signals φ4 and φ3 from the frequency dividing circuit 2 in FIG. 1 are input to the gates of the transistors M7 and M8, respectively.

Next, the basic circuit configuration and operation of the switched capacitor will be described. FIG. 4 is a circuit configuration diagram of a basic switched capacitor. FIG. 5 is a timing chart showing the timing for driving the switched capacitor of FIG. In the circuits of FIGS. 4A and 4B, switches S1 and S2 are analog switches composed of MOS transistors. The switch S1 is turned on while the two-phase clock φ1 is “H (high level)”,
It is turned off during the period of “L (low level)”. Similarly, the switch 2 is turned on during a period when the two-phase clock φ2 is “H” and turned off during a period when the two-phase clock φ2 is “L”. FIG. 4
It is assumed that Vi and Vo in the above are voltage sources.

In FIG. 4A, when S1 is on and S2 is off, the electric charge charged to the capacitor C is Q = 0 [C].
When S2 is turned on and S1 is turned off, the charge stored in the capacitor C is Q = C (Vo-Vi) [C].
As shown in FIG. 5, the falling time of φ1 is nt, φ2
Is defined as (n + 0.5) t, the next falling time of φ1 is defined as (n + 1) t, and T is defined as a clock cycle. From power supply Vi to Vo, Q = C ｛Vo ( n + 0.5) t−Vi (n + 0.5) t｝ [C] (6)

Therefore, the average current in one cycle is I = C {Vo (n + 0.5) t-Vi (n + 0.5) t} / T [A] (7) The frequency cycle is Vi
, Vo sufficiently higher than the maximum spectrum frequency, the circuit shown in FIG. 4A is equivalently represented by the resistance shown in FIG. The equivalent resistance value is as follows: R = T / C [Ω] (8)

In the circuit shown in FIG. 4B, the time (n-0.
5) Q = C {Vo (n-0.5) t}
[C] is stored, the switch S1 is turned on,
When S2 is turned off, the charge of Q = CVi (n) t is charged in the capacitor C. Therefore, by the time nt, Vi
Then, the charge Q = C (Vo (n−0.5) t−Vi (n) t} [C] is transferred to C.

Next, when the switch S2 is turned on and the switch S1 is turned off, a charge of Q = CVo (n + 0.5) t [C] is accumulated in the capacitor C, and the electric charge is changed from C by time (n + 0.5) t. V
The charge transferred to o is as follows: Q = C ｛Vo (n + 0.5) t−Vi (n) t｝ [C] (9) As in FIG. Is sufficiently higher than the spectral maximum frequencies of Vi and Vo, it can be regarded as equivalently a resistance element.

Next, the operation of the circuit of FIG. 1 will be described in detail with reference to the drawings. As described above, the equivalent resistances 3 and 4 shown in FIG. 1 are equivalent resistances constituted by the switched capacitor circuits of FIGS. FIG. 6 is a timing chart of pulses for driving the equivalent resistances 3 and 4. The switched capacitor circuits in FIGS. 2 and 3 have a circuit configuration similar to that of FIG. 4A described in the basic configuration of the switched capacitor circuit, and can be regarded as equivalent resistance.
The equivalent resistance value can be arbitrarily given by the capacitance of the switched capacitor and the driving cycle of the switch. The circuit shown in FIG. 1 has a typical configuration of an inverting amplifier circuit, and the relationship between the input and output of this circuit is expressed by Eout =-(R2 / R1) .Ein (10).

That is, the amplification degree Av is equivalent to the equivalent resistances R1 and R1.
Av = R2 / R1 (11)

The oscillator 1 generates a clock signal having a specific frequency, and inputs the clock signal to the frequency dividing circuit 2. The constant input device 7 is an input device for externally inputting the frequency dividing ratio of the frequency dividing circuit, that is, M and N values (M and N are not limited to integers) to the gain control circuit. The frequency dividing circuit 2 divides the given clock signal according to the M and NK values specified by the constant input device 7. At the same time, the frequency divider 2
Inputs the frequency-divided clock signals φ1 and φ2 to the equivalent resistance 3 and the clock signals φ3 and φ4 to the equivalent resistance 4, respectively.

Assume that the divided clock signals, that is, the timings of φ1, φ2, φ3, and φ4 have the relationship shown in FIG. Specifically, it is assumed that φ1 and φ2 are complementary pulses and the period is T1, and φ3 and φ4 are complementary pulses and the period is T2. The capacitor values of the switched capacitors shown in FIGS. 2 and 3 are denoted by C1 and C2, respectively. At this time, the input / output relationship of the gain control circuit is derived from the equations (8) and (10) as follows: Eout = − {(T2 / C2) / (T1 / C1)} · Ein (12) .

Here, if the capacitor value is set as C1 = C2, then Eout =-(T2 / T1) .Ein (13), and the gain of the gain control circuit drives the equivalent resistors 3 and 4. It is given by the ratio of the clock signal periods of φ1, φ2 and φ3, φ4. Since the clock signal periods of φ1, φ2 and φ3, φ4 are determined by the frequency division information (M, N) given to the frequency dividing circuit 2, the gain of the present gain control circuit is consequently determined by the frequency dividing information M given to the frequency dividing circuit 2. And N.

Now, if the gain is to be doubled in the present gain control circuit, T1 = T2 =
The ratio may be set to 1: 2. Therefore, if the ratio of the dividing information M value to the N value input to the dividing circuit is 1: 2, the gain of the gain control circuit is set to twice.

Next, the effect of the first embodiment of the present invention will be described. In the first embodiment of the present invention, the gain of the gain control circuit is determined by the clock signal cycle ratio (T1: T2) for driving the switched capacitor, that is, the frequency division ratio of the frequency divider circuit. Is better than the case where a conventional resistance element is used. For the same reason, the linearity of gain control is also good. Further, since the resistance element, which is a passive element, is not used in the circuit, the temperature dependence of the gain, which is found in a conventional gain control circuit, is small.

Further, when a conventional gain control circuit using a passive element resistance element is formed in an IC, the area occupied by the circuit is generally large because the area occupied by the resistance element is large. In the present gain control circuit, the circuit occupying the inside of the IC can be reduced because the circuit is not configured using the conventional resistance elements. In addition, in the circuit configuration of the present invention, the load seen from the driving terminal, for example, the output terminal of the operational amplifier, has only one equivalent resistance composed of a switched capacitor and the driving load is small. Therefore,
As seen in the conventional gain control circuit, a phenomenon in which a plurality of switched capacitor circuits are connected to realize gain control and the signal band is significantly reduced can be avoided.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. 7 and 8 are detailed configuration diagrams of the equivalent resistors 3 and 4 in the first embodiment (FIG. 1) of the present invention, and detailed configuration diagrams of the switched capacitor circuit shown in FIG. 4B. But also. As described above, equivalent resistance can be realized by each of the switched capacitor circuit configurations shown in FIGS. 4A and 4B.

In the second embodiment of the present invention, the configuration of the switched capacitor forming the equivalent resistance adopts the configuration of FIG. 4B, and the equivalent resistance 3 in the first embodiment of the present invention is adopted. , 4 are replaced by the detailed configuration of the switched capacitor shown in FIGS. 7 and 8, the same effect as that of the first embodiment of the present invention can be obtained.

In FIG. 7, M11 and M13 are N-channel MOS transistors, and M12 and M14 are P-channel MOS transistors. Each transistor M11,
The source (S) and drain (D) of M12 are connected, and the sources and drains of the transistors M13 and M14 are connected. These are analog switches composed of P / N complementary MOS transistors generally used in the past.

The sources of the transistors M11 and M12 are connected to the input signal (Ein) in FIG.
The drains of M1 and M12 are connected to the capacitor C3 and the sources of the transistors M13 and M14. Transistor M
The divided clock signals φ1 and φ2 from the frequency dividing circuit 2 in FIG. 1 are input to the gates of 11 and M12, respectively. Also,
The sources of the transistors M13 and M14 are
1, the drain of M12 and the capacitor C3, and one terminal of the capacitor C3 is grounded to GND. The drains of the transistors M13 and M14 are the same as those in FIG.
Are connected to the inverting input terminal of the operational amplifier 5. Divided clock signals φ2 and φ1 from the frequency dividing circuit 2 in FIG. 1 are input to the gates of the transistors M13 and M14, respectively.

In FIG. 8, the transistors M15 to M18 and the capacitor C4 are respectively connected to the transistor M11 in FIG.
M14 and the element completely equivalent to the capacitor C3.
M15 and M17 are N-channel MOS transistors,
M16 and M18 are P-channel MOS transistors.
The sources and drains of the transistors M15 and M16 are connected, and the sources and drains of the transistors M17 and M18 are connected.

The sources of the transistors M15 and M16 are connected to the inverting input terminal of the operational amplifier 5 in FIG. 1, and the drains of the transistors M15 and M16 are connected to the capacitor C4 and the sources of the transistors M17 and M18. The divided clock signals φ3 and φ4 from the frequency dividing circuit 2 in FIG. 1 are input to the gates of the transistors M15 and M16, respectively. The sources of the transistors M17 and M18 are connected to the drains of the transistors M15 and M16 and the capacitor C4, and one terminal of the capacitor C4 is grounded. The drains of the transistors M17 and M18 are connected to the output terminal (Eout) of the operational amplifier 5 in FIG. The gates of the transistors M17 and M18 have a divided clock signal φ from the frequency dividing circuit 2 in FIG.
4 and φ3 are input, respectively.

7 and 8, similarly to the first embodiment of the present invention, if the values of the capacitors C3 and C4 are set to be the same, the gain of the gain control circuit becomes equal to that of the frequency dividing circuit 2 in FIG.
And the same effect as in the first embodiment can be obtained.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a configuration diagram of the third embodiment of the present invention. The oscillator 1, the frequency divider 2, the equivalent resistors 3, 4, the operational amplifier 5, and the constant input device 7 in FIG. 9 are the same as those in the configuration diagram of the first embodiment of the present invention shown in FIG. .

The circuit shown in FIG. 9 is a typical non-inverting amplifier using the operational amplifier 5. The input / output relationship of this circuit is expressed as follows: Eout = {(R1 + R2) / R1} .Ein (14)

The degree of amplification in the third embodiment of the present invention is determined by R1 and R2 as in the first embodiment of the present invention. Therefore, the gain of the circuit can be arbitrarily set by changing the amplification ratio by changing the frequency dividing ratio of the frequency dividing circuit 2, that is, the constant of the constant input device 7.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a configuration diagram of the fourth embodiment of the present invention. The oscillator 1, the equivalent resistors 3 and 4, the operational amplifier 5, and the constant input device 7 in FIG. 10 are the same as those in the configuration diagram of the first embodiment of the present invention shown in FIG. The equivalent resistances 8 and 9 are equivalent to the equivalent resistances 3 and 4, and the clock signal for driving the switches of the switched capacitors from the frequency dividing circuit 2 is the equivalent resistance (equivalent resistance) composed of the switched capacitors. Are input to the resistors 3, 4, 8, 9). The circuit shown in FIG. 10 is a typical differential amplifier circuit, and the input / output relation of this circuit is as follows: Eout = {(R1 + R2) / R1} · {R4 / (R3 + R4)} · Ein2 + ｛− (R2 / R1 )｝ · Ein1 (15)

In the fourth embodiment of the present invention, as in the first and third embodiments of the present invention, the equivalent resistances 3, 4,
8, 9, that is, the resistance ratio of R1, R2, R3, and R4 can be arbitrarily set. Therefore, the gain of this circuit can be set arbitrarily.

[0064]

The first effect is that the temperature fluctuation of the circuit gain is small. For this reason, the circuit can operate in a wide temperature range. The reason is that an equivalent resistance by a switched capacitor is used instead of using a resistance element which is a passive element as in the related art.

The second effect is that when the present circuit is configured in an IC, the chip area occupied by the circuit can be reduced. For this reason, it is possible to contribute to the reduction of the IC chip size and the cost of the IC. The reason is,
This is because the gain control circuit is configured using a resistor element of a switched capacitor circuit including a transistor and a capacitor, instead of a resistor element occupying a large area.

The third effect is that the accuracy of the absolute gain is good. The reason is that the gain control is realized by changing the period for driving the switched capacitor, that is, the frequency division ratio of the frequency divider circuit.

The fourth effect is that the linearity of gain control is good. The reason is that the gain control is realized by changing the period for driving the switched capacitor, that is, the frequency division ratio of the frequency divider circuit.

The fifth effect is that in a gain control circuit composed of a switch and a capacitor, a decrease in bandwidth due to the addition of the switch and the capacitor can be minimized. Therefore, the present gain control circuit can be applied to a high-bandwidth application. The reason is that the gain control is performed by changing the cycle of driving the switched capacitor circuit, so that the gain control circuit can be configured with the minimum number of switches and capacitors, and the output load is small.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an equivalent resistance of FIG. 1;

FIG. 3 is a block diagram showing a detailed configuration of an equivalent resistor in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a basic switched capacitor circuit.

FIG. 5 is a timing diagram for driving the switched capacitor of FIG. 4;

FIG. 6 is a timing chart showing timing for driving the equivalent resistance shown in FIG. 1;

FIG. 7 is a detailed circuit diagram showing an equivalent resistance according to the second embodiment of the present invention.

FIG. 8 is a detailed circuit diagram showing an equivalent resistance according to the second embodiment of the present invention.

FIG. 9 is a configuration diagram showing a third embodiment of the present invention.

FIG. 10 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing an example of a conventional gain control circuit.

FIG. 12 is a block diagram showing another example of the conventional gain control circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Oscillator 2 Divider circuit 3, 4, 8, 9 Equivalent resistance comprised of switched capacitors 5 Operational amplifier 7 Constant input device C1-C4 Capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J023 CA01 CB11 5J090 AA01 AA47 CA02 CA21 CA92 CN01 FA20 HA02 HA09 HA25 HA29 HA38 HA39 KA00 KA32 KA35 TA01 TA06 5J100 AA02 AA18 BA07 BB00 BB02 BB08 BB11 CA25 BC25 BC02 EA02

Claims (8)

[Claims] 1. A gain control circuit for determining the gain of an amplifier based on a ratio of resistance values of first and second resistance elements, wherein the first and second resistance elements function as first and second resistance elements, respectively. And a second switch capacitor circuit; clock signal generating means for generating first and second drive clock signals for driving each of the first and second switch capacitor circuits; And a control means for changing and controlling the cycle ratio of the second drive clock signal. 2. The clock signal generating means includes: an oscillator that oscillates a clock signal having a constant cycle; and a frequency divider that divides the clock signal having the fixed cycle to output the first and second drive clocks. 2. The method according to claim 1, wherein
A gain control circuit as described. 3. The control means includes frequency division number setting means for setting first and second frequency division numbers in the frequency divider for generating the first and second drive clocks, respectively. The gain control circuit according to claim 2, wherein: 4. The gain control circuit according to claim 3, wherein said frequency division number setting means is capable of externally inputting constants for setting said first and second frequency division numbers. 5. The gain control circuit according to claim 4, wherein said period ratio is determined by a ratio of two said constants. 6. The gain of the amplifier is determined by the ratio of the resistance values of the first and second resistance elements, wherein the first and second resistance elements use first and second switched capacitor circuits. A gain control method for a gain control circuit that drives the first and second switched capacitor circuits with first and second drive clock signals, respectively,
A gain control method, wherein the gain is determined by a cycle ratio of each drive clock of the first and second switched capacitor circuits. 7. The gain control method according to claim 6, wherein the cycle ratio of the first and second drive clocks is set by an external setting. 8. A clock signal having a fixed period is divided by a frequency divider by first and second frequency division numbers, respectively, to obtain the first and second drive clocks, and the first and second frequency divisions are performed. 8. The gain control method according to claim 7, wherein the ratio of the numbers is set externally.