JPS5941917A - Television receiver - Google Patents

Television receiver

Info

Publication number
JPS5941917A
JPS5941917A JP15215482A JP15215482A JPS5941917A JP S5941917 A JPS5941917 A JP S5941917A JP 15215482 A JP15215482 A JP 15215482A JP 15215482 A JP15215482 A JP 15215482A JP S5941917 A JPS5941917 A JP S5941917A
Authority
JP
Japan
Prior art keywords
channel
circuit
memory
tuning
tuner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15215482A
Other languages
Japanese (ja)
Inventor
Mitsugi Sasaki
佐々木　貢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15215482A priority Critical patent/JPS5941917A/en
Publication of JPS5941917A publication Critical patent/JPS5941917A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
    • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
    • H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
    • H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To correct a frequency shift, by storing preliminarily the frequency shift of the tuner of each channel in a memory and reading out this frequency shift at a channel selection time and applying this value to a varactor diode of the tuner. CONSTITUTION:The tuning deviation of frequency response generated between channels is preliminarily stored in a memory circuit 9 for every channel. When a channel is designated by a channel selection panel 8, the desired channel is selected by a channel selecting circuit 7. At this time, stored contents for the channel in the circuit are selected and are applied to varactor diodes 11 and 12. Thus, the tuning deviation is corrected.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は各チャンネル間の周波数応答特性を補正したテ
レビジョン受像機に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a television receiver in which frequency response characteristics between channels are corrected.

従来例の構成とその問題点 従来、テレビジョン受像機の選局は、チューナの同調回
路に可変容量ダイオードを設け、この可変容量ダイオー
ドに各チャンネル毎に異なる選局電圧を印加して希望す
るチャンネルを受信しているＯ しかし、チー−すの高周波増幅器のチューニングのずれ
がチャンネルによって異なり、また局部発振器の発振出
力の振幅が各チャンネルによって異なることによりミキ
サーの出力のチューニングにずれが生じる欠点がある。Conventional configuration and its problems Traditionally, television receivers have been tuned by installing a variable capacitance diode in the tuning circuit of the tuner, and applying a different tuning voltage to each channel to the variable capacitance diode to select the desired channel. However, there is a drawback that the tuning deviation of the high-frequency amplifier of the CH's varies depending on the channel, and the amplitude of the oscillation output of the local oscillator differs depending on each channel, resulting in deviations in the tuning of the mixer output. .

特に１〜３チヤンネルのＶＨＦのローバンド、４〜１２
チヤンネルのＶＨＦのハイバンドおよび１３〜６２チヤ
ンネルのＵＨＦバンドのようにバンド間の差が大きく、
壕だ同一バンド内でも差がある。Especially VHF low band of channels 1 to 3, 4 to 12
There are large differences between bands, such as the VHF high band of channels and the UHF band of channels 13 to 62,
There are differences even within the same band.

発明の目的 本発明は上記のチューニングずれが起らないようにしよ
うとするものである。OBJECT OF THE INVENTION The present invention attempts to prevent the above-mentioned tuning deviation from occurring.

発明の構成 本発明はあらかじめ各チャンネルのチューナにおける周
波数ずれをメモリに記憶させ、チャンネル選局時にこの
メモリよりそのチャンネルの周波数ずれを読み出し、チ
ューナの可変容量ダイオードＶこ加えて周波数ずれを補
正することを特徴とするテレビジョン受像機である。Structure of the Invention The present invention stores the frequency deviation in the tuner of each channel in advance in a memory, reads out the frequency deviation of that channel from this memory when selecting a channel, and corrects the frequency deviation by adding it to the variable capacitance diode V of the tuner. This is a television receiver featuring:

実施例の説明 第１図おいて１は単同調形結合回路、２は高周波増幅器
、３は複同調回路、４はミキサー、６・・・第１局部発
振器、６はＩＦ回路、７はＰＬＬ選局回路、８は選局パ
ネル、９はメモリ回路、１ｏはＤ／Ａ変換回路、１１．
１２は可変容量ダイオードである。Description of the Embodiment In Fig. 1, 1 is a single-tuned coupling circuit, 2 is a high-frequency amplifier, 3 is a double-tuned circuit, 4 is a mixer, 6... a first local oscillator, 6 is an IF circuit, and 7 is a PLL selection circuit. A station circuit, 8 a channel selection panel, 9 a memory circuit, 1o a D/A conversion circuit, 11.
12 is a variable capacitance diode.

あらかじめ各チャンネル間に生じる周波数レスポンスの
チューニングずれをメモリ回路９に各チャンネル毎に記
憶させておき、選局パネル８によってチャンネルを指定
すると選局回路７によってそのチャンネルが選ばれる。Tuning deviations in frequency responses that occur between channels are stored in memory circuit 9 in advance for each channel, and when a channel is specified using channel selection panel 8, that channel is selected by channel selection circuit 7.

このとき、メモリ回路９もそのチャンネルのメモリ量が
選択され、Ｄ／Ａ　変換回路でアナログ信号に変換され
、可変容量ダイオード１１．１２に加えられる。これに
よってチューニングのずれを補正する。At this time, the memory amount of the channel of the memory circuit 9 is also selected, converted into an analog signal by the D/A conversion circuit, and added to the variable capacitance diodes 11 and 12. This corrects the tuning deviation.

なお、可変容量ダイオード１１．１２はどちらか一方だ
けでも補正可能である０すなわち、最終結果が良好にな
るようにメモリ回路９に各チャンネル毎の補正量をディ
ジタル的に記憶させればよいＯ 発明の効果 以上のように本発明によれば各チャンネル毎にチューニ
ングのずれの補正量を記憶させ、これを選局時にチー−
すの可変容量ダイオードに加えるようにしているので、
各チャンネル毎に正確なチューニング状態を得ることが
できるものである０Note that it is possible to correct only one of the variable capacitance diodes 11 and 12. In other words, it is only necessary to digitally store the correction amount for each channel in the memory circuit 9 so that the final result is good. As described above, according to the present invention, the amount of correction for tuning deviation is stored for each channel, and this is used when selecting a channel.
Since it is added to the variable capacitance diode of
0, which allows accurate tuning status to be obtained for each channel.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例におけるテレビジョン受像機のブ
ロック線図である０ １・・・・・・単同調形結合回路、２・・・・・・高周
波増幅器、３・・・・・・複同調回路、４・・・・・・
ミキサー、６・・・・・・第１局部発振器、６・・・・
・・ＩＦ回路、７・・・・・・ＰＬＬ選局回路、８・・
・・・・選局パネル、９・・・・・・メモリ回路、１０
・・・・・・Ｄ／Ａ変換回路、１１．１２・・・・・・
可変容量ダイオード〇The figure is a block diagram of a television receiver in an embodiment of the present invention. 0 1...Single tuning type coupling circuit, 2...High frequency amplifier, 3... Double tuned circuit, 4...
Mixer, 6...First local oscillator, 6...
...IF circuit, 7...PLL tuning circuit, 8...
...Tuning panel, 9...Memory circuit, 10
......D/A conversion circuit, 11.12...
Variable capacitance diode〇

Claims (1)

【特許請求の範囲】[Claims] あらかじめ各チャンネルのチューナにおける周波数ずれ
をメモリに記憶させ、チャンネル選局時にこのメモリよ
り、そのチャンネルの周波数ずれを読み出し、チューナ
の可変容量ダイオードに加えて周波数ずれを補正するこ
とを特徴とするテレビジョン受像機。A television characterized in that the frequency deviation in the tuner of each channel is stored in a memory in advance, and when selecting a channel, the frequency deviation of that channel is read out from this memory, and the frequency deviation is corrected in addition to the variable capacitance diode of the tuner. receiver.
JP15215482A 1982-08-31 1982-08-31 Television receiver Pending JPS5941917A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15215482A JPS5941917A (en) 1982-08-31 1982-08-31 Television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15215482A JPS5941917A (en) 1982-08-31 1982-08-31 Television receiver

Publications (1)

Publication Number Publication Date
JPS5941917A true JPS5941917A (en) 1984-03-08

Family

ID=15534200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15215482A Pending JPS5941917A (en) 1982-08-31 1982-08-31 Television receiver

Country Status (1)

Country Link
JP (1) JPS5941917A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137003A (en) * 1974-04-17 1975-10-30

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137003A (en) * 1974-04-17 1975-10-30

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