JPS5941862A - Electronic circuit module - Google Patents

Electronic circuit module

Info

Publication number
JPS5941862A
JPS5941862A JP57150773A JP15077382A JPS5941862A JP S5941862 A JPS5941862 A JP S5941862A JP 57150773 A JP57150773 A JP 57150773A JP 15077382 A JP15077382 A JP 15077382A JP S5941862 A JPS5941862 A JP S5941862A
Authority
JP
Japan
Prior art keywords
monitoring
terminals
semiconductor chip
chip
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57150773A
Other languages
Japanese (ja)
Inventor
Shigemi Mio
美尾　恵己
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57150773A priority Critical patent/JPS5941862A/en
Publication of JPS5941862A publication Critical patent/JPS5941862A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Abstract

PURPOSE:To detect the risk of the breakdown of terminal connecting parts when the breaking possibility is present, by providing monitoring wirings in a multilayered substrate and in a semiconductor chip so that the parts between monitoring connecting parts are connected and one circuit is constituted. CONSTITUTION:Each monitoring part 3 is connected by an intrachip wiring 4 which is provided along each side of a semiconductor chip 1. Meanwhile, a multilayered ceramic substrate 5 has terminals at the positions corresponding to ordinary terminals 2 and the monitoring terminals 3. The parts between the monitoring terminals 3 and the part between the monitoring terminal 3 and a monitoring terminal 6 at the outside of the chip are connected by wirings 7 in the multilayered ceramic substrate 5. When a current is conducted through an electronic circuit module, the semiconductor chip 1 is heated and thermal expansion occurs. Conversely, when a power source is turned OFF, the temperature is decreased and the chip is contracted. Thus shearing stress is repeatedly applied to soldered connecting parts. When the power source is turned ON and OFF for more than certain number of times, thermal fatigue breakdown occurs. The first breakdown occurs at the monitoring terminals 3, which are located at the out side where the shearing stress is the largest. Therefore, opening of the monitoring terminal 6 of the electronic circuit module occurs before the ordinary terminals 2 are broken.

Description

【発明の詳細な説明】 発明の対象 本発明は、フリップチップ形半導体チップを、たとえば
多層セラミック基板などの多層基板上に搭載する電子回
路モジュールに係り、特にチ。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to an electronic circuit module in which a flip-chip type semiconductor chip is mounted on a multilayer substrate such as a multilayer ceramic substrate.

ツブ接続信頼性の改善に好適な半導体チップ及び多層基
板の構造に関するものである。The present invention relates to a structure of a semiconductor chip and a multilayer substrate suitable for improving the reliability of joint connections.

従来技術 フリップチップ形の半導体チップと多層セラミック基板
との接続は、チップ側端子と多層セラミック側端子間を
ハンダで接着することにより行っている。このため半導
体チップが発熱すると半導体チップと多層セラミック基
板の熱膨張率の差に起因する熱応力がハンダ接続部にく
り返し加わり、ハンダが疲労破断するという問題がある
。BACKGROUND OF THE INVENTION Connection between a flip-chip type semiconductor chip and a multilayer ceramic substrate is achieved by bonding the terminals on the chip side and the terminals on the multilayer ceramic side using solder. For this reason, when the semiconductor chip generates heat, thermal stress caused by the difference in coefficient of thermal expansion between the semiconductor chip and the multilayer ceramic substrate is repeatedly applied to the solder joint, causing a problem of fatigue rupture of the solder.

ところでハンダの熱疲労寿命は、チップと多層セラミッ
ク基板との接続部にがかるせん断心力の２乗に反比例す
るので、最も外側にある端子が最も太きなせん断心力を
受けるので、従って破断寿命が短いことになる。そこで
チップ側端子をできるだけチップの中央部に寄せるとい
うことが行われている。By the way, the thermal fatigue life of solder is inversely proportional to the square of the shear core force applied to the connection between the chip and the multilayer ceramic board, so the outermost terminal receives the greatest shear core force, so its life at break is short. It turns out. Therefore, the chip-side terminals are moved as close to the center of the chip as possible.

また一方加速寿命試験等を行って事前にハンダの耐用寿
命を予測し、このデータによって上記問題に対し対策し
ていた。しかしチップが大形化し、入出力端子数が増大
するに伴い、前記熱応力が大きくなるので、耐用寿命が
短くなる傾向がある。そこで個々のチップについて、よ
り正確に耐用寿命を知り、ハンダ接続部の疲労破断の危
険を防止するという必要が生じている。On the other hand, accelerated life tests and the like were conducted to predict the service life of solder in advance, and countermeasures were taken against the above problems using this data. However, as the size of the chip increases and the number of input/output terminals increases, the thermal stress increases, which tends to shorten the service life. Therefore, there is a need to more accurately know the service life of individual chips and to prevent the risk of fatigue failure of solder joints.

発明の目的 本発明の目的は、半導体チップと多層基板間の端子接続
部の状態について常時監視を行い。OBJECTS OF THE INVENTION An object of the present invention is to constantly monitor the state of terminal connections between a semiconductor chip and a multilayer board.

破断の危険があるときこれを検知できる電子回路モジュ
ールの提供にある。The purpose of the present invention is to provide an electronic circuit module that can detect when there is a risk of breakage.

本発明は、フリップチップ形半導体チップと多層基板と
の間の通常の接続部の外１１＋１１に複数個の監視用接
続部を設け、該監視用接続部間を接続し１つの回路が構
成されるように多層基板内および半導体チップ内に監視
用の配線を設けた電子回路モジュールを特徴とする。In the present invention, a plurality of monitoring connection parts are provided at 11+11 in addition to the normal connection parts between a flip-chip type semiconductor chip and a multilayer board, and one circuit is configured by connecting the monitoring connection parts. The electronic circuit module is characterized by having monitoring wiring provided inside the multilayer substrate and inside the semiconductor chip.

発明の実施例 以下本発明の一実施例を第１図及び第２図により説明す
る。Embodiment of the Invention An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

第１図は、多層セラミック基板５およびその上に実装さ
れた半導体チップ１から成る電子回路モジ−一ルな示す
平面図である。半導体チップ１は、その内側に電源及び
信号入出力用の一般端子２をもち、外側にハンダ接続寿
命監視のための監視用端子６が設けられており、各監視
用端子６は半導体チップ１の斜辺に沿って配設されてい
るチップ内の配線４で接続されている。FIG. 1 is a plan view showing an electronic circuit module comprising a multilayer ceramic substrate 5 and a semiconductor chip 1 mounted thereon. The semiconductor chip 1 has general terminals 2 for power supply and signal input/output on the inside, and monitoring terminals 6 for monitoring the solder connection life on the outside. They are connected by wiring 4 inside the chip, which is arranged along the oblique side.

一方多層セラミック基板５も、上記−膜端子２および監
視用端子３と対応する位置に端子を有し、監視用端子３
問および監視用端子３とチップ外部の監視用端子６間は
、多層セラミック基板５内の配線７により接続されてい
る。なお第２図は、第１図の電子回路モジュールを図の
Ａ−Ａ′で切断した断面図である。On the other hand, the multilayer ceramic substrate 5 also has terminals at positions corresponding to the -membrane terminals 2 and the monitoring terminals 3.
The contact and monitoring terminals 3 and the monitoring terminals 6 outside the chip are connected by wiring 7 within the multilayer ceramic substrate 5. Note that FIG. 2 is a cross-sectional view of the electronic circuit module of FIG. 1 taken along line AA' in the figure.

このような構造をもつ電子回路モジュールに通電すると
、半導体チップ１が発熱して熱膨張し、逆に電源断とす
ると、温度下降するため収縮し、せん断芯力が繰り返し
ハンダ接続部に加わる。このため、ある回数以上電源を
断続させると、ハンダの熱疲労破断を起すが、最初に破
断するのは一番せん断芯力の大きい外側の監視用端子３
であるので、−膜端子２が破断する前に電子回路モジュ
ールの監視用端子６の開放が発生し、この半導体チップ
１のハンダ熱疲労寿命を検知できるので、電子回路モジ
ュールを交換することにより、障害の発生を未然に防ぐ
ことができる。When an electronic circuit module having such a structure is energized, the semiconductor chip 1 generates heat and expands thermally. Conversely, when the power is turned off, the semiconductor chip 1 contracts due to a drop in temperature, and shear core force is repeatedly applied to the solder joints. Therefore, if the power is turned on and off more than a certain number of times, the solder will break due to thermal fatigue, but the one that breaks first is the outer monitoring terminal 3, which has the largest shear core force.
Therefore, the monitoring terminal 6 of the electronic circuit module opens before the membrane terminal 2 breaks, and the solder thermal fatigue life of the semiconductor chip 1 can be detected, so by replacing the electronic circuit module, It is possible to prevent failures from occurring.

発明の効果 本発明によれば、実稼動中にフリップチップ形チップと
多層基板間の接続寿命を検知できるので、障害の発生を
未然に防ぐ効果がある。Effects of the Invention According to the present invention, the lifespan of the connection between the flip-chip chip and the multilayer board can be detected during actual operation, which is effective in preventing the occurrence of failures.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例である電子回路モジュールの
平面図、第２図は第１図のＡ−Ａ’線断面図である。 符号の説明 １・・・・・・半導体チップ ３・・・・・・監視用端子 ４・・・・・・配線 ５・・・・・・多層セラミック基板 ６・・・・・・監視用端子 ７・・・・・・配線 １＝１　　図FIG. 1 is a plan view of an electronic circuit module according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA' in FIG. Explanation of symbols 1...Semiconductor chip 3...Monitoring terminal 4...Wiring 5...Multilayer ceramic substrate 6...Monitoring terminal 7...Wiring 1=1 Diagram

Claims (1)

【特許請求の範囲】[Claims] フリップチップ形半導体チップが多層基板上に低融点金
属により接続および搭載される電子回路モジュールにお
いて、前記半導体チップの前記通常の接続部の外側に設
けられた複数個の監視用接続部と、該監視用接続部間を
接続し１つの回路が構成されるように該基板内および該
半導体チップ内に設けられた監視用の配線とを有するこ
とを特徴とする電子回路モジュール。In an electronic circuit module in which a flip-chip type semiconductor chip is connected and mounted on a multilayer substrate using a low-melting point metal, a plurality of monitoring connection parts provided outside the normal connection part of the semiconductor chip; 1. An electronic circuit module comprising monitoring wiring provided within the substrate and within the semiconductor chip so as to connect the connecting portions to form one circuit.
JP57150773A 1982-09-01 1982-09-01 Electronic circuit module Pending JPS5941862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57150773A JPS5941862A (en) 1982-09-01 1982-09-01 Electronic circuit module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57150773A JPS5941862A (en) 1982-09-01 1982-09-01 Electronic circuit module

Publications (1)

Publication Number Publication Date
JPS5941862A true JPS5941862A (en) 1984-03-08

Family

ID=15504101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57150773A Pending JPS5941862A (en) 1982-09-01 1982-09-01 Electronic circuit module

Country Status (1)

Country Link
JP (1) JPS5941862A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2445036A1 (en) 2010-09-03 2012-04-25 Sanyo Electric Co., Ltd. Terminal for sealed battery and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2445036A1 (en) 2010-09-03 2012-04-25 Sanyo Electric Co., Ltd. Terminal for sealed battery and manufacturing method therefor

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