JPS5941598B2 - Section DPCM audio demodulator - Google Patents

Description

Detailed Description of the Invention The present invention is filed in Japanese Patent Application No. 51/1215 filed by the same applicant.
This invention relates to a device that demodulates audio codes compressed and recorded in advance on a magnetic disk or the like in real time using the interval DPCM method of No. 53.

In the interval DPCM method, as shown in Figure 1, an audio signal is divided into intervals of a certain time, and a constant coefficient [scale factor: γ] is applied to each interval [section number:] to the extent that the audio signal does not overscale. Perform predictive encoding after multiplying by
Alternatively, when restoring the original voice, the decoding process is performed and then the decoding process is performed and then divided by the constant coefficient γ determined for each section.

Furthermore, in the interval DPCM method, when nonlinearly quantizing the prediction error signal, the optimum quantization characteristic is selected and adapted according to the effective value of the prediction error signal in each interval. For example, after an audio signal is 12-bit PCM encoded, it is divided into approximately 25 ms intervals, multiplied by a scale factor γ for each divided interval, and then subjected to two-stage predictive encoding (predicting the current value from two past samples, predicting the When quantizing errors and encoding them, if three types of nonlinear quantization characteristics (15 steps) are selected and adapted according to the effective value of the prediction error signal in each divided interval, 12 It is possible to compress information into 4-bit information, and to obtain reproduction quality equivalent to or higher than that of 8-bit PCM.

According to the literature (Arai, "Evaluation of Sectional DPCM Audio Coding System," Acoustical Society of Japan Proceedings 3-2-5, October 1972), the dynamic range is equivalent to 12-bit PCM, and the S/Nd is 8-bit. Equivalent to PCM, frequency characteristics are PC
This is equivalent to the M method. Therefore, if audio signals are compressed and recorded on a magnetic disk or the like using the section DPCM method, and then demodulated and played back as necessary, expensive storage devices can be used efficiently and inexpensive automatic broadcasting equipment can be used. Realization becomes possible.

The present invention relates to a real-time demodulation device necessary for realizing such an automatic broadcasting device. The work of compressing and storing audio information on a magnetic disk is accomplished in advance using software.

The compression process is performed, for example, according to the flow shown in FIG.
FIG. 2 will be described in detail below. 1 (1) First, the original speech is 12-bit PCM encoded (10 KHz sampling) in units of clauses, phrases, or sentences and stored in a buffer area.

(2) Divide the discrete audio signal stored in the buffer into a fixed time length (every 249 samples), and divide it into S
Let it be ri.

However, r is the section number (r-011, 2,...
・・・・・・・・・), i is the sample number within each interval (
1-0, 1, 2, 24
8). (3) Set the initial value clear flag CL to ``''1
``17C set.

This means that during demodulation processing, the initial value is set to 7'O for the first section only.
(4) Determine the scale factor γr (r is the section number) from the following equation. However, FS is the full scale level.

Here, the scale factor γ1 is set to simplify the configuration of the demodulator, and the value of the exponent k of the scale factor is limited to five types, 0, 1, 2, 3, and 4.

Also, in equation (2), S(r-1)247, S(r-
1) 248 is the absolute value of the last two samples of the previous section, but in r-0, that is, the first section, both are treated as 7''O''.

This corresponds to processing only the first section (CL-1) with the initial value set to "O" during demodulation processing. In other sections (CL=O), the last two samples of the previous section are the initial values, so γ1 is determined to such an extent that it does not scale over including these samples. (5) Determine prediction coefficients αr1 and αR2 from the following equations. Here, ρr1 and ρR2 are signal sequences {
The autocorrelation coefficient of Sri} is derived from the following equation. (6
) To determine the quantization function, estimate the effective value σRe of the prediction error signal.

The prediction error signal Eri is the difference between the true value γr−Sri and the predicted value including Ri, and is expressed as follows. Further, 'Jri is expressed by the following equation from the prediction coefficients αrl and αR2.
(6) The effective value σRe is calculated using the following equation.

(7) Select a quantization function Qp from σRe.

The quantization function Qp is determined in advance by three types Q using the method shown on pages 6 and 7 of the specification of Japanese Patent Application No. 121553. ,Q. ．． Q2 is prepared and the quantization function selection number p is determined as follows. here. e is the effective value of the prediction error signal over the entire interval.

(8) Using Qp selected as above, Eri
is quantized to obtain a representative value Eri*.

(9) Encode Eri* into 4 bits to obtain Dri.
QOI extraction parameters, namely CL-. k・αrl−
“R2, p and the code sequence {Dri} are arranged in a certain format (for example, in Figure 3). In Figure 3, the parameters and 2
49 compressed audio codes D. ~ D248 in 64 words (
One word is packed into 16 bits. Furthermore, 8 sections of compressed data, 512 words, are collectively filed on a magnetic disk. Circle Repeat this process for all divided sections. The compressed audio code D is pre-filed as described above.

When demodulating .about.D248, the 4-bit code Dri per sample is first decoded to obtain a quantized prediction error signal Eri*. Next, the original sound Sri is demodulated using the demodulation calculation formula derived from equations (6) and (7).

Since Eri* includes a quantization error, the result is S
Although ri also contains errors, it is possible to reproduce a signal with an extremely high degree of approximation. Si-1* and Si-2* are demodulated sample values including a scale factor. When calculating formula (9), the initial value is "o" in the first interval (CL=1).
(Sr(I4)=Sr(i-2)*-0), and in other sections (CL=0), the last two samples of the previous section are used as initial values for calculation. Normal minicomputers and microcomputers have slow processing speeds, making it impossible to perform the above demodulation calculations in real time.

The present invention provides an audio demodulation device that uses a high-speed multiplication LSI and a logic array control system to enable real-time demodulation calculations that were previously impossible.

An embodiment of the present invention will be described below based on the drawings.

FIG. 4 is a block diagram of a demodulator according to the present invention. BMI
, BM is a buffer memory that stores compressed data for continuous and seamless demodulation of audio signals. While the compressed data in the buffer memory BMI is being demodulated, the subsequent compressed data is transferred from the magnetic disk to the buffer memory BM, and when the demodulation of the buffer memory BMI is completed, switching is made to demodulate the compressed data in the buffer memory BM. During this time, the subsequent compressed data is transferred to the buffer memory BMI. Such operations are repeated to continuously reproduce the audio signal. Address designation when writing to the buffer memories BMI and BM is performed by the disk control section (FIG. 5), and address designation when reading is performed by the buffer memory address counter AC. The address switching devices ASWI, ASW are for switching between the two address buses. Bus switching device B
The SW is used to alternately connect the data buses of the buffer memories BMI and BM to the data bus of the disk controller or the data bus of the demodulator. MPX is a multiplexer that selects one of the four audio codes read from the buffer memory BMI or BM (four audio codes are read out at the same time since each word has a 16-bit configuration). PREG is a 2-bit register that stores a quantization function selection number p. DEC is a decoder that converts the audio code into a prediction error signal Eri*, and is composed of a read-only memory. The decoder DEC uses the contents of the register PREG as the upper address and the output of the multiplexer MPX as the lower address, and uses the prediction error signal E.
ri* is output to the B bus. KREG is a 3-bit exponent register that stores the exponent k of the scale factor. SFTC is a shift controller.
In accordance with a control signal output from timing generator TG, the contents of shift register SFRG are shifted to the right or left by a number of bits equal to the contents of exponent register KREG. SIM is Sr(I4
), Sr(i-2)* is a demodulation sample memory that temporarily stores past demodulation sample values corresponding to Sr(i-2)*, and when the CL flag set in the buffer memory is "1", the contents of this demodulation sample memory SIM are cleared. It's summery.
XREG is the multiplicand register, demodulation sample memory SI
Sr(i-,)* or Sr(i-2) read from M
Set *. YREG is a multiplier register that sets the prediction coefficient "Rlj or αR2" read from the buffer memory. MPY is a 12-bit multiplier (execution time: 150
ns), the past demodulated sample value is multiplied by the prediction coefficient. MSPR and LSPR are the upper register and lower register of the multiplication result. ADDER is a 12-bit adder,
Accumulating the multiplication results and adding the prediction error signal. AREG is an accumulator register that temporarily stores the addition progress in equation (9), and the current demodulated sample value indicating the final result is also stored in this accumulator register AR.
I will remain in EG. The shift register SFRG is for shifting the demodulated sample value which is the contents of the demodulated sample memory SIM and the accumulator register AREG, and by the shifting operation, the demodulated sample value is multiplied and divided by the scale factor of the relevant section. will be done. I
The ROM is a macro instruction memory that indicates the demodulation processing procedure, and is composed of an instruction ROM consisting of a logic array. The macro instruction consists of 24 bits, and each bit is assigned to take charge of the control shown in the instruction ROM bit assignment table shown in Table 1. In the present invention, the demodulation process is performed using a macro instruction created from a combination of these 24 bits according to the processing procedure shown in the macro instruction table shown in Table 2. The timing generator TG outputs specific control signals (read pulses, write pulses, etc.) according to macro instructions. The buffer memory access time is 200 ns, the multiplication execution time is 150 ns, and the addition execution time is 20 ns. Other memory and register access times are 50n
Even the shift control, which takes the longest time, completes the process in less than 1 μs.

Therefore, by incrementing the address counter ROMAC of the macro instruction memory IROM every 1 μs, the processing in Table 2 proceeds sequentially, and demodulation of one sample is completed in about 20 μs. In the embodiment, since the sampling frequency is 10 KHz (100 μs), multiplex processing of up to 5 channels is possible. Next, control of shift register SFRG will be described in detail.

In the interval DPCM method, after each divided interval is multiplied by a scale factor γ1, predictive encoding or decoding is performed for each interval. Therefore, adjacent sections usually have different scale factors γ1, and the demodulated signal becomes discontinuous at the joint between the sections. In order to eliminate such problems, the present invention controls the shift register SFRG as follows. (1) Shift register SFR
Clear G.

(2) Write the contents of shift register SFRG to demodulation sample memory SIM only in the first section (clear SIM, that is, initial value (3) From memory SIM to Sr(1
-1) Read * into shift register SFRG and shift it to the left by the number of bits equal to the contents of register KREG (multiply the initial value by the scale factor γ of the section).

Store the result in demodulation sample memory SIM. (4) Shift register SFR from memory SIM to Sr(卜,)*
The data is read out to G and the same processing is performed.
After performing the above processing, the demodulation calculation for the relevant section is performed, and 249 demodulated sample values are obtained from the shift register SFRG and output to the DAC, which is the complete opposite of (3) and (4) above. The operation (shift to the right) is performed so that the scale factor γ1 of the last two samples becomes 717. In the next section, the above processes (3) and (4) are performed again, and then demodulation calculation is performed. By performing such operations, a continuous demodulated signal is finally obtained. As described above, in the present invention, since control is performed using a 24-bit macro instruction using a logic array, processing speed can be increased, and real-time multiple processing can be realized.

Furthermore, since the initial value scale factor is controlled using a shift register, a continuous demodulated signal can be obtained. Furthermore, the instruction RO
There is an advantage that the multiplicity can be changed simply by modifying the contents of M (logic array). Adjustments and tests can be easily handled by simply changing the instruction ROM. Furthermore, because of the logic array control, the configuration is much simpler than the random logic method, and reliability is improved, and manufacturing and adjustment processes are significantly shortened.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing how an audio signal is divided and scaled in the interval DPCM method, Fig. 2 is a flow chart of compression processing, Fig. 3 is an arrangement diagram of compressed data, and Fig. 4 is an embodiment of the present invention. FIG. 5 is a diagram showing a configuration example of an automatic broadcasting system using the demodulation device according to the present invention. BMI, BM...Buffer memory, DEC...
...decoder, KREG ... power register, SFTC ... shift controller, SFR
G: Shift register, SIM: Demodulation sample memory, MPY: Multiplier, ADD
ER: Adder, AREG: Accumulator register, IROM: Macro instruction memory.

Claims (1)

[Claims] 1. Compressing an audio signal using a section DPCM method,
The extracted parameters and audio codes are stored in advance in a magnetic disk device, etc., and a nonlinear quantization function is selected as needed to demodulate and reproduce the original audio signal from compressed data consisting of the extracted parameters and audio codes. A decoder that derives a quantized prediction error signal from the number and audio code, a demodulation sample memory that stores past demodulated sample values, a multiplier that multiplies the past demodulated sample value by a prediction coefficient, and a multiplier that stores the multiplication result. an adder that accumulates and adds the prediction error signal; an accumulator register that temporarily stores the addition result; an accumulator register that temporarily stores the addition result; a shift register that shifts the demodulated sample value; A number register for temporarily storing an exponent of a scale factor, and a shift controller for controlling the shift register to shift the shift register to the right or left by a number of bits equal to the contents of the exponent register, and a macro instruction indicating a processing procedure. A section DPCM audio demodulation device characterized in that demodulation processing is controlled by a logic array formed. 2 For each section, the demodulation calculation is started after multiplying the contents of the demodulation sample memory by the scale factor, and after the completion of the demodulation calculation for the section, the demodulation processing is controlled by dividing the contents of the demodulation sample memory by the scale factor. The section DPCM audio demodulation device according to claim 1, characterized in that: