JPS5941343B2 - Binary code DC feedback method - Google Patents
Binary code DC feedback methodInfo
- Publication number
- JPS5941343B2 JPS5941343B2 JP55019992A JP1999280A JPS5941343B2 JP S5941343 B2 JPS5941343 B2 JP S5941343B2 JP 55019992 A JP55019992 A JP 55019992A JP 1999280 A JP1999280 A JP 1999280A JP S5941343 B2 JPS5941343 B2 JP S5941343B2
- Authority
- JP
- Japan
- Prior art keywords
- binary code
- level
- detection circuit
- feedback method
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/065—Binary decisions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】
本発明は光信号の如く、基準値に対し片側のみに信号が
存在する如き二値符号の受信側における復号に必要な直
流補償を行なう二値符号直流帰還方式に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binary code DC feedback system that performs DC compensation necessary for decoding on the receiving side of binary codes such as optical signals where a signal exists only on one side with respect to a reference value. It is.
更に説明を加えると二値符号(1、oレベル)伝送にお
いて、二値符号を判定するため、1、0レベルの平均値
が常に1、0レベルの中心にあるようにして二値符号の
判定を確実に行なわせる方式である。To explain further, in binary code (1, o level) transmission, in order to judge the binary code, the average value of the 1, 0 level is always at the center of the 1, 0 level, and the binary code is judged. This is a method that ensures that this is done.
従来方式では、二値符号を長時間にわたつて積分し、そ
の平均値をもつて直流レベルとしていた。In the conventional method, the binary code is integrated over a long period of time, and the average value is taken as the DC level.
この場合、二値符号自体が均等な1、oレベルの発生確
率を持つように符号化されることが必要であつた。しか
し、二値符号のマーク率は必ずしも50%を維持される
ものでなく、1、1、1 ・・・・・・・・・とかo、
o、o・・・・・・・・・の二値符号が伝送される場合
が多い。このような場合、特に二値符号のマーク率が5
0%になるような符号化処理が行われていた。本発明は
上記の難点を解決するために主としてAGCとピーク検
波回路より構成した回路で二値符号のマーク率の発生確
率に関係なく二値符号の判定が行なえる二値符号直流帰
還方式を提供するものである。In this case, it was necessary that the binary code itself be encoded so that it has an equal probability of occurrence at the 1 and o levels. However, the mark rate of the binary code is not necessarily maintained at 50%, and is 1, 1, 1, etc.
In many cases, binary codes such as o, o, etc. are transmitted. In such a case, especially if the mark rate of the binary code is 5
Encoding processing was performed so that the value became 0%. In order to solve the above-mentioned difficulties, the present invention provides a binary code direct current feedback system that can judge binary codes regardless of the probability of occurrence of the mark rate of the binary code using a circuit mainly composed of an AGC and a peak detection circuit. It is something to do.
本発明を光伝送の場合を例にして図で説明する。The present invention will be explained using diagrams taking an example of optical transmission.
第1図は本発明の概要を説明するためのものである。1
は発光ダイオード、2はホトダイオード(受光素子)、
3は電源、4は電流電圧変換、5はAGC、6はAGC
のV+出力端子、TはAGCのV−出力端子、8はピー
ク検波回路、9はピーク検波回路のフィードバック出力
を示す。FIG. 1 is for explaining the outline of the present invention. 1
is a light emitting diode, 2 is a photodiode (light receiving element),
3 is power supply, 4 is current voltage conversion, 5 is AGC, 6 is AGC
T is the V+ output terminal of the AGC, 8 is the peak detection circuit, and 9 is the feedback output of the peak detection circuit.
第2図は本発明の基本を説明するための図で二値符号の
同極性(V+)、逆極性(V−)の中心レベルのずれ△
Vをゼロにするための概念図である。Figure 2 is a diagram for explaining the basics of the present invention, and shows the difference in the center level of the same polarity (V+) and opposite polarity (V-) of the binary code.
It is a conceptual diagram for making V zero.
ここでV+は1レベルのとき1で0レベルのとき0を示
し、V−は1レベルのときOで、0レベルのとき1を示
す。第3図は本発明のピーク検波回路の一実施例を示す
。Here, V+ indicates 1 when the level is 1 and indicates 0 when the level is 0, and V- indicates O when the level is 1 and indicates 1 when the level is 0. FIG. 3 shows an embodiment of the peak detection circuit of the present invention.
11はV−の入力端子、12はV+の入力端子、T,l
,T,2,T,4,T,5はトランジスタ、T,3は定
電流源のトランジスタ、A,Bは電位を示す点、Cはコ
ンデンサ、Rl,R2は抵抗、βはT,5の電流増幅率
、+Vは電源を示す。11 is a V- input terminal, 12 is a V+ input terminal, T, l
, T,2, T,4, T,5 are transistors, T,3 is a constant current source transistor, A, B are points indicating potential, C is a capacitor, Rl, R2 are resistors, β is a transistor of T,5. Current amplification factor, +V indicates power supply.
第1図において、発光ダイオードの光信号1,0がホト
ダイオード(光受光素子)2に受光され、光一電気変換
出力が電流電圧変換回路4に入力され、その出力がAG
C5に入力され、その出力端子6,7より第2図に示す
如きV−1+が出力されピーク検出回路8に人力される
ピーク検出回路で△Vをゼロにすべく、二値符号1、O
の中心レベルを作るためピーク検波出力を電流電圧変換
回路に直流帰還する。In FIG. 1, optical signals 1 and 0 from a light emitting diode are received by a photodiode (light receiving element) 2, and a photoelectric conversion output is input to a current-voltage conversion circuit 4, and the output is sent to an AG.
C5, and the output terminals 6 and 7 output V-1+ as shown in FIG.
The peak detection output is fed back to the current-voltage conversion circuit in order to create a center level.
第3図にピーク検波と直流帰還について述べる。Figure 3 describes peak detection and DC feedback.
入力端子11,12にAGC5の出力V−,V+が入力
されるこの回路は基本的にはコンパレータとピーク電圧
保持回路より構成されている。コンパレータはT,l〜
T,3によつて構成され(V−ー+)の演算を行い、そ
の最大値をコンデンサC1に保持される。(V−一V+
)が正の場合はR1・C1の時定数でコンデンサC1を
チャージし、(V−一V+)が負の場合にはβ・R2・
C1の大きな時定数(β・R2・C1〉〉R1′C1)
でゆつくりした時間で放電し、R2の端子より電流電圧
変換回路4に直流帰還して△Vをゼロに近づける。次に
V−,V+が第4図の様にクロスオーバされたとき、そ
のV−の上部のa点のレベルが第3図の入力端子11に
入力されると、V−が高くなり、T,lが動作すると、
T,2は動作が停止し、A点の電位が上昇し、T,4が
動作し、R1・C1の時定数でC1をチヤージし、チャ
ージ電位(T,5のVbeを差引いた電位)を帰還する
。This circuit, into which the outputs V- and V+ of the AGC 5 are input to input terminals 11 and 12, basically consists of a comparator and a peak voltage holding circuit. The comparator is T,l~
It is composed of T and 3, performs the calculation of (V--+), and its maximum value is held in the capacitor C1. (V-1V+
) is positive, capacitor C1 is charged with the time constant of R1・C1, and when (V-1V+) is negative, β・R2・
Large time constant of C1 (β・R2・C1〉〉R1′C1)
The voltage is discharged in a slow period of time, and DC feedback is returned to the current-voltage conversion circuit 4 from the terminal R2, bringing ΔV close to zero. Next, when V- and V+ are crossed over as shown in Figure 4, when the level at point a above V- is input to the input terminal 11 in Figure 3, V- becomes high and T ,l operates,
T,2 stops operating, the potential at point A rises, T,4 operates, charges C1 with the time constant of R1・C1, and charges the charge potential (potential minus Vbe of T,5). Return.
逆にV+が低くなつた場合も同様にb点のレベルがゼロ
になるような動作が行なわれる。Conversely, when V+ becomes low, the same operation is performed so that the level at point b becomes zero.
これによりクロスオーバの△Vをゼロにされる。以上本
発明はV+とV−の最も近接した部分でのみ動作する。This makes the crossover ΔV zero. As described above, the present invention operates only at the closest portions of V+ and V-.
したがつて信号の振輻の影響を受けず、AGCとは独立
で動作可能という利点もある。Therefore, it has the advantage that it is not affected by signal vibration and can operate independently of AGC.
第1図は本発明の概要を示す図、第2図は発明の基本を
示す図、第3図は本発明のピーク検波回路を示す図、第
4図は第2図のV−,V+がクロスオーバしたときの図
を示す。
図で1は発光ダイオード、2はホトダイオード、3は電
源、5はAGD、7,8はV−,V+の出力端子、V+
は同極性、V−は逆極性の二値符号を示す。FIG. 1 is a diagram showing an overview of the present invention, FIG. 2 is a diagram showing the basics of the invention, FIG. 3 is a diagram showing a peak detection circuit of the present invention, and FIG. 4 is a diagram showing the peak detection circuit of the present invention. A diagram showing a cross-over is shown. In the figure, 1 is a light emitting diode, 2 is a photodiode, 3 is a power supply, 5 is AGD, 7 and 8 are V- and V+ output terminals, V+
indicates the same polarity, and V- indicates the opposite polarity.
Claims (1)
を用いて情報伝送を行なう方式において、入力信号と同
極性及び逆極性の信号を作る回路と、該同極性及び逆極
性信号のレベル差のピーク値を検出するピーク値検出回
路とを有し、該ピーク値検出回路出力を同極性信号の最
底値と逆極性信号の最大値(あるいはその逆)が一致す
る様に帰還をかけることを特徴とする二値符号直流帰還
方式。1. In a system that transmits information using a binary code in which a signal exists only on one side with respect to a reference value, a circuit that generates signals of the same polarity and opposite polarity as the input signal, and the levels of the same and opposite polarity signals. and a peak value detection circuit that detects the peak value of the difference, and feedback is applied to the output of the peak value detection circuit so that the lowest value of the same polarity signal and the maximum value of the opposite polarity signal (or vice versa) match. A binary code DC feedback method characterized by:
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55019992A JPS5941343B2 (en) | 1980-02-20 | 1980-02-20 | Binary code DC feedback method |
CA000370825A CA1175919A (en) | 1980-02-20 | 1981-02-13 | Device for discriminating between two values of a signal with dc offset compensation |
DE3105758A DE3105758C2 (en) | 1980-02-20 | 1981-02-17 | Device for distinguishing between two signal values |
GB8105318A GB2070375B (en) | 1980-02-20 | 1981-02-19 | Device for discriminating between two values of a signal with dc offset compensation |
FR8103357A FR2476323B1 (en) | 1980-02-20 | 1981-02-20 | DEVICE FOR DISCRIMINATION BETWEEN TWO VALUES OF A SIGNAL, WITH COMPENSATION OF CONTINUOUS COMPONENT |
US06/236,609 US4363977A (en) | 1980-02-20 | 1981-02-20 | Device for discriminating between two values of a signal with DC offset compensation |
CA000443220A CA1175920A (en) | 1980-02-20 | 1983-12-13 | Device for discriminating between two values of a signal with dc offset compensation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55019992A JPS5941343B2 (en) | 1980-02-20 | 1980-02-20 | Binary code DC feedback method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56117457A JPS56117457A (en) | 1981-09-14 |
JPS5941343B2 true JPS5941343B2 (en) | 1984-10-06 |
Family
ID=12014655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55019992A Expired JPS5941343B2 (en) | 1980-02-20 | 1980-02-20 | Binary code DC feedback method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5941343B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61173846U (en) * | 1985-04-17 | 1986-10-29 |
-
1980
- 1980-02-20 JP JP55019992A patent/JPS5941343B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61173846U (en) * | 1985-04-17 | 1986-10-29 |
Also Published As
Publication number | Publication date |
---|---|
JPS56117457A (en) | 1981-09-14 |
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