CA1175920A - Device for discriminating between two values of a signal with dc offset compensation - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

This invention provides a device for discriminating between two values of a signal with DC offset compensation and an automatic gain control comprising an automatic gain control circuit for receiving an incoming signal to produce a signal having the same polarity as the incoming signal and a signal having the opposite polarity of that of the incoming signal; a first level shift circuit for shifting the same polarity signal; a first peak detection circuit for receiving the output of the first level shift circuit to peak-detect the difference between the shifted same polarity signal and the opposite polarity signal; a second level shift circuit for shifting the opposite polarity signal; a second peak detection circuit for receiving the output of the second level shift circuit to peak-detect the difference between the shifted opposite polarity signal and the same polarity signal; a first feedback path for connecting the output of the first peak detection circuit with the input circuit of the automatic gain control circuit to effect DC feedback; a second feedback path for connecting the output of the second peak detection circuit with the feedback terminal of the automatic gain control circuit to effect automatic gain control; and a comparator for receiving the same polarity signal and the opposite polarity signal to produce a two value discriminated output signal, wherein the DC feedback by the first feedback path is carried out so that the minimum value of the opposite polarity signal coincides with the maximum value of the shifted same polarity signal.

Description

-- 1 .

This application is a divisional of co-pending application Serial Number 370,825, filed February 13, 1981.
The present invention relates to a device for the dis crimination between two values "1" and "0" of a signal with direct current (DC) offset compensation. The device of the present invention is used, for example, as a device for dis-criminating between two values of a signal in an LSI optical data link. The two values "1" and "0" of a signal in an LSI
optical data link correspond to the "light is ON" state and the "li~ht is OFF" state, respectively.
It is a principal object to provide an improved device for discriminating between two values of a signal W7 th DC
offset compensation, in order to solve the above described problemsO
In accordance with the present invention, there is pro-vided a device for discriminating between two values of a signal with DC offset compensation and an automatic gain control comprising an automatic gain control circuit for receiving an incoming signal to produce a signal V(+) having the same polarity as the incoming signal and a signal V(-) having the opposite polarity of that of the incoming signal; a Eir~t level shift circuit for shifting the same polarity signal; a ~irst peak detection circuit ~or receiving the ~; :

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output of the first level shift circuit to peak-detect the difference between the shifted same polarity signal and the opposite polarity signal; a second level shift circuit for shifting the opposite polarity signal; a second peak detection 5 circuit for receiving the output of the second level shift circuit to peak-detect the difference between the shifted opposite polarity signal and the same polarity signal; a first feedback path for connecting the output of the first peak detection circuit with the input circuit of the automatic gain control circuit to effect DC feedback; a second feedback path for connecting the output of the second peak detection circuit with the feedback terminal of the automatic gain control circuit to effect automatic gain control; and a comparator for receiving the same polarity signal and the opposite polarity signal to produce a two value discriminated output signal, wherein the DC feedback by the first feedbacX path is carried out so that the minimum value of the opposite polarity s~gnal coincides with the maximum value of the shifted same polarity . signal.
A still further embodiment of the present invention provides a device for discriminating between two values of a ~ignal using DC offset compensation and automatic gain control, compri~ing an automatic gain control circuit having 1. ~ '7~

an input and a feedback terminal, for receiving an incoming signal and for generating both a same polarity signal having the same polarity as the incoming signal and an opposite polarity signal having opposite polarity to that of the incoming signal; a first level shift circuit, operatively connected to the automatic gain control circuit, for generating a shifted same polarity signal by shifting the same polarity signal and for passing therethrough the opposite polarity signal; a first peak detection c.ircuit, operatively connected to the first level shift circuit, for receiving the output of the first level shift circuit and for peak-detecting the difference betwen the shifted same polarity signal and the opposite polarity signal; a second level shift circuit, operatively connected to the automatic gain control circuit, for generating a shifted opposite polarity signal by shifting the opposite polarity signal and for passing therethrough the same polarity signal; a second peak detection circuit, operatively connected to the second level shift circuit, :Eor receiving the output of the second level shift circuit and for peak-detecting the difference between the shifted opposite polar.ity signal and the same polarity signal; a first Eeedback path Eor connecting the output oE the first peak detection circuit with the input oP the automatic gain control circuit to efEect DC feedback; a second Eeedback path Eor connecting the output o~ the second peak detection circu.it with the feedback terminal of the automatic gain control circuit . . .

to effect automatic gain control; and a comparator, operatively connected to the automatic gain control c.ircuit, for receiving the same polarity signal and the opposite . polarity signal, for generating a two value discriminated output signal, wherein the DC feedback by the first feedback path is carried out so that the minimum va:Lue of the opposite polarity signal coincides with the maximum value of . the shifted same polarity signal.
A still further embodiment of the present invention relates to a device for discriminating between two values of an incoming signal, comprising an automatic gain control circuit, operatively connectable to receive the incoming ~ignal, for generating a first signal and a second signal; a first level shift circuit, operatively connected to the automatic gain control circuit, for shifting the first signal by a first predetermined value and for passing therethrough the second signal; a first peak detector circuit, operat.ively connected to the first level shift circuit and to the automatic gain control circuit, for detecting the peak of a first difference between the shifted first signal and the second signal and for generating a feedback signal in dependence on the fir~t diEference; a second level shift circuit, operatively connected to the automatic gain control circuit, for shifting the second slgnal by a second predetermined value and for pa~sing therethrough the .Eirst signal; a second peak detector, operatively connected to the level shift circuit and to the automatic gain control circuit~ for detecting the peak of a second difference between the shifted second signal and the first signal and for generating the gain control signal in dependence on the second difference, the automatic gain control circuit generating the ~irst and second signals in dependence upon the incoming signal, the feedback signal and the gain control signal; and a comparator, operatively connected to the automatic gain control circuit, for comparing the second signal and the first signal and for generating a discriminated signal in dependence upon the comparison, so that the two values of the incoming signal are discriminated.
Having thus generally described the invention, reference will now be made to the accompanying drawings illustrating preferred embodiments of the invention, a.nd in which:
Figs. l(A) through ltI) illustrate the relationships be-tween an original signal, the inverted signal and theshi.Eted signal ~or explaining the problem in discriminating between the values o~ a received signal;
E'igs. 2 and 3 illustrate an embodiment o~ the present invention;

Figs. 4(A) through 4(G) and 5(A) through 5(G) illustrate the waveforms of the signals present in the cir-cuit of Figs. 2 and 3;
Figs. 6, 7 and 8 illustrate another embodiment of the present invention; and Figs. 9(A) through 9(C), lO~A) through lO(C), ll(A) through ll(C) and 12(A) through 12(C) illustrate the wave-forms of the signals present in the circuit of Fig`s. 6, 7 and 8.
Dealing now with the prior art~ when the value signal which is sent from a transmitting side is discriminated at a receiving side, if it is impossible to obtain the central level at the receiving side by DC regeneration, a method for discriminating between the two values "1" and "0" of the re-ceived signal is carried out as illus-trated in Figs. l(A), 1(B) and l(C). From a received signal SIGNAL-I, the in-verted signal SIGNAL-II and the shifted signal SIGN~L-III
are obtained as illustrated in Figs. l(A) and l(B). The amount of the shift is equal to the amplitude VS of SIGNAL-I. Comparing the two signals SIGNAL-II and SIGNAL-III, a signal SIGNAL-IV is obtained so as to represent the result o~ the discrimination of -the received signal SIGNAL-I as illustrated in Fig. l(C).

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'`' In this method, however, a problem is incurred if the basic levels of SIGNAL-I and SIGNAL-II do not coincide and , hence a DC offset OFS is formed between SIGNAL-I and SIGNAL-II as illustrated in Figs. l(D) and l(G), under the condi-tion that the value of maximum amplitudes of SIGNAL-I and SIGNAh-II is limited within a predetermined value v(max)~
This is because, the discrimination margin MG formed by SIGNAL-II and SIGNAL-III is reduced compared with the case of FigsO l(A), l(B) and l(C~ as illustrated in Figs. l(E) and l(H), and accordingly the discrimination of the value of the received signal cannot always be conducted correctly.
Also, a prior art method is disclosed in U.S. Patent No. 4,027,152 in which a signal which is sent from a transmitting side and has three values is used and the dis-crimination of the signal received at a receiving side iscarried out by using a basic level which is obtained as the result of the integration of the received signal. Mowever, this prior art method re~uires a process of making the three valued signal and causes a reduction of the discrimination margin because of the use of the three valued signal. There-~ore, thi3 prior art cannot provide a complete solution for the discri~ination o~ the received signal having plural values.

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The circuit of a device for discriminati.ng between two values of a signal with DC offset compensation as an embodiment of the present invention is illustrated in Figs~

2 and 3, where Fig. 3 illustrates the peak detector device 4 of the circuit of ~ig. 2.
An input signal is supplied to one input terminal of a current to voltage conversion circuit 2. Said input signal represents the value "i1 - i2" where il is the current of a photodiode 12 irradiated by a light beam 11 and i2 is the feedback current. The output signal Vl of the current to voltage conversion circuit 2 is supplied to one input terminal 31 of an automatic gain control circuit 3, while a reference signal Vrefl is supplied to the other input terminal 32. The value of the signal Vl is equal to the value "il - i2" multiplied by the value R where R
represents a predetermined resistance value.
~ i2).R (1) The automatic gain control circuit 3 produces the output signals V(+) and V(-) which are expressed as follows:

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g _ V(~ Vl (2) V(~ a-Vl . (3) where is the amplification factor of the automatic gain control circuit 3. The signal V~+) is of the same polarity as the signal Vl, while the signal V(-) is ~he opposite . polarity of tha~ of the signal Vl. The produced signals V~) and V(-) are supplied to the input terminals of a peak detector device 4. An example of the structure of the peak detector device 4 is illustrated in Fig. 3.
The peak detector device 4 consists of a differential amplifier circuit 41 and a peak detection circuit 42. The differential amplifier circuits provide transistors 411, - 412 and 413 so that the subtraction "V(-) - Vl+) n is carried outO The maximum value of the result of this subtraction is stored in a capacitor 424 in the peak de-tection circuit 42.
If V(-) - Vl+) ~ 0, the transistor 421 turns ON and hence the capacitor 424 is charged up with a time constant determined by the capacitor 424 and a resistor 423 to increase the voltage of the capacitor 424 so that the voltage across the resistor 425 is increased. Due to the increase o~ the voltage across the resistor 425, the voltage at the output terminal 426 of the peak detector device 4 is increased and hence the feedhack current i2 passing through a ~eedback resistor 8 is decreased. Thust the value of i2 is decreased to approach the basic value of il of the current of the photodiode 12 so that the minimum value of V~) and the maximum value of Vl-) tend to become equal.

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Contrary to the above, if V(-~ - Vl+) < 0, the tra~-sistor 421 turns OFF and hence the charge stored in the capacitor 424 is slowly discharged with a time con~tant determined by the capacitor 424, a resistor 425 and the current amplification factor of a trans:istor 422 to decrease the voltage of the capacitor 424 so that the voltage across the resistor 425 is decreased. Due to the decrease of the voltage across the resistor 425, the voltage at the output terminal 426 of the peak detector de~ice 4 is decreased and hence the feedback current i2 passing through a feedback resistor 8 is increased. Thus, the value of i2 is increased to approach the basic value of il of the current of the photodiode 12 90 that the minimum value of V(+) and the maximum value of V(-) tend to become equal.
The operation of the circuit of Figs. 2 and 3 is illustrated in Figs. 4(A) through 4(G~ and 5(A) throuyh 5(G). Figs. 4(A) through 4(G) corresponds to the case where V(-) - V(+) > 0, while Figs. 5(A) through 5(G) cor-responds to the case where V(-) - V(~) < 0.
With regard to Figs. 4(A) through 4(G), the state of tha signals present in the circuit of Fig. 2 is illustrated in Figs. 4~A) through 4(F) and an offset OFS, exists between the basic levels o~ V(~) and V~ ). As the rasult o~ the operation o~ the circuit of Fig~ 2, the state of V(~3 and V(-) changes into the state illustrated in Fig. 4(G) in which the o~fset OFS, approaches æero.
With regard to Figs. 5~A) through 5(G)/ the state of the signals present in the circuit of Fig. 2 is illustrated 2~ .

in Figs. 5(A) through 5(F) and an offset OFS2 exists between the basic levels of V(~ and V(-l. As a result of the opera-tion of the circuit of Fig . 2, the state of V(~) and V( ) changes into the state illustrated in Fig. 5(G) in which the offset OFS2 approaches zero.
In consequence, the offset between the basic levels of the signal V(~) and the signal V(-) is eliminated to achieve the DC offset compensation, and accordingly the discrimination of the value of the received signal is carried out correctly.
One output signal (V~) of the automatic gain control cir-cuit 3 is supplied through a level shift circuit 91 to one in-put terminal of a comparator 92, and the other output signal V(-) of the automatic gain control circuit 3 is suppli~d to the other input terminal of the comparator, to produce an output signal either "1" or "0" as the result of the discrimination of the received signal.
Although in the above described embodiment, the waveform of the received signal is such that the waveform is situated above the basic level, it is also possible to use a received signal having such a waveform situated below the basic level.
However, it should be noted that the maximum value of V(~) and the minimum value o~ V~-) are to be equalized in the case where such waveform is situated below the basic level.
The circuit o~ a device ~or discriminating between two values of a signal with DC oeEset compensation and automatic gain control as another embodiment o~ the present invention i9 illustrated in ~igs. 6, 7 and 8, where Figs. 7 and 8 illustrate the level shift circuits 40 and 60 and the peak detection circuits S0 and 70 of the circuit of Fi~. 6.
The output signal Vl of a current to voltage conversion circuit 20 is supplied to one input terminal 301 of an automatic gain control amplifier circuit 30. A reference voltage Vrefl is supplied to the other input terminal 302 of the automatic gain control amplifier circuit 30. An automatic gain control feedback signal Vagc is supplied to the feedback terminal 303 of the circuit 30. Assuming that the amplification factor~of the automatic gain control amplifier circuit 30 is ~, the open loop gain is Qm and the control factor is y, the~following equation is obtained..
(l - yVagc) (4) The automatic gain control amplifier circuit 3Q pro-duces a signal V~) which has the same polarity as the input signal Vl and a signal V(-) which has the opposite polarity of that of the input signal Vl~ The produced signals V(+) and V(-) are supplied to a first level shift circuit 40 and to a second level shift circuit 60. The output of the first level shift circuit 40 is supplied to a firs~ peak detection circuit 50, the output signal i2 f which is supplied as a DC:feedback signal through a feedback resistox 80 to the input circuit of khe current to voltage conver~ion circuit 20. The output of the second level shi~t circuit 60 is supplied to a second peak detection circuit 70, the output signal VagC of which is supplied as an automatic gairl control ~eedbac~ signal to the feedback terminal 303 o~ the circuit 30.
The details of the level æhift circuit 40 and the peak :

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detection circuit 50 are illustrated in Fig. 7. The level shift circuit comprises transistors 4~1 and 402. To the bases of the transistors 401 and 402 the signal V(~) and the signal V~-) are supplied, respectively. The signal V(+) is level shifted, by a predetermined value VS ~ to become the signal V(+)i due to the existence of a resistor 403.
The shifted signal V(~)' is supplied to the base of a tran-sistor 501 in the peak detection circuit. The siynal V~-) is supplied to the base of a transistor 502. The differ-ence between the values V(~)' and V(-3 which is obtained in the peak detection circuit 5G is supplied to a circuit con-sisting of a resistor 508, a capacitor 509, a transistor 507 and a resistor 510.
The capacitor 509 is charged with a ti~e constant determined by the capacitor 509 and the resistor 508 and discharged with a time constant determined by the capacitor 509, the resistor 510 and the current amplification factor o~ the transistor 507. Thus, a DC feedback current i2 flows between the output terminal 511 of the peak detection circuit 50 and one of the input of the current to voltage conversion circuit 20 through a feedback resistor 80. The DC feedback is carried out so that the minimum value o~
said opposite polarity signal V~ ) coincides with the ma~imum value o~ said shi~ted same polarity signal V(~t) ~ .
The operation o~ the circuit o~ Fig. 7 is illustrated in Figs. 9~A) through ~(C) and lO(A) through lO(C). It can be understood that the relationship between (V-) and V(~)' in Figs. 9(B) and 10(B) corresponds to the relationship between V(+) and V(-) in Fiys. 4(F) and 5(Fl ~or the oper-: ation of the circuit of Fig. 3.
The details of the level shift circ`uit 60 and the peak detection circuit 70 are illustrated in Fig. 8. The level shift circuit comprises transistors 601 and 602. To the bases of the transistors 601 and 60~ the signal (V~) and the signal V~-) are supplied, respectively. ~he signal Y~-) is level shifted, by a predetermined value Vs ~ to become the signal V(-)' due to the existence of a resistor 604. The shifted signal V(-)' is supplied to the base of a transistor 702 in the peak detection circuit 70.
The signal V(+) is supplied to the base of a transistor 701.
The difference between the values V(-)' and V~+) which is obtained in the peak detection circuit 70 is supplied to a circuit consisting of a resistor 708, a capacitor 709, a transistor 707 and a resistor 710.
The capacitor 709 is charged with a time constant determined by the capacitor 709 and the resistor 708 and discharged with a time constant determined by the capacitor 709, the resistor 710 and the current amplification factor of the transistor 707. Thus, an automatic gain control signal Vagc is sent from the output terminal 711 of the pea~
detection circuit 70 and is supplied to the ~eedback termi-nal 303 o~ the automatic gain control circuit 30. The auto-matic gain control is carried out so that the minimum valueof s~id same polarity signal V~) coincides with the maximum value of said shifted opposite polarity signal V(-)'.
The operation of the circuit of Fig. 8 is illustrated s~z~
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in Figs. ll(A) through ll(C) and 12~A) through 12(C~. It can be understood that the relationship between Vt+) and V(-)' in Figs. ll(B) and 12(B) corresponds to the relation-; ship between V(~ and V(-) in Figs. 4(F) and 5(F) for the operation of the circuit of Fig. 3.
Figs. 9(A) and lO(A) illustrate th~e state before the feedback for DC compensation is carried out. The differ-ence between the V(+) center level and the V~-) center level is equal to "a(vc ~ Vrefl ~ 17 ~ where a is the amplifi-cation factor of the automatic gain control amplifiercircuit 30, VC is the voltage of the center level of the signal Vl and Vrefl is the reference voltage.
As the result of the feedback ~or DC compensation the di~ference tends to become zero as illustrated in Figs. 9(C) and lO(C).
Figs. ll~A) and 12(A) illustrate the state before the feedback for automatic gain control is carried out. It is assumed that the amplitude of each of V(+) and V(-) is not equal to VS but equal to either ~Ivs +k" or ''Vs -k" where k is a predetermined value. The value "VS +k~ is equal to ''~(Va ~ Vrefl)", where va is the amplitude of the signal Vl.
~s a result o~ the ~eedhack ~or automatic gain control the amplitude of each o~ V(~) and V(-) tends to become equal to Vs as illustrated in Figs. ll(C) and 12tC).
The output signals V~) and V(-) o~ the automatic gain control circuit 3 are supplied to a comparator 90 to produce an output siynal either "1" or "o~ as a result of discrimi-nation the received signal.

Claims (5)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. A device for discriminating between two values of a signal with DC offset compensation and an automatic gain con-trol comprising:
an automatic gain control circuit for receiving an incoming signal to produce a signal having the same polarity as said incoming signal and a signal having the opposite polarity of that of said incoming signal;
a first level shift circuit for shifting said same polarity signal;
a first peak detection circuit for receiving the out-put of said first level shift circuit to peak-detect the differ-ence between said shifted same polarity signal and said oppo-site polarity signal;
a second level shift circuit for shifting said oppo-site polarity signal;
a second peak detection circuit for receiving the out-put of said second level shift circuit to peak-detect the dif-ference between said shifted opposite polarity signal and said same polarity signal;
a first feedback path for connecting the output of said first peak detection circuit with the input circuit of said automatic gain control circuit to effect DC feedback;
a second feedback path for connecting the output of said second peak detection circuit with the feedback terminal of said automatic gain control circuit to effect automatic gain control; and a comparator for receiving said same polarity signal and said opposite polarity signal to produce a two value dis-criminated output signal, wherein said DC feedback by said first feedback path is carried out so that the minimum value of said opposite polarity signal coincides with the maximum value of said shifted same polarity signal.

2. A device as defined in claim 1, wherein said auto-matic gain control by said second feedback path is carried out so that the minimum value of said same polarity signal coin-cides with the maximum value of said shifted opposite polarity signal.

3. A device for discriminating between two values of a signal using DC offset compensation and automatic gain con-trol, comprising:
an automatic gain control circuit having an input and a feedback terminal, for receiving an incoming signal and for generating both a same polarity signal having the same polarity as said incoming signal and an opposite polarity signal having opposite polarity to that of said incoming signal;
a first level shift circuit, operatively connected to said automatic gain control circuit, for generating a shifted same polarity signal by shifting said same polarity signal and for passing therethrough said opposite polarity signal;

a first peak detection circuit, operatively connected to said first level shift circuit, for receiving the output of said first level shift circuit and for peak-detecting the dif-ference between said shifted same polarity signal and said oppo-site polarity signal;
a second level shift circuit, operatively connected to said automatic gain control circuit, for generating a shifted opposite polarity signal by shifting said opposite polarity signal and for passing therethrough said same polarity signal;
a second peak detection circuit, operatively con-nected to said second level shift circuit, for receiving the output of said second level shift circuit and for peak-detecting the difference between said shifted opposite polarity signal and said same polarity signal;
a first feedback path for connecting the output of said first peak detection circuit with the input of said automa-tic gain control circuit to effect DC feedback;
a second feedback path for connecting the output of said second peak detection circuit with the feedback terminal of said automatic gain control circuit to effect automatic gain control; and a comparator, operatively connected to said automatic gain control circuit, for receiving said same polarity signal and said opposite polarity signal, for generating a two value discriminated output signal, wherein said DC feedback by said first feedback path is carried out so that the minimum value of said opposite polarity signal coincides with the maximum value of said shifted same polarity signal.

4. A device as defined in claim 3, wherein said auto-matic gain control by said second feedback path is carried out so that the minimum value of said same polarity signal coin-cides with the maximum value of said shifted opposite polarity signal.

5. A device for discriminating between two values of an incoming signal, comprising:
an automatic gain control circuit, operatively con-nectable to receive the incoming signal, for generating a first signal and a second signal;
a first level shift circuit, operatively connected to said automatic gain control circuit, for shifting the first sig-nal by a first predetermined value and for passing therethrough the second signal;

a first peak detector circuit, operatively connected to said first level shift circuit and to said automatic gain control circuit, for detecting the peak of a first difference between the shifted first signal and the second signal and for generating a feedback signal in dependence on the first dif-ference;
a second level shift circuit, operatively connected to said automatic gain control circuit, for shifting the second signal by a second predetermined value and for passing there-through the first signal;
a second peak detector, operatively connected to said level shift circuit and to said automatic gain control circuit, for detecting the peak of a second difference between the shifted second signal and the first signal and for generating the gain control signal in dependence on the second difference, said automatic gain control circuit generating the first and second signals in dependence upon the incoming signal, the feedback signal and the gain control signal; and a comparator, operatively connected to said automatic gain control circuit, for comparing the second signal and the first signal and for generating a discriminated signal in depen-dence upon the comparison, so that the two values of the in-coming signal are discriminated.