JPS594079A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the defect density of a gate oxide film by treating an Si substrate at a specified temperature or above so as to remove the distortion of a crystal lattice near the surface of the substrate and to prevent the outward diffusion of impurities at the time of treatment. CONSTITUTION:A P type Si substrate 1 doped with B is treated at the temperature of 1,000 deg.C for one hour in an Ar gas containing a very small quantity of H2O to form an SiO2 film 2 of about 1,000Angstrom , and subsequently, a poly Si film 3 of about 3,000Angstrom is superposed thereon by a CVD method. Next, after the film 3 is doped with B, a treatment is applied for two hours at the temperature of 1,100 deg.C (a temperature of not less than 1,050 deg.C is sufficient) in the Ar gas containing O2 of 10% partial pressure, poly Si 3 is removed by a dry chemical etchihg method, and the SiO2 film 2 is removed by a buffer fluoric acid. Then, a gate oxide film 4 is formed on the Si substrate 1 in dried O2, a poly Si gate electrode 5 is attached thereto, and thereby MOS capacity is completed. This constitution enables the removal of the distortion of a crystal lattice without alteration of the distribution of an impurity density in the vicinity of the surface of the substrate, and the reduction of the defect density of the gate oxide film, and thus the characteristics of the device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor manufacturing technology, and particularly to semiconductor manufacturing technology.
The present invention relates to a method for manufacturing a semiconductor device that requires a thin r-) oxide film of less than CX].

[Technical background of the invention and its problems]

Conventionally, the method for manufacturing semiconductor devices is to form an oxide film on a silicon substrate, then form a silicon nitride film that acts as an oxidation-resistant mask on the nuclear oxide film, and then photoetch this silicon nitride film. After that, a relatively thick oxide film (field oxide film) is formed in the area where the silicon nitride film has been removed. Subsequently, a so-called selective oxidation process is employed in which the silicon nitride film and the oxide film thereunder are removed to expose the silicon substrate and an oxide film is formed again. This selective oxidation method is attracting attention as an indispensable technology for high-density integrated circuits.

By the way, in the above method, when the silicon nitride film used as a rigid oxidation mask is oxidized in an atmosphere containing water vapor, the water vapor and the silicon nitride film react to generate ammonia. This ammonia is silicon nitride)1U1
It diffuses through the underlying silicon oxide film, reaches the underlying silicon substrate surface, and nitrides that surface. This surface compound becomes an oxidation-resistant mask again in the subsequent process, so for example, y-to oxidation fl! ! If this happens, the withstand voltage of the oxide film itself will be extremely reduced.

Recently, in order to prevent the deterioration of the oxide breakdown voltage, a method has generally been adopted in which the silicon surface is further oxidized before dirt oxidation and the nitride film that serves as a mask for dirt oxidation is removed.

However, even with such measures, it has not been possible to reduce the oxide film defect density of the dirt oxide film by selective oxidation to a level sufficient for use in high-density integrated circuits.

The reason for this is thought to be as follows. That is, in the conventional integrated circuit manufacturing technology, a silicon ingot is cut into wafer shapes, the surfaces of which are polished, and then the wafers are introduced into the integrated circuit manufacturing process.

In the above integrated circuit manufacturing process] 000[℃
] is generally adopted as an upper limit, and recently, due to the demand for miniaturization, lowering the temperature of the manufacturing process is being considered. However, in the above process at temperatures below 1 (10 (+ [℃)], it was not possible to avoid oxide film breakdown voltage defects caused by S'l wafer, resulting in a significant decrease in productivity. In the process of polishing and polishing the surface, impurities such as heavy metals are captured in the strained crystal lattice layer introduced near the silicon surface. Impurities such as heavy metals captured near the silicon surface are incorporated into the oxide film. If the silicon substrate is directly subjected to high-temperature heat treatment or high-temperature oxidation, the St surface will be damaged. The impurity concentration distribution in the vicinity changes,
There was a drawback that the threshold voltage and the like of elements formed later changed. Even if the broken impurities such as heavy metals are dattered onto the back surface before the selective oxidation step, there is a drawback that impurities such as heavy metals introduced during the selective oxidation step or the dirt oxidation step cannot be prevented.

[Purpose of the invention]

An object of the present invention is to be able to remove a strained crystal lattice layer on the surface of a silicon substrate without causing a change in the concentration distribution of major impurities near the surface of the silicon substrate, and to reduce the defect density of a dirt oxide film, thereby achieving a cylindrical density integrated circuit. An object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to improving device characteristics.

[Summary of the invention]

According to the present invention, the strained crystal lattice layer near the surface of the silicon substrate is removed by heat-treating the silicon plate at a high temperature of H150 [°C] or higher, and during this heat treatment, the main impurities in the silicon substrate diffuse outward. The reason lies in the fact that it was prevented from happening.

That is, in manufacturing a semiconductor device, the present invention forms a silicon oxide film on the surface of a silicon substrate by a thermal oxidation method, and then impurities of the same type as the main impurity of the silicon substrate are added to the same concentration on this silicon oxide lIv. In this method, a polycrystalline silicon film containing the above is formed, and then the silicon substrate is heat-treated at a high temperature of 1050°C or higher in an inert gas containing an oxidizing agent at a low partial pressure, and then an element forming process is performed. .

゛However, in the present invention, after the above heat treatment step, the back surface of the silicon substrate is exposed and the impurity concentration is 10 [α] on the back surface.
This is a method in which the above phosphorus diffusion layer is formed [2], and then an element forming step is performed.

゛However, in the present invention, after forming a first silicon oxide film on the surface of a silicon substrate by thermal oxidation method, the same kind of impurity as the main impurity of the silicon substrate is added to the same degree on this first silicon oxide film. A first polycrystalline silicon film containing a polycrystalline silicon film having a concentration higher than or equal to the concentration of polycrystalline silicon is formed, and then the silicon substrate is heat-treated at a temperature of 1050 [°C] or higher in an inert force containing a low stress oxidizing agent. After removing the side of the polycrystalline silicon, an oxidation-resistant film is formed to mask the element forming region in the first silicon oxidation layer, and then a Sifield fermentation film is formed by a thermal oxidation method. After removing the silicon oxide film and the oxidation-resistant film, a second silicon oxide film and a second polycrystalline silicon film are formed on the surface of the semiconductor substrate, and then the back surface of the silicon substrate is exposed and impurities are once applied to the back surface. 1- (lCtyn:]
This is a method in which the above phosphorus diffusion layer is formed and then an element forming step is performed.

〔Effect of the invention〕

According to the present invention, it is possible to perform high-temperature heat treatment while suppressing changes in the concentration distribution of main hair impurities on the surface of the silicon substrate, thereby removing the strained crystal lattice layer near the surface of the silicon substrate and eliminating defects in the substrate oxide film. Achieves density reduction. moreover,
By forming a back surface phosphorus diffusion layer, impurity duttering can be effectively performed on the front surface, and it is also possible to significantly reduce the defect density of the dirt oxide film. Therefore, still
M It is effective in improving the productivity of prefectural product circuits. Also, 2
Since the defect density can be lowered even for thin silicon oxide films of 00 [X:] or less, the applications of thin silicon oxide films can be significantly expanded, and the ripple effect is extremely large.

[Embodiments of the invention]

Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 (IL) (b) is a cross-sectional view showing the manufacturing process of a MOS capacitor according to the first embodiment of the present invention.

First, as shown in Figure 1(a),
) obtained by law, fc about I X I 016[m-3
] A boron doug P-type (100) Si substrate 1 is prepared, and its surface is heated at a temperature of 10 (
Oxidize at JO[℃] for 1 hour to 1ooo[X] (7) 1st
A silicon oxide film 2 is formed. Subsequently, a first polycrystalline silicon film 3 having a thickness of about 300[X] is formed on the silicon substrate 1 by the LPCVD method. Then, by ion implantation, polycrystalline silicon llQ, 9Vc3X10'' [crn-
2] Dorf 0 boron. Then, the branch 51 pressure is 10
C%] in Ar gas at a temperature of 11 (10° C.) for 2 hours. Subsequently, after removing the polycrystalline silicon film 3 by chemical dry etching, the silicon oxide film 2 is etched with buffered hydrofluoric acid. Remove.

Next, as shown in FIG. 1(b), a dirt oxide film 4 of 400 [X] is formed on the silicon substrate 1 in dry oxygen, and a phosphorus-doped oxide film 4 is formed on this dirt oxide film 4 by the CVD method. Deposit a crystalline silicon film. Then, a MOS capacitor is fabricated by turning the phosphorous-doped polycrystalline silicon film by photolithography to form a dirt electrode 5.

FIG. 2 is a characteristic diagram showing the withstand voltage histogram of a conventional MOS capacitor formed without performing the above-mentioned high-temperature heat treatment, and FIG. FIG. 3 is a characteristic diagram showing a breakdown voltage histogram of a V10s capacitor. From these figures, it can be seen that in this example, the frequency of defects exhibiting a withstand voltage of 7 [MV/m] or less due to oxide film defects is significantly reduced. However, Figure 4 shows the characteristic OO showing the impurity concentration distribution near the surface of the silicon substrate.
℃] The case of a substrate obtained by heat treatment in dry oxygen for 2 hours is shown. From this figure, it can be seen that the method of this example suppresses the outward diffusion of the main impurities of the silicon substrate 1 during the tube temperature heat treatment. Thus, according to this embodiment,
The defect density of the keto oxide film 4 can be reduced without causing a change in the concentration distribution of main impurities on the surface of the silicon substrate 10.

FIGS. 5(a) to 5(d) are cross-sectional views showing the manufacturing process of a MOS capacitor according to the second embodiment. In addition, 8T!
] Figure (,) The same parts as in (b) are given the same symbols,
A detailed explanation thereof will be omitted. This embodiment differs from the previously described embodiments in that a phosphorus diffusion layer is provided on the back surface of the silicon substrate 1 and heavy metals are doubled therein. That is, as shown in FIG. 5(a), a silicon oxide film 2 and a polycrystalline silicon film 3 are formed on the front and back surfaces of a silicon substrate 1. Next, by ion implantation, the polycrystalline silicon film 3 is
×1011 [Crn-2] doped with boron, followed by a medium ball in Ar gas with an oxygen partial pressure of 10 C%] [°C]
Heat treatment at a temperature of 2 hours. The process up to this point is the same as the previous embodiment.

Next, polycrystalline silicon film 3 and silicon oxide film 2 formed on the back surface of silicon substrate 1 are removed to expose the back surface of silicon substrate 1.

Next, the silicon oxide film 2 and polycrystalline silicon film 3 remaining on the surface of the silicon substrate 10 are masked, and POCt3 is diffused at 1 (+00[°C] for 30 minutes, as shown in FIG. 5(b). A phosphorous-concentrated diffusion layer 6 is formed.Next, the polycrystalline silicon film 3 and the silicon oxide 11*2 are removed by etching as shown in FIG. A dirt oxide film 4 of 200°C is formed at a temperature of 900°C, and a phosphorous-doped polycrystalline silicon film 5 is deposited on this dirt oxide film 4 by CVD. Then, by turning the phosphorus-doped polycrystalline silicon film 5 by photolithography to form a dirt electrode 6, an MO as shown in FIG. 5(d) is formed.
An S capacitor will be created.

FIG. 6 is a characteristic diagram showing the withstand voltage histogram of the keto oxide film 4 with a film thickness of 20 (l [i]) formed after performing the high temperature heat treatment and backside phosphorus diffusion treatment shown in this example. From this figure, 8[+1/IV/
It can be seen that the frequency of breakdown voltage failures below [cn] has been significantly reduced, and is also much better than the breakdown voltage histogram of the first embodiment shown in FIG. Therefore, according to this embodiment, not only the same effects as the first embodiment described above can be achieved, but also the defect density of the gate oxide film 4 can be further reduced.

Figures 7(,) to (g) are MOSs related to the pressure of the third embodiment.
) is a sectional view showing the transistor manufacturing process. In addition, the first
The same parts as in Figures (,) (b) and Figures 2 (,) to (c) are designated by the same reference numerals, and detailed explanation thereof will be omitted.

First, similar to the first and second embodiments described above,
As shown in FIG.
silicon oxide films 2 and first polycrystalline silicon film 3
form. Furthermore, polycrystalline silicon 11Q3 was doped with 3×10" [cm -2 of poron by ion implantation, and then 110 cm -2 of poron was doped into polycrystalline silicon 11Q3 in Ar gas with an oxygen partial pressure of 1O [chi].
Oxidize at 0 [℃] temperature for 2 hours.

Next, after etching the polycrystalline silicon film 3, the LPC
< 2on, as shown in Figure 7(b), by the VD method.

[X] grade silicon nitride 11, (antioxidizing film) 7
is deposited, and the silicon oxide film 7 is patterned by photolithography. Next, on the silicon substrate 1 in the field area? An ion implantation layer 8 is formed by implanting ion ions. 10 (lo) using the silicon nitride film 7 as a mask.
t:° C.] A field oxide film 9 having a thickness of 10 μm is formed as shown in FIG. 7(C) by the hydrogen combustion method. Next, silicon nitride film 7 and silicon oxide film 2 are removed by etching. Subsequently, oxidation was performed at 1000[° C.] in 7 Ar gas containing a trace amount of water vapor for one hour, and a second silicon oxide film 1 of 100[X] was formed on the surface of the substrate 1 as shown in FIG. 4(d).
0 is formed, and then a second polycrystalline silicon film NO having a thickness of about 3000 [kilometers] is formed on the oxide films 9 and 10 by the LPCVD method.

Next, a resist (not shown) is applied on the second polycrystalline silicon film 1 and solidified at 150 [°C], and the oxide film 9 on the back side is coated with a resist (not shown).
The back surface of the silicon substrate 1 is exposed by etching. After removing the resist, phosphorus is diffused at 100° C. for 30 minutes to form a highly concentrated phosphorus diffusion layer 6 on the back surface of the silicon substrate 1.

Next, polycrystalline silicon 1lIi! is formed on the surface of silicon substrate 1. ! After etching and removing the silicon oxide film 10, a dirt oxide film (third silicon oxide film) 12 of 400 (z) is formed in dry oxygen as shown in FIG. 7(e). Next, this dirt oxide film 1
A phosphorous-doped polycrystalline silicon film (third polycrystalline silicon film) with a thickness of 30 (10CX) is deposited on the dirt electrode 1 by CVD and then patterned by photolithography.
form 3. Thereafter, the dirt oxide film 12 is etched using the gate electrode 13 as a mask. Then, As ions are implanted while masking the field acid hole film 9 and the gate electrode 13, and an n-type high concentration impurity layer is formed into the source/drain 14 with a depth of 0.6 [μ+711].
a, 14b are formed. Next, as shown in FIG. 7(f), a CVD-SiO2 film with a thickness of 30 (10 CA) was applied to the entire surface.
Film 15 and a phosphorus silicide glass film (P
SG film) 16 is deposited. After this, proceed to the normal process)CVD-sio2Mz 5 and PSG film 16
, a contact hole is opened in , an At interconnection film 17 is deposited by the snow jitter method, and an At interconnection film 1 is formed by photolithography.
Figure 7 (g) from LIC after patterning step 7.
This is because a MOS transistor as shown in FIG.

Thus, according to this embodiment, the defect density of the dirt oxide film 12 can be reduced as in the previous embodiment, and the confectionery characteristics of the MOS transistor can be improved.

Note that the present invention is not limited to the embodiments described above. For example, the oxidation source Jf of the first oxide film is IO'
The film thickness is not limited to 1 (10[ The film thickness of the first polycrystalline silicon film may be at least 200 mm to prevent etching of the first silicon oxide film during the buffered hydrofluoric acid treatment in the wafer cleaning process. X) It is sufficient that the film is thick enough to prevent the entire first polycrystalline silicon from being oxidized during madder temperature heat treatment and back surface phosphorus diffusion. The amount added is 3
X 10''[cnl-'' 13, however, this may be in a range of the same level or several times the impurity concentration of the silicon substrate. That is, it is sufficient that there is no apparent exchange of impurities between the silicon substrate and polycrystalline silicon during the high-temperature heat treatment. Further, the second polycrystalline silicon film used as a mask for rear surface phosphorus diffusion may be replaced with a thick CVD-8102 film or the like. In short, it is sufficient to act as a mask to prevent phosphorus from diffusing to the front surface when phosphorus is diffused to the back surface. Also, Figure 1 (a), Figure 5 (a), and Figure 7 (,)
The high humidity heat treatment is carried out in the process of 10% oxygen partial pressure.
[H] In Ar gas at a high temperature of 3100 [° C.] for 2 hours, the Ic is not limited in any way. In short, if the first polycrystalline silicon film is not completely oxidized] U3
The temperature may be any temperature higher than O [° C.], any partial pressure of the oxidizing agent may be used, and it goes without saying that the inert gas may be N2 instead of Ar. Further, the present invention can be applied not only to MOS capacitors and MOS transistors, but also to various semiconductor devices that require a thin r-) oxide film. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are cross-sectional views showing the manufacturing process of a MOS cannon according to the first embodiment of the present invention, and FIGS. 2 to 4 are only for explaining the operation of the above embodiment. Second
The figure is a characteristic diagram showing the withstand voltage histogram of the rise in the oxidation of the substrate according to the conventional method, FIG. 3 is the characteristic diagram showing the withstand voltage histogram of the dirt oxide film according to the method of the above embodiment, and FIG. The characteristic diagram shown in Fig. 5 (,
) to (d) are cross-sectional views showing the MOS capacitor manufacturing process according to the second embodiment, FIG. 6 is a characteristic diagram showing the withstand voltage histogram of the dirt oxide film according to the method of the second embodiment, and FIG. ) to (g) are cross-sectional views showing the MOS transistor manufacturing process according to the third embodiment. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... First silicon oxide film, 3... First polycrystalline silicon film, 4... Dirt oxide film, 5... Dirt electrode, 6... Phosphorus Diffusion layer, 7...
・Silicon nitride film (oxidation resistant film), 8... Ion implantation layer, 9... Field oxide film, 10... Second silylan oxide film, 1... Second polycrystalline silicon film , 12
...Third silicon oxide 8tA (dirt oxide film), 1
3...Third polycrystalline silicon film (dart electrode), 14
a * 14 b...source/drain, 15...
・CV D-5in2 film, 16...PSG film, 1
7 ・At wiring film. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (3)

[Claims] (1) Forming a silicon oxide film on the surface of a silicon substrate by thermal oxidation, and forming a polycrystalline silicon film containing the same type of impurity as the main impurity of the silicon substrate at a similar concentration or higher on the silicon oxide film. step and then at 1050°C in an inert gas containing an oxidizing agent at a partial pressure of
] A method for manufacturing a semiconductor device, comprising the following steps: heat-treating the silicon substrate at a high temperature; and then forming a desired element on the silicon substrate. (2) Silicon substrate surface is siliconized by thermal oxidation method. a step of forming a silicon oxide film, and a step of forming a polycrystalline silicon film containing impurities of the same kind as the main impurities of the silicon substrate at a similar concentration or higher on the silicon oxide film;
The temperature was then heated to 1050°C in an inert gas containing an oxidizing agent at a low partial pressure.
] a step of heat-treating the silicon substrate at a high temperature above;
Next, the step of exposing the back surface of the silicon substrate and forming an adjacent diffusion layer with an impurity concentration of IQ19[crn':] or more on the back surface, and then the step of forming a desired element on the silicon substrate. A method for manufacturing a semiconductor device, characterized in that: (3) forming a first silicon oxide film on the surface of the silicon substrate by a thermal oxidation method; a step of forming a polycrystalline silicon film, a step of heat-treating the silicon substrate at a high temperature of 1050 [° C.] or higher in an inert gas containing an oxidizing agent at a low partial pressure, and then a step of forming the first polycrystalline silicon film. a step of forming an oxidation-resistant film on the first silicon oxide film so as to mask an element formation region, and then a step of forming a field oxide film by a thermal oxidation method;
Next, a step of forming a second silicon oxide film and a second polycrystalline silicon film on the surface of the semiconductor substrate after removing the first silicon oxide film and the oxidation-resistant film, and then exposing the back surface of the silicon substrate. A semiconductor characterized by comprising the steps of forming a phosphorus diffusion layer with an impurity concentration of 1019 [z-'] or more on the back surface, and then forming a desired element on the silicon substrate. Method of manufacturing the device.