JPS594012A - Method and apparatus for manufacturing semiconductor device - Google Patents
Method and apparatus for manufacturing semiconductor deviceInfo
- Publication number
- JPS594012A JPS594012A JP11313682A JP11313682A JPS594012A JP S594012 A JPS594012 A JP S594012A JP 11313682 A JP11313682 A JP 11313682A JP 11313682 A JP11313682 A JP 11313682A JP S594012 A JPS594012 A JP S594012A
- Authority
- JP
- Japan
- Prior art keywords
- wafers
- during
- temperature
- wafer
- quartz tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4587—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially vertically
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は半導体装置の製造方法およびその装置、詳しく
は、減圧エピタキシャル成長方法およびその装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and an apparatus thereof, and more particularly to a method of low pressure epitaxial growth and an apparatus thereof.
(2)技術の背景
半導体ウェハ上にシリコン単結晶の薄膜を成長する減圧
エピタキシャル成長(気相成長)方法とそれに用いられ
る装置は知られている。第1図+alには前記装置の配
置が模式的に示され、同図において、■は石英管、2は
ウェハ、3はガス管、4は石英管1を加熱するための高
周波(RF)電源5に接続された加熱用コイル、6はガ
スホンへを収納するボンへホックス、7は流量計等を収
納したガス・コントロール・ボックス、8はロータリポ
ンプ、9はメカニカル・ブースタ・ポンプ、1゜はガス
排出口をそれぞれ示す。ソリコンソースとなるモノシラ
ンガス(S i IIす、ジクロールシランガス(Sj
HzC4z ) 、ドーパントとなるボスフィン/水素
ガス(PII3 / )It) 、塩化水素/水素ガス
(H(J / lh) 、パージガス(N2)等はボン
へボックス6からガス・コン日コール・ボックス7を経
てガス管3の排出口1oがらウェハ2に向けて放出され
、ロークリポンプ8によって矢印に示される方向に1ノ
ド出される。石英管1内は一般に150Torr以−1
・(減圧エビの効果が発生ずる圧力範囲)の圧力に保た
れる。(2) Background of the Technology A low-pressure epitaxial growth (vapor phase growth) method for growing a silicon single crystal thin film on a semiconductor wafer and an apparatus used therefor are known. Figure 1+al schematically shows the arrangement of the device, in which ■ is a quartz tube, 2 is a wafer, 3 is a gas tube, and 4 is a radio frequency (RF) power source for heating the quartz tube 1. 5 is the heating coil connected to it, 6 is the box hook that stores the gas phone, 7 is the gas control box that stores the flow meter, etc., 8 is the rotary pump, 9 is the mechanical booster pump, 1° is Each gas outlet is shown. Monosilane gas (S i II), dichlorosilane gas (Sj
HzC4z), dopant bosphin/hydrogen gas (PII3/)It), hydrogen chloride/hydrogen gas (H(J/lh), purge gas (N2), etc., from Bonge Box 6 to Gas Conn Day Call Box 7. The gas is then discharged from the outlet 1o of the gas pipe 3 toward the wafer 2, and is ejected one nozzle in the direction shown by the arrow by the low-pressure pump 8.
・The pressure is maintained at (the pressure range where the decompression shrimp effect occurs).
第1図(blはウェ゛ハの配置を詳細に示す図で、ウェ
ハ2はSiCコートしたカーボン円板(サセプタ)11
上に置かれ、ガスはガス管3がら図に矢印で示す如くに
送られる。サセプタ11ば図示しない石英ホルダ」二に
置かれる。同図fclはウェハ2の配置を同図(blの
側面から見た図である。FIG. 1 (bl is a diagram showing the arrangement of wafers in detail, wafer 2 is a SiC-coated carbon disk (susceptor) 11
gas is sent through the gas pipe 3 as shown by the arrow in the figure. The susceptor 11 is placed in a quartz holder (not shown). The figure fcl is a view of the arrangement of the wafer 2 seen from the side of the figure (bl).
かかる装置を用い石英管内1を1150℃±50°Cま
で昇温し、約15分程度加熱(プレヒート)シ・その間
ウェハ2の表面を清浄にする目的でIIC!ガスを約1
分間通ず。次いで1000°Cに降温し、5〜20分の
時間をかけてエピタキシャル成長を行わせる。次いで約
5分の時間をかけて降温しエピタキシャル成長工程は終
了する。この経過は第2図の線図に示し、同図において
縦軸は温度(’C)、横軸は時間(分)を表す。Using such a device, the inside of the quartz tube 1 was heated to 1150°C ± 50°C and heated (preheated) for about 15 minutes.During this time, the surface of the wafer 2 was cleaned using IIC! about 1 gas
Lasts for a minute. Next, the temperature is lowered to 1000° C., and epitaxial growth is performed over a period of 5 to 20 minutes. Next, the temperature is lowered over a period of about 5 minutes, and the epitaxial growth process is completed. This progress is shown in the diagram of FIG. 2, in which the vertical axis represents temperature ('C) and the horizontal axis represents time (minutes).
(3)従来技術と問題点
」二記したシリコン単結晶の気相成長において、ウェハ
2とサセプタ11の間の熱伝導−が悪く (特に減圧下
で著しい)、またサセプタ11が完全に均一な温度分布
で加熱されないために、ウェハ内で温度勾配が生じ、ス
リップラインが発生ずる。(3) Prior Art and Problems In the vapor phase growth of silicon single crystals as described in Section 2, heat conduction between the wafer 2 and the susceptor 11 is poor (particularly noticeable under reduced pressure), and the susceptor 11 is completely uniform. Because the wafer is not heated by the temperature distribution, a temperature gradient occurs within the wafer, resulting in slip lines.
前記スリップラインはウェハ上に第3図(alに符号1
2で示されるように発生ずるが、それはシリコン単結晶
層の段差に起因する。同図(blはウェハ表面のシリコ
ン単結晶層の模式的断面図で、シリコン単結晶1*13
aと13bとの間に段差があるとき、シリコン単結晶層
の深さ方向にこスリップライン12が現れる。これは前
記した塩度勾配によりウェハ表面上の温度が不均一で、
この温度の不均一が単結晶シリコンの成長の不均一を、
従ってシリコン単結晶層の表面のi3aと13bに示す
如き段差をもたらすからである。The slip line is placed on the wafer as shown in FIG.
2, which is caused by the step difference in the silicon single crystal layer. The same figure (bl is a schematic cross-sectional view of the silicon single crystal layer on the wafer surface; silicon single crystal 1*13
When there is a step between a and 13b, a slip line 12 appears in the depth direction of the silicon single crystal layer. This is because the temperature on the wafer surface is non-uniform due to the salinity gradient mentioned above.
This temperature non-uniformity causes non-uniform growth of single crystal silicon.
This is because a step difference as shown in i3a and 13b is produced on the surface of the silicon single crystal layer.
かかるスリップライン12上に形成された半導体デバイ
スは不良品となるだけでなく、かがるスリップラインに
沿ってシリコン単結晶が割れることもある。Semiconductor devices formed on such slip lines 12 not only become defective products, but also the silicon single crystal may crack along the slip lines.
(4)発明の目的
本発明は上記従来の問題点に鑑み、半導体ウェハ上に単
結晶シリコンを気相成長する際に、従来技術においてみ
られたスリップラインの発生することなく均一な厚さの
シリコン単結晶層を成長させうる方法と装置を提供する
にある。(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides a method for growing monocrystalline silicon on a semiconductor wafer in a vapor phase, without generating slip lines seen in the prior art. An object of the present invention is to provide a method and apparatus for growing a silicon single crystal layer.
(5)発明の構成
そしてこの目的は本発明によれば、半導体ウェハ表面上
への単結晶シリコンの減圧気相成長(単結晶シリコンの
エピタキシャル成長)方法ニおいて、単結晶シリコン成
長中の石英管内温度が一定している間は隣合うウェハの
間の距離を15闘程度に保ち、これらウェハの間にシリ
コンソースガスが流入し易い状態に保ち、昇温または降
温中ずなわち温度変化の進行中は隣合うウェハの間の距
離を6mm以下に接近せしめる方法と、エピタキシャル
成長用装置において、一方の1つおきのウェハの群は固
定手段上に載置し、他方のウェハの群は可動手段上に配
置し、シリコン単結晶成長中は一方の群のウェハと他方
の群のウェハのそれぞれの間の間隔を15上程度に保つ
如く可動手段を配置し、ウェハに加えられる熱の昇温ま
たは降温中ずなわち温度変化の進行中ば前記可動手段を
動かして一方の群のウェハと他方の群のウェハとのそれ
ぞれの間の間隔が6mm以下に狭める構成とした装置を
提供することによって達成される。しかして、上記装置
における可動手段は、ウェハの配置される石英管の長さ
方向に配置されかつその方向に可動なホルダから成り、
このホルダ上にウェハを支持するサセプタが固定された
手段または一方の群のウェハを載置したサセプタのホル
ダと他方の群のウェハを載置したサセプタを固定したホ
ルダとを開閉2態様をとりうる如く構成し、これらホル
ダが閉じたとき隣合うウェハ相互間の距離は6mm以下
に保たれた状態をとり、またホルダの開いた状態におい
ては隣合うウェハそれぞれの間の距離が15mm程度と
なる如き構成とする。(5) Structure and object of the invention According to the present invention, in a method for low-pressure vapor phase growth (epitaxial growth of single crystal silicon) of single crystal silicon on the surface of a semiconductor wafer, in a quartz tube during growth of single crystal silicon. While the temperature is constant, the distance between adjacent wafers is kept at about 15 mm to allow silicon source gas to easily flow between these wafers, and the temperature changes during heating or cooling. In the method, the distance between adjacent wafers is brought closer to 6 mm or less, and in an epitaxial growth apparatus, one group of every other wafer is placed on a fixed means, and the other group of wafers is placed on a movable means. During silicon single crystal growth, the movable means is arranged so as to maintain a distance of about 15 mm between the wafers in one group and the wafers in the other group, and the movable means is arranged so as to increase or decrease the temperature of the heat applied to the wafers. This is achieved by providing an apparatus configured to move the movable means to reduce the distance between the wafers of one group and the wafers of the other group to 6 mm or less during a temperature change. Ru. Therefore, the movable means in the above device comprises a holder arranged in the length direction of the quartz tube in which the wafer is arranged and movable in that direction,
A means on which a susceptor for supporting wafers is fixed, or a holder for a susceptor on which one group of wafers is placed and a holder on which a susceptor on which wafers from the other group are placed can be opened and closed. When these holders are closed, the distance between adjacent wafers is maintained at 6 mm or less, and when the holders are open, the distance between adjacent wafers is approximately 15 mm. composition.
(6)発明の実施例 以下本発明の実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
前記したスリップラインの原因探求の実験において、本
願の発明者は次の事実を確認した。スリップラインは温
度勾配の不均一によるものであるが、温度勾配の不均一
はウェハの置かれた石英管内の温度の降温中に特に発生
し易く、降温中ウェハの温度は周縁から先に急激に隆)
する。しかし、2枚のウェハが6mmmmトート離で配
置されているときは、互いの輻射熱によって上記したウ
ェハの冷却は発生し帥い。更にウェハを前記6mm以下
の近い距離で配置したとき、両者の間にシリコンソース
ガスを送り込むよう第1図(blに示す構成の装置を用
意しても、単結晶シリコンの十分な成長は得られない。In an experiment to find the cause of the slip line described above, the inventor of the present application confirmed the following fact. Slip lines are caused by non-uniform temperature gradients, and non-uniform temperature gradients are particularly likely to occur when the temperature inside the quartz tube in which the wafer is placed is decreasing. Takashi)
do. However, when two wafers are arranged with a distance of 6 mm mm, the above-mentioned cooling of the wafers does not occur due to mutual radiant heat. Furthermore, when the wafers are placed at a close distance of 6 mm or less, even if an apparatus having the configuration shown in FIG. do not have.
他方、2枚のウェハを15mm程度に離しておくと、成
長温度(1000°C)において単結晶シリコンは満足
すべき状態で成長する。しかし2枚のウェハがこの程度
に離れていると、降温中にウェハの周縁からの冷却があ
り、スリップラインが発生し易い。On the other hand, if the two wafers are separated by about 15 mm, single crystal silicon will grow in a satisfactory state at the growth temperature (1000° C.). However, if the two wafers are separated to this extent, cooling occurs from the periphery of the wafer during cooling, and slip lines are likely to occur.
そこで本発明の方法においては、シリコン成長時すなわ
ちウェハの置かれた石英管内の温度が1000℃である
間は隣合うウェハを15mm程度に拡げておく。2枚の
ウェハが15mm程度に離れていると、降温中には前記
したウェハの周縁からの冷却があるが、この離された状
態はシリコン成長中だけであり、その間石英管内の温度
は1000℃に保たれているからウェハの冷却について
顧慮する必要はない。降温中2枚のウェハの間の距離を
6mm以下にすると、前記した如くにウェハの急激な周
縁からの冷却はウェハ相互間の輻射熱によって防止され
る。所定の膜厚の単結晶シリコン膜は既に成長し終って
いるから、この6mm以下に配置された状態でシリコン
の成長が進まないという事実はなんらの影響も及はさな
い。Therefore, in the method of the present invention, adjacent wafers are spread apart by about 15 mm during silicon growth, that is, while the temperature inside the quartz tube in which the wafers are placed is 1000°C. If the two wafers are separated by about 15 mm, there will be cooling from the periphery of the wafers as described above during cooling, but this separation only occurs during silicon growth, and during that time the temperature inside the quartz tube will remain at 1000°C. There is no need to worry about cooling the wafer. If the distance between the two wafers is set to 6 mm or less during temperature cooling, rapid cooling from the periphery of the wafers is prevented by radiant heat between the wafers, as described above. Since the single-crystal silicon film having a predetermined thickness has already grown, the fact that silicon growth does not proceed in a state where the thickness is less than 6 mm does not have any effect.
第4図には本発明の方法を実施するための装置が模式的
W1面図で示され、同図において、21はイコ英管、2
2はウェハ、23はガス管、24はIiFソース(図示
せず)に接続されたコイルを示し、このガス管に送られ
るシリコンソースガスは排出口3oがら矢印の方向に噴
出される。ウェハ22はサセプタ31」二に第1図(b
lと(C1に示される如く載置される。FIG. 4 shows a schematic W1 side view of an apparatus for carrying out the method of the present invention, in which 21 is an Iconic tube;
2 is a wafer, 23 is a gas pipe, and 24 is a coil connected to an IiF source (not shown), and silicon source gas sent to this gas pipe is ejected in the direction of the arrow from an outlet 3o. The wafer 22 is placed on the susceptor 31'' in Figure 1 (b).
1 and (C1).
シリコンソースガスの供給システム、排気システム等図
示されない他の部分の構成は第1図に示されるものと同
様である。The configuration of other parts not shown, such as a silicon source gas supply system and an exhaust system, is the same as that shown in FIG.
図に見て左から2番目のものから1つおきのサセプタ3
Iは固定ボルダ32上に固定され、固定ホルダ32は不
動である。他力、図に見て最も左のものから1つおきの
サセプタ31aは可動ボルダ32a上に固定され、可動
ボルダ32aは例えば図示しないレール上を滑動可能に
構成し、図示しない適当な駆動手段によって図に見て左
右方向に動きうる。Every other susceptor 3 from the second one from the left in the figure
I is fixed on a fixed boulder 32, and the fixed holder 32 is immovable. By force, every other susceptor 31a from the leftmost one in the figure is fixed on a movable boulder 32a, and the movable boulder 32a is configured to be able to slide, for example, on a rail (not shown), and is driven by an appropriate driving means (not shown). As shown in the figure, it can move left and right.
単結晶シリコン成長中、すなわぢ石英管21内の温度が
1000°Cに保たれている間、サセプタ31と31a
とは、隣合うウェハ22間の距離が15mm程度に保た
れる如く互いに離れた状態にある(第4図(a))。During single crystal silicon growth, that is, while the temperature inside the quartz tube 21 is maintained at 1000°C, the susceptors 31 and 31a
The wafers 22 are separated from each other so that the distance between adjacent wafers 22 is maintained at about 15 mm (FIG. 4(a)).
エピタキシャル成長が終了し石英管21内の温度の降温
が始まるに先立つ一ζ、可動ボルダ32aを図に見て右
方に、互いに隣合うウェハ22の間の距離が6mm以下
になるまで動かず(第4図(b))。この程度に2枚の
ウェハが接近すると、互いの輻射熱によってウェハ22
は温められた状態に保たれるので、従来技術において経
験されたウェハ周縁からの急激な冷却は防止される。Before the epitaxial growth is completed and the temperature inside the quartz tube 21 begins to decrease, the movable boulder 32a moves to the right as seen in the figure and does not move until the distance between the adjacent wafers 22 becomes 6 mm or less. Figure 4(b)). When two wafers come close to each other, the radiant heat from each other causes the wafers to
Since the wafer is kept warm, rapid cooling from the wafer periphery as experienced in the prior art is prevented.
以上には本発明の好ましい実施例について説明したが、
ホルダ32と32aは2本の同心的に配置された軸とし
、外側の軸を可動ホルダ32a、内側の軸を固定ホルダ
32とし、外側の軸が内側の軸上をスライドする構成と
してもよい。Although preferred embodiments of the present invention have been described above,
The holders 32 and 32a may be two concentrically arranged shafts, the outer shaft being the movable holder 32a, the inner shaft being the fixed holder 32, and the outer shaft sliding on the inner shaft.
または以上に代えて、可動ホルダ32aば回転可罷に形
成し、可動ホルダ32が開の状態に回ったときはウェハ
22は第4図fatに示す離れた状態にあり、可動ホル
ダ32aが閉の状態のときウェハ22が第4図(Ill
に示す状態にある如き開閉手段を用いる構成としてもよ
い。かかる装置は石英管に大口径のものを使用しなけれ
ばならないが、サセプタ31゜31aの両側面にウェハ
22を載置しうる利点がある。Or instead of the above, the movable holder 32a is formed to be rotatable, and when the movable holder 32 is rotated to the open state, the wafers 22 are in the separated state shown in FIG. When the wafer 22 is in the state shown in FIG.
It is also possible to use an opening/closing means as shown in FIG. Although such a device requires the use of a quartz tube with a large diameter, it has the advantage that the wafer 22 can be placed on both sides of the susceptor 31.degree. 31a.
第4図fa+から理解される如く、前記した装置におい
てはサセプタの一方側面にしかウェハを載置しえないが
、開閉手段を用いる装置はこの点を改善する。As understood from FIG. 4 fa+, in the above-described apparatus, the wafer can only be placed on one side of the susceptor, but an apparatus using opening/closing means improves this point.
なお上記においては例を降温の場合にとったが、昇温の
場合についても同様であり、本発明の適用範囲は昇温、
降温の双方の場合、すなわち温度変化のある場合に及ぶ
ものである。−(7)発明の効果
以上、詳細に説明したように、本発明の方法と装置によ
るときは従来技術において経験されたスリップラインの
発生が防止され、半導体装置の製造歩留りを改善するだ
けでなく、製品の信頼性を向上させる効果大である。In the above example, the case of temperature decrease is taken, but the same applies to the case of temperature increase, and the scope of the present invention is applicable to temperature increase,
This applies to both cases of temperature drop, that is, cases where there is a temperature change. - (7) Effects of the Invention As explained in detail above, the method and apparatus of the present invention prevents the occurrence of slip lines experienced in the prior art, and not only improves the manufacturing yield of semiconductor devices. , which is highly effective in improving product reliability.
【図面の簡単な説明】
第1図は従来の減圧エピタキシャル成長装置を示す図で
、そのTalは装置の配置を示ず図、そのfblはウェ
ハを載置するサセプタの配置を示す断面図、その(0)
ばTblに示されたサセプタを側面から見た図、第2図
は単結晶シリコン薄膜成長におりる時間と温度の関係を
示す図、第3図はスリップラインを説明するための図で
、その(alばスリップラインの発生したウェハの平面
図、そのfblは単結晶シリコン層のスリップラインに
おける断面図、第4図は本発明の一実施例の模式的断面
図である。
■、11・−・石英管、2.22・−ウェハ、3.23
−ガス管、4.24− コイル、5−11Fソース、6
−ボンベボックス、7−ガス・コントロール・ボックス
、
8−・ロータリホン’7’、9−メカニカル・′ ブー
スタ・ボックス、10.30−ガス排出口、11.31
・−サセプタ、12− スリップライン、13a 、1
3b−単結晶シリコン層表面、32・・−固定ホルダ、
32a−nJ動ホルダ特 許 出願人 富士通株式会
社
=62
第3図
(Q)
(b)[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing a conventional low-pressure epitaxial growth apparatus, in which Tal is a diagram not showing the arrangement of the apparatus, fbl is a cross-sectional view showing the arrangement of a susceptor on which a wafer is placed, and its ( 0)
For example, the susceptor shown in Tbl is viewed from the side, Figure 2 is a diagram showing the relationship between time and temperature during single crystal silicon thin film growth, and Figure 3 is a diagram for explaining slip lines. (Al is a plan view of a wafer where a slip line has occurred, fbl is a cross-sectional view of a single crystal silicon layer at a slip line, and FIG. 4 is a schematic cross-sectional view of an embodiment of the present invention.・Quartz tube, 2.22・-Wafer, 3.23
-Gas pipe, 4.24- Coil, 5-11F source, 6
-Cylinder box, 7-Gas control box, 8-Rotary phone '7', 9-Mechanical booster box, 10.30-Gas outlet, 11.31
・-Susceptor, 12- Slip line, 13a, 1
3b-single crystal silicon layer surface, 32...-fixed holder,
32a-nJ dynamic holder patent Applicant: Fujitsu Ltd. = 62 Figure 3 (Q) (b)
Claims (1)
シャル成長する方法において、単結晶シリコン薄膜成長
中の加熱温度が一定している間は、隣合う前記ウェハの
間隔をほぼ15rr1mに保ち、昇温および降温の温度
変化の進行している間は隣合う前記ウェハの間隔を6m
m以下に保つことを特徴とする半導体装置の製造方法。 (2)石英管、石英管を囲む高周波電源に接続された加
熱用コイル、前記石英管にシリコンソースガス等を供給
し排出するシステムから成り、その上に単結晶シリコン
薄膜が成長される半導体ウニ、ハはサセプタ上に載置さ
れ、前記サセプタはホルダに固定された構成の減圧エピ
タキシャル成長装置にして、前記ウェハの一方の1つお
きの群は固定手段上にまた他方の一つおきの群は可動手
段上に載置され、前記石英管がエピタキシャル成長のた
めの一定温度に保たれている間は一方の群のウェハと(
fll方の群のウェハのそれぞれの間隔−’i: 15
mm程度に保つ如くに可動手段を配置し、前記石英管の
昇温および降温の温度変化の進行している間は前記可動
手段を動かして一方の群のウェハと他方の群のウェハの
それぞれの間隔を6mm以下に狭める構成としたことを
特徴とする半導体装置を製造するための装置。[Claims] In a method for epitaxially growing an o1fi crystal silicon thin film on a semiconductor wafer, while the heating temperature is constant during growth of a single crystal silicon thin film, the interval between adjacent wafers is maintained at approximately 15rr1m, and the While the temperature change is progressing, the distance between adjacent wafers is 6 m.
A method for manufacturing a semiconductor device, characterized in that the temperature is kept below m. (2) A semiconductor urchin consisting of a quartz tube, a heating coil connected to a high-frequency power supply surrounding the quartz tube, and a system for supplying and discharging silicon source gas to the quartz tube, on which a single crystal silicon thin film is grown. , wafers are mounted on a susceptor, and the susceptor is fixed to a holder. placed on a movable means, one group of wafers and (
Spacing between each wafer in the fll group −'i: 15
The movable means is arranged so as to keep the wafers in one group and the wafers in the other group by moving the movable means while the temperature of the quartz tube is increasing and decreasing. An apparatus for manufacturing a semiconductor device, characterized in that the interval is narrowed to 6 mm or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11313682A JPS594012A (en) | 1982-06-30 | 1982-06-30 | Method and apparatus for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11313682A JPS594012A (en) | 1982-06-30 | 1982-06-30 | Method and apparatus for manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS594012A true JPS594012A (en) | 1984-01-10 |
Family
ID=14604461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11313682A Pending JPS594012A (en) | 1982-06-30 | 1982-06-30 | Method and apparatus for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS594012A (en) |
-
1982
- 1982-06-30 JP JP11313682A patent/JPS594012A/en active Pending
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