JPS5939728B2 - Shutter time display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shutter time display device that displays a shutter time on a camera using a light emitting diode or the like. The present invention relates to a shutter time display device having a simple circuit configuration, in which a shutter time display circuit having a shutter time display circuit is controlled based on the output of a common selection drive circuit and the output of a level selection circuit.

Conventionally, many circuits for displaying the shutter time on a camera have been proposed.

As an example, after converting the brightness of the subject into an electrical signal, this electrical signal is logarithmically compressed, and this compressed signal (analog signal) is converted to 1/2000 to 4 of the shutter time.
There is a method that divides up to a second into 14 levels. In this method, a desired level is selected from levels divided into 13 levels using a level selection circuit, and a corresponding light emitting diode or the like is caused to emit light to display a shutter time. However, using the above method to divide a low power supply voltage of about 4 V into 14 voltage levels as in a camera is extremely difficult both from the viewpoint of ensuring the accuracy of the shutter time display and from a technical standpoint.

Further, even if the above-mentioned shutter time display could be realized, the camera would be equipped with an expensive shutter time display. Therefore, the conventional shutter time display was not divided into as many as 14 stages. 1/2000, 1/1000
・・・・・・ Shutter time is displayed in 7 steps with large shutter time intervals, such as 7 steps up to 1/60 and 1/30 seconds, or 1/2000｜11500 up to 1/125'゜゜゜゜02 seconds. It used a means of constructing a circuit.

However, in the former case, a slow shutter time cannot be displayed, and in the latter case, a desired shutter time cannot be displayed.
In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its main purpose is to always maintain the field of view by using a simple structure without using complicated means. To provide a shutter time display device which can accurately display shutter time corresponding to light, has high display resolution, and has many display steps.

Another object of the present invention is to provide a shutter time display device that can accurately display multiple shutter times even with a low voltage power supply.

In order to achieve such an object, the present invention includes a photosensitive element that converts changes in field light into an electrical signal, and a photosensitive element that amplifies and logarithmically compresses the electrical signal obtained by the photosensitive element. The output of this amplifier is input to an amplifier that converts it into a signal corresponding to the data speed and outputs it, and the level of the input signal is compared with a preset reference level. a level selection circuit that outputs a signal from one output terminal and outputs a signal from a second output terminal when the level of the input signal is lower than a reference level; It has a selection drive circuit that sequentially selects and operates the drive circuits and outputs a signal from each output terminal, and a first and second display element group in which a plurality of display elements are arranged, and a corresponding display element in both groups. are connected at one end in common to the corresponding output end of the selection drive circuit,
A shutter time display circuit whose other end is commonly connected to each group and connected to the first and second output ends of the level selection circuit respectively, and a signal from the second output end of the level selection circuit. and a level correction circuit that superimposes a constant voltage on the signal input from the amplifier to the selection drive circuit, so that the display element of the shutter time display circuit can be selected by the outputs of both the selection drive circuit and the level selection circuit. This is what I did.

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing the basic structure of an embodiment of a shutter time display device according to the present invention.

In the figure, PD is a photosensitive element such as a photodiode that converts changes in field light into electrical signals, and AMP is a photosensitive element that amplifies and logarithmically compresses the electrical signal obtained by PD, and adjusts the shutter speed. The SWC, which is an amplifier that converts the output of the amplifier AMP into a signal and sends it out, takes the output of this amplifier AMP as an input, compares the level of the input signal with a preset reference level, and when the level of the input signal is higher than the reference level, the signal is output. A level selection circuit that outputs a signal from one output terminal and outputs a signal from a second output terminal when the level of the input signal is lower than the reference level, and IDV is an amplifier AMP.
This is a selection drive circuit (display driver) which receives the output of the input signal and sequentially selects and operates a plurality of drive circuits according to the level of the input signal and outputs a signal from each output terminal. DISI
, DIS2 each has a plurality of display elements arranged, and the plurality of display elements are connected to a selection drive circuit 1D and a level selection circuit SW.
A shutter time display circuit (hereinafter abbreviated as display circuit) configured to be selected by both outputs and C, and this first display circuit DIS1 displays seven steps from 1/2000 to 1/30 second. The second display circuit DIS2 is a circuit that displays seven stages from 1/15 to 4 seconds, and both circuits are formed from light emitting diodes and the like. LAC is a level correction circuit that superimposes a certain voltage on the signal input from the amplifier AMP to the selection drive circuit IDV based on the signal from the second output terminal of the level selection circuit SWC.
The amplifier AMP is controlled to change the input level of the selection drive circuit DV at any shutter time group selected by comparing a reference level set in advance based on the operation of the WC and the output signal of the amplifier AMP. It is composed of

FIG. 2 is a circuit diagram of an embodiment showing a specific configuration of the present invention.

The parts surrounded by broken lines in FIG. 2 correspond to the parts shown in FIG. 1, and the same reference numerals indicate corresponding parts. Both ends of the photosensitive element PD are connected to the gates of field effect transistors (hereinafter abbreviated as FETs) 11 and 12, and are configured so that the voltage across the photosensitive element PD is always zero.

Here, FET11 and FET12 constitute a differential amplifier, each drain of which is connected to a positive bus line 15 via resistors 13 and 14, respectively, and each source is commonly connected and then connected to a negative bus line via a resistor 16. 17. In addition,
The gate of FETl2 is connected to negative bus 17. The signals appearing at the drains of FETs 11 and 12 constituting the differential amplifier are supplied to the bases of transistors 18 and 19, respectively.
The emitters of the transistors 18 and 19 are connected in common and then connected to the positive bus 15 via a resistor 20, the collector of the transistor 18 is directly connected to the negative bus 17, and the collector of the transistor 19 is connected to the negative bus 17 via a resistor 21. ing.
Further, the collector of this transistor 19 is connected to the gate of the FET 22 and also to the negative bus line 17 via a capacitor 23. And this FET22
The amplified signal is fed back to the gate of FETll via the collector of transistor 24. Further, the drain and source of the FET 22 are connected to the positive and negative bus lines 15 through resistors 25 and 26, respectively.
, 17. Further, the transistor 24
The emitter of is connected to the positive bus 15 via an information voltage source 46. Here, this information voltage source 46 is provided to provide information such as aperture value and film attitude.
The base of the transistor 24 is connected to the level selection circuit S.
Commonly connected to the base of transistor 27 of WC and FE
connected to the drain of T22 and also connected to the drain of transistor 24
, 27 are both connected to the positive bus bar 15.

Here, if the transistor 27 has the same characteristics as the transistor 24, the current 1C2 flowing through the collector of the transistor 27 will be equal to the current 1C1 flowing through the collector of the transistor 24. Further, the collector of the transistor 27 is connected to the negative bus 17 via a resistor 28, and the transistor 27 constituting the differential amplifier
It is connected to the bases of transistors 29 of transistors 9 and 30. The emitters of the transistors 29 and 30 are connected in common and then connected to the negative bus 17 via a resistor 31, and the bases of the transistor 30 are connected to the positive bus 15 and the negative bus 1.
The reference voltage is connected to the midpoint between resistors 33 and 32 connected in series between the resistors 33 and 32, and the reference voltage is obtained from the midpoint of the connection. The collector of the transistor 29 is connected to the base of the transistor 34, and the transistor 34 is turned on only when the base voltage of the transistor 29 becomes higher than the base voltage of the transistor 30. The emitter of this transistor 34 is connected to the positive bus 15, and the collector is connected to the negative bus 1 through a resistor 35.
7 and to the base of a transistor 37 via a resistor 36. The collector of this transistor 37 is connected to the positive bus 15 via a resistor 38, and also to the base of a transistor 39, and is further connected in common to the light emitting diodes D1 to D7 forming the first display circuit DIS1. It is connected to the cathode side, and the emitter of the transistor 37 is directly connected to the negative bus. Further, the emitter of the transistor 39 is connected to the negative bus 17, and the collector is connected to the second display circuit DIS2.
It is connected to the commonly connected cathode side of the light emitting diodes D8 to Dl4 forming the diodes D8 to Dl4. The anode side of each of these light emitting diodes D1 to Dl4 is connected to a selection drive circuit 1VD. In this way, the first and second display circuits DISl and DIS2 have first and second display element groups in which a plurality of light emitting diodes D1 to D7 and light emitting diodes D8 to Dl4 are arranged, and the correspondence between the two groups is as follows. Light emitting diodes Dl, D8, D2, D9...
D7 and Dl4 are commonly connected at one end to form a selection drive circuit 1D.
The other end is connected in common to each group and is connected to the first and second output ends of the level selection circuit SWC, respectively. The cathode sides of the light emitting diodes D8 to Dl4 are connected via a resistor 40 to the bases of transistors 41 and 42 whose bases are commonly connected and to the collector of the transistor 41, which constitute a level correction circuit LAC for input level shifting. .

The emitters of the transistors 41 and 42 are also connected to the positive bus 15, and the collector of the transistor 42 is connected to the source of the FET 22 and the selection drive circuit 1VD.
are connected to the input terminals of each. Next, the operation of the embodiment shown in FIG. 2 will be explained. First, the intensity of the field light is detected by the photosensitive element PD, converted into an electric signal, and applied to the amplifier AMP, and the signal amplified by the amplifier AMP is fed back to the FETll via the transistor 24.

Then, the voltage across the photosensitive element PD is always set to zero volts. Hereinafter, the case where a photodiode is used as the photosensitive element PD will be explained. The characteristics of the photosensitive element (photodiode) PD can be expressed by the following equation. This (1
) In the equation, V is controlled to be exactly 0V, so the equation (1) is set to I-1L.

That is, only 1 L of photocurrent flows through the photodiode PD. This photocurrent L is the transistor 2 of the amplifier AMP.
Since it is equal to the collector current 1C1 of 4, it becomes.

Further, the collector current C1 of the transistor 24 is expressed by the following equation. QVBE In this equation (3), Exp? >> In the V1) region where V1 is 1, the base-emitter voltage VBE is as follows.

VBE Therefore, the drain current of FET22 is 1.

is ID=liver+Va, and the source potential (selection drive circuit D
The input voltage (input voltage) V8 is as shown in the following equation. However, R1 is the resistance value of the resistor 25, R2 is the resistance value of the resistor 26, and 3 is the voltage of the information voltage source 46.

From this equation (5), the source potential V8 is proportional to the logarithm of the photocurrent 1L, and this source potential V5 becomes an input signal to the selection circuit (display driver) IDV.

Note that the signal is amplified as a logarithmically compressed signal depending on the resistance values of the resistors 25 and 26. Further, by varying the voltage Va of the information voltage source 46 corresponding to information such as film sensitivity and aperture, various information can be inserted at the shutter speed.

Since the transistor 27 in the level selection circuit SWC has the same characteristics as the transistor 24 of the amplifier AMP and is configured to be operated with the same bias, the collector current C2 of the transistor 27 is proportional to the photocurrent 1L.

FIG. 3 is a characteristic curve diagram showing the relationship between this photocurrent 1L and shutter time, and this FIG. 3 shows experimental results. The collector current IC2 of this transistor 27 is
flows through resistor 28, and a voltage appears on both sides of this resistor 28. This voltage V1 is the base voltage V2 of the transistor 30.
If compared with V1>V2, shutter speed is 1/3
If the shutter speed is set to be 0 seconds or more, and if V1≦V2, then the shutter speed is set to 1/15 seconds or less, the level selection time 3 is determined depending on the magnitude of voltage 1.
road SWC is activated. That is, if V1>V2, transistors 29 and 37 are turned on, and the first display circuit D
The cathode sides of the light emitting diodes D, -D7 of ISI are electrically connected to the negative bus 17. At this time, since the transistor 39 is off, the second display circuit DIS
Since no current flows through the light emitting diodes D8 to Dl
4 does not emit light. In addition, the level correction circuit LAC
doesn't work either. On the other hand, selection drive circuit (display driver)
The input voltage of the IDV is set to the source voltage of the FET 22, and the selection drive circuit DV has a function of dividing this input voltage into seven levels and selecting the level.

Therefore, the selection drive circuit DV is 1/2000 to 1/3
Select one level up to 0 seconds and light emitting diode D1
- By applying a voltage to one of D7, the shutter time can be displayed.

Figure 4 is a characteristic curve diagram showing the relationship between the input voltage V8 (display driver manual voltage V) of the selection drive circuit DV and the shutter time.As shown in the figure, the shutter time is divided into seven stages, so the voltage at each shutter time interval is The range can be relatively wide.

In addition, in this FIG. 4, A is the first display circuit DIS
B shows the relationship between the display input voltage V8 (display driver input voltage ( )) and shutter time for displaying the second display circuit DIS2, and B is the display input voltage V8 (display driver input voltage () shows the relationship between the shutter time and the shutter time.As is clear from the characteristic curve diagram shown in Fig. 4, the shutter time is 1/
Even if it is 15 seconds or less, the display input voltage V8 is 1/2000
Since it can be set to the same value as seconds, the shutter time can be displayed accurately.

That is, in order to perform this display operation, the voltage V
When 1≦V2, the transistor 37 of the level selection circuit SWC is turned off and the transistor 39 is turned on, so that the light emitting diodes D8 to Dl4 of the second display circuit DIS2 are turned off.
The cathode side of is electrically connected to the negative bus bar 17.

Then, the transistors 41 and 42 of the level correction circuit LAC for input level shifting operate, and a constant current based on the transistor 41 flows to the transistor 42. Since this constant current 1C3 flows through the resistor 26, the voltage across this resistor 26 increases, and the voltage at 1/15 seconds becomes 1/20.
The current 1C3 is set so as to be equal to the display input voltage when displaying 00 seconds (FIG. 4B). In this way, by increasing the display input voltage, extremely accurate display operation can be performed. FIG. 5 shows a specific circuit of the selection drive circuit (display driver) IDV, and the details of the circuit operation are described in Japanese Patent Application No. 48-2326 (Japanese Patent Publication No. 56-30846). be.

In this Fig. 5, LEDl, LED2... are light emitting diodes for displaying shutter time, Q2-1, Q2-
2,... are transistors, R1-1, R1-2...
is a resistor, and E1 is a DC power supply. FIG. 6 is a circuit diagram showing another embodiment of the level correction circuit LAC.

In FIG. 6, the same parts as those in FIG. 2 are given the same reference numerals, and their explanation will be omitted.

The difference from FIG. 2 is that one end of the resistor 26 shown in FIG. The reason is that a voltage power supply circuit is provided.

The base of the transistor 43 is connected to the positive bus 15 via a resistor 44, and the second display circuit DIS
It is connected to the cathode side of the second light emitting diodes D8 to Dl4. 45 is a constant voltage power supply circuit, and the voltage of this constant voltage power supply circuit 45 is such that when the transistor 43 is off, that is, when the shutter time is 1/15 seconds or less, the input voltage of the selection 1 drive circuit DV is as shown in FIG. 4B. It becomes like a characteristic.

Note that the present invention is not limited to the above-described embodiments, and can be modified in various ways without changing the gist.

As explained above, according to the present invention, a shutter time display circuit is divided into two display element groups, a first and a second display element group each having a plurality of display elements arranged, and the display elements of both groups are selectively driven by a drive circuit. and the output of the level selection circuit, and the output obtained by the level selection circuit is input, and the reference level and the output signal of the amplifier are set in advance based on the operation of the level selection circuit. A level correction circuit for input level shift is provided, which controls an amplifier to change the input level of the selection drive circuit at the slow shutter time selected by comparison with the level, and sets the input voltage of the selection drive circuit to the first level. Since the input voltage is set to be equal to the input voltage when driving the shutter time display circuit,
To accurately and reliably display a shutter time even if the shutter time is as slow as 1/15 second or less. Further, according to the present invention, even when a low voltage source is divided into multiple levels as in a camera to correspond to the level of the shutter time display, two display element groups corresponding to the output obtained by the level selection circuit can be used. Since it was divided into 1
It has various excellent effects, such as being able to display shutter time in four or more stages easily and with high precision. Further, a level correction circuit for level shifting is provided, and a selection drive circuit and a level selection circuit for common multiple use of display elements of a shutter time display circuit having first and second display element groups in which a plurality of display elements are arranged. Since the selection is made using both outputs, the number of drive circuits in the selection drive circuit is 1Z, which simplifies the circuit configuration and reduces the cost due to the simplification of the configuration.
This is extremely effective in that the display resolution can be increased and the number of display stages can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of a shutter time display device according to the present invention, FIG. 2 is a circuit diagram showing a specific configuration of an embodiment of the present invention, and FIGS. 3 and 4 are FIG. 2 is a characteristic curve diagram showing the relationship between the photocurrent and shutter time and the relationship between the input voltage of the selection 5 drive circuit and the shutter time for explaining the operation. FIG. A circuit diagram showing an example of a circuit,
FIG. 6 is a circuit diagram showing another example of the level correction circuit in the embodiment of FIG. 2. PD...Photosensitive element, AMP...Amplifier, DV...Selection drive circuit, SWC...
・Level selection circuit, DISl, DIS2... Shutter time display circuit, LAC... Level correction circuit.

Claims (1)

[Claims] 1. A photosensitive element that converts changes in field light into an electrical signal, and an amplifier that amplifies and logarithmically compresses the electrical signal obtained by this photosensitive element, converts it into a signal corresponding to the shutter speed, and sends it out. , the output of this amplifier is input, the level of the input signal is compared with a preset reference level, and when the level of the input signal is higher than the reference level, a signal is output from the first output terminal, and the level of the input signal is a level selection circuit that outputs a signal from a second output terminal when the signal is smaller than a reference level; and a first and second display element group in which a plurality of display elements are arranged, one end of each of the corresponding display elements of both groups is connected in common to the selection drive circuit. a shutter time display circuit, the other end of which is connected in common to each group and connected to the first and second output terminals of the level selection circuit, respectively; a level correction circuit that superimposes a constant voltage on a signal input from the amplifier to the selection drive circuit according to a signal from a second output terminal, and level-sorts the display element of the shutter time display circuit with the selection drive circuit; A shutter time display device characterized in that the shutter time can be selected by both outputs of a circuit.