JPS5939152A - Carrier wave extracting device - Google Patents

Abstract

PURPOSE:To attain stably the extraction of normal carrier wave even if the pulse width of an input information signal is changed continuously, by generating the 2nd pulse train by a gate control signal in a carrier wave extracting device of the BPSK system. CONSTITUTION:A gate control signal generating circuit is constituted so that a gate control signal is generated, in which almost middle point of an input carrier wave period is used as a start point, a gate is inhibited for the 1st time interval smaller than a carrier period T1 and larger than 1/2 of the carrier period T1, the gate release level is obtained for the 2nd time interval T3 smaller than 3/2 of the carrier period T1 from the end of the 1st time interval T2, and the gate is inhibited for the 3rd time interval T4 smaller than the twice of the carrier period T2 from the end point of the 2nd time interval T3. Gate circuits G2, G3 are controlled with this gate control signal (e) to produce the 2nd pulse train, which is led to a frequency phase comparator 9, allowing to extract stably normal carrier wave without producing inversion.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a carrier extraction device in a BPSK (Binary Phase Shift Keying) system.

BACKGROUND ART Conventionally, the BPSK system has been widely used, for example, in pulse communications and when recording binary signal data on magnetic tape. By the way, in this BPSK system, it is necessary to extract a carrier wave synchronized with a transmitted carrier wave from the received signal etc. when demodulating the information signal on the receiving side or for controlling the tape speed.

As such a conventional carrier wave extracting device, there is one that employs a digital method as shown in FIG. 1, for example.

To explain this carrier wave extraction device together with the time chart of each signal shown in FIG. 2, in FIG.
~ (3) d are Nandt gates, and these data type clip flops (2) and four Nando games [3) a ~ (3) d are used to calculate the rise of the signal waveform in the input signal (Fig. 2 (a)). A pulse train generation circuit (4) that generates a pulse train signal having a pulse width equal to the period of the output signal of the voltage-controlled multivibrator, which will be described later, in the up and down directions.
is configured.

(3) e (31f is a Nant gate, (5) is a counter, and (6) is a flip-flop, which is composed of two Nant gates (3) g (3) h. is the stone output of the counter (5) (Fig. 2 (
The output terminal (6) is for outputting 2.
The output signal from a (Figure 2 (to)) is a Nando game) (
31a (respectively cut into 31b. (3) Amount ~ (
3) k is the Nant gate, (7) a and (7) b are the input terminals for the D GATE signal (Fig. 2 (c)) and the Mameoka signal (in the same figure), respectively. It is introduced for 0N10FF operation such as Nant Gate.

(8) is a multivibrator whose free-running frequency is selected to be approximately the same as the clock of the input phase shift keyed wave (BPSIO). Also, code (9) is a frequency phase comparator, CI (Il). is a loop filter, aυ is a voltage-controlled multivibrator (voltage-controlled clock signal oscillator),
Each of these devices (9) to (
One type of PLL (Phase Locked)
I, 00p) is configured. Ripple counter Q
The count number N of 72 is selected to be about 24, whereas the count number N2 of the counter (5) is NJ2.
It is selected so that the relationship is <N2<Nl. The fin is an output terminal and the carrier wave extracted from this terminal Q3 (Fig. 2 (
)) is output.

Then, input terminal (1) is connected to the digital information signal (Fig. 2
When an input signal (Fig. 2 (a)) obtained by phase-shift modulating a carrier pulse at From the output terminal (4) a of the pulse generating circuit (4), the voltage-controlled multivibrator 0υ is output at the rising and falling edges of the signal waveform of the input signal (Fig. 2 (a)) using the method shown in Fig. 2 (c)). A pulse train signal (FIG. 2 (E)) having a pulse width equal to the period of the output clock signal is output. FIG. 2(b) shows the Q terminal output signal of the data type flip-flop (2), which is delayed by one cycle of the output clock signal of the voltage controlled multivibrator aυ with respect to the input signal. Then, when the pulse train signal (Fig. 2 (E)) is output from the pulse generating circuit (4), the NAND game corresponding to this pulse train signal) (
The counter (5) starts counting by the output pulse from 31f (FIG. 2 0)).

The count number N2 of the counter (5) is N1/
2<N2<Nl, and when this count is reached, the pulse output shown in FIG. 2(G) appears at the Q terminal. The output period T2 of this pulse output is T+/2 < 72 < TI with respect to the carrier wave period TI of the input signal.
There is a relationship between Next, the above pulse output (Figure 2 (g))
is latched by the flip-flop (6), and the waveform signal shown in FIG. 2 is output from its output terminal (6) a. Then, this waveform signal (see Fig. 2) is fed back to the pulse generating circuit (4) and controls the Nantes gate (31a (31b) to turn on and off.Thus, this ON @OFF control turns on the counter (5). While the is counting, the output from the pulse generator circuit (4) is prohibited and the output is disabled as shown in Fig. 2 (
The pulse component shown by the dotted line in the middle of the pulse train signal e) does not appear at the output terminal (4)a. 1. Therefore, the pulse train signal output from the NAND game (3) k is as shown in FIG. It is the same as the carrier wave period TI in (a)). And carrier wave period T!
This pulse train signal has the same period as (Figure 2 (S))
is inputted to the frequency phase comparator (9) K, and the phase is compared with the output signal of the ripple counter a in this frequency phase comparator (9). If there is a phase difference as a result of this comparison, the detection output corresponding to this phase difference is guided from the loop filter to the voltage controlled multivibrator Q1), and the repetition frequency of the output clock signal is controlled. Then, the period of the output signal from the ripple counter a, which is output by counting 24 of these output clock signals, is controlled to be the same as the carrier wave period TI of the input signal (Fig. 2 (a)), and the output terminal is (From I3, a carrier synchronized with the input carrier pulse (FIG. 2 0)) is extracted.

However, in the conventional carrier wave extracting device such as , only one counter (5) is equipped, and by selecting that count number as the required count number, the pulse train generation circuit (4
) The pulse train signal (b in Fig. 2 (e)) output from
Only the pulse components during the time interval T2 with the relationship T+/2 < T* < T1 are removed, and the pulse train signal after this removal (Figure 2 (S)) is passed through a frequency phase comparator (
9) to extract the carrier wave (G in Figure 2), when the pulse width of the IW signal is an integral multiple of the input carrier wave period T, as shown in Q0 in Figure 2, A carrier wave (Figure 2 ( ) 0) that is normally synchronized with the input carrier wave is extracted, but as shown in Figure 3, the change point of the information signal is
It coincides with the change point of the carrier wave.
If the timing matches the timing required for the output of
The carrier wave (0 in Fig. 3) which appears in the pulse train signal (Fig. 3 (S)) introduced into the signal and is normally extracted at the timing shown by the cylinder number t1 in Fig. 3 is shown by s t=. In terms of timing (the problem is that the ashing of the FF signal affects the phase of the carrier wave to be extracted, inverting the phase as shown in the figure, and the carrier wave that is accurately synchronized with the input carrier wave pulse cannot be extracted). If the information signal is PwM (pulse width modulated) and its pulse width changes continuously, the change point of the information signal is the change point of the carrier wave as described above. Since there are many cases in which the timing coincides with the timing required for the input of the frequency phase comparator, there is a problem in that it becomes increasingly difficult to extract a normal carrier wave.

Another conventional carrier wave extracting device is a system called a Costas loop that employs an analog system. This system is configured as a type of PLL consisting of a voltage controlled oscillator, a loop filter, a low-pass filter, a phase shifter that shifts the output of the voltage controlled oscillator by 90 degrees, etc. In addition to this configuration, the output of the voltage controlled oscillator and the input The first multiplier multiplies the input signal and the phase shift output of the phase shifter.
and a third multiplier that multiplies both outputs of the first and second multipliers. In this method, the information signal does not need to be synchronized with the input carrier wave (it is possible to extract a normal carrier wave even if the signal is PWMed and its pulse width changes continuously). However, other conventional methods require that the first to third multipliers and the voltage controlled oscillator are DC-coupled, and when integrated circuits are considered, the DC current of nominal jIpI8 is reduced. There was a problem in that it was extremely difficult to eliminate adjustment due to the offset problem.

The object of this invention is to solve the conventional problems as mentioned above.

The present invention will be explained below based on the drawings. FIG. 4 is a diagram showing an embodiment of the present invention, and FIG. +a) to (kl).

It should be noted that equipment and the like in FIG. 4 that are the same or equivalent to those in FIG.

First, to explain the configuration, FF in FIG. 1 is the first data type lip-flop, which converts the pulse width of the input signal (fat in FIG. Clock (J) from control multivibrator αυ
The device quantizes with a period of II I GH
This prevents operation at an unstable signal level near the intermediate value between LOW and LOW. FF is a second data type flip-flop, and Gl is an exclusive OR gate.The second data type flip-flop FF and OR gate GI constitute a pulse train generating circuit. Pulse train generation circuit o! 9 is the period of the clock (j) at the rising edge and falling edge of the signal waveform in the human power signal expansion) (in this example, correctly, the output signal (b) of the first data type flip 70-tube FF1). A first pulse train signal (d) of equal pulse width is generated. 62 to G9 are the second to ninth Nantes gates, and among these, G, G
The first pulse train signal (
d) Introduction 1. A second pulse component controlled by the gate control signal tel and having a pulse component synchronized with the long carrier pulse (a).
A gate circuit is configured to output a pulse train signal (+1). CT is a first BCD (binary) counter, and when the clock signal 01 is counted 15 times as an example, the BCD counter CT outputs the output of the Nant gate Gs to LO.
W, and when counting 22 times, another Nantes gate G
It operates to set the output fjl of o to LOW. FF3
is the third data type flip-flop, FF4 is a flip-flop, and this one is a two-digit NAND game) C7
It is composed of G. CT2 is a second BCD counter, and this second BCD counter CT operates so as to set the output fg) of the Nant gate Gg to f, OW when the clock (j) is counted 11 times, for example.

The above-mentioned first and second QBCD counters CT.

A gate control signal generation circuit that generates a gate control signal tel is configured by CT, flip 70, FF3, FF4s, and NAND gates G4 to G9.

Next, the effect will be explained.

When an input signal (a) obtained by phase-shift modulating a carrier wave pulse using a digital information signal is introduced into the input terminal (1), the first
, a second respective data type flip-flop FF.

From the Q terminal of FF2, a pulse signal fl)l (C1 is output, which is delayed by one period and two periods of the clock (j), respectively, with respect to the input signal (a).Then, both pulse signals (bl)l (C1 is exclusive or game)
At the rising and falling edges of the signal waveform in the input signal (correctly, pulse signal (b)) from the pulse train generation circuit (l!9), the first pulse train with a pulse width equal to the period of A signal (dl) is generated. This first pulse train signal ((1) is generated by two Nant gates G
2 G3, and is controlled by the gate control signal +61 to the second Nant gate G2, and from this gate circuit a second pulse train signal (hl is Output.

This second pulse train signal ('b) is then led to a frequency phase comparator (9), from which a carrier wave (kl) synchronized with the input carrier pulse (al) is extracted from the phase-locked loop, and Second pulse train signal (1
Depending on the output timing of the pulse component being extracted, a problem arises in that the extracted carrier wave (fk) may be inverted. To explain this with the time chart of FIG. 5, the changing points of the information signal in the figure are tl and +2, and the time t
Point 1 is the point at which a carrier wave accurately synchronized with the input carrier pulse (al) can be extracted, and is the desirable generation timing of the pulse component h'. A time lag occurs by the period. However, this degree of time lag has a very small effect on carrier wave extraction, and does not cause problems such as reversing the phase of the extracted carrier wave. Then, at time t2, the second pulse train When a pulse component occurs in the signal (k), it is extracted (4;) This causes a phase inversion in the transmitted wave, causing a problem.In this invention, the gate control signal generation circuit and gate circuits G, G, etc. The problem is solved by acting like this.

That is, when the pulse component h' appears at the time point ta (approximately the midpoint of the input carrier wave period) at the output terminal of the Nant gate G3, this pulse component is sent to the first BCD counter CT and flip-flop FF4 as a resetting/resetting signal. is introduced, the output of flip-flop FF4 is inverted, and its i terminal output (gate control signal) (e) is LOW, that is, the gate prohibition level.
HL was recently moved to the eastern part of the prefecture. One way solution 1 BCD counter C
T starts counting from the reset time, counts 22, and operates to turn the output fi+ of the sixth NAND gate G6 LOW at time point tb after the first time interval T2 has elapsed. Next, this LOW level signal is input as a set signal to the 7-lip flop FF4, and the latch is inverted again so that the gate terminal output (e) becomes the old GH, that is, the gate release level, and the gate circuits G2 and G3 become ready for output. The above first time interval T2 is the input carrier period T as shown in the figure.
The time interval is set to be smaller than 1 and larger than 1/2 p of the carrier wave period TI.

On the other hand, simultaneously with the latch inversion of the flip 70-tube FF, the inverted output of its Q terminal becomes the second BCD counter CT.

This second BCD counter CT2 starts counting, and if no pulse appears from the pulse train generation circuit Q51 during this period, the time point after the second time interval 1.3 from which the 11 counts has elapsed is reached. To tc, set the output (g) of G9 to L
It acts to make it OW. This LOW cuckold g
' passes through the third and fourth NAND games) 03G4, becomes the Norms component h'' and inputs it to the flip-flop FF4 as a reset signal, and its Q terminal output +e+ is set to the gate prohibition level again. 2 time interval T3 is 3 of the carrier wave period T from the end point tb of the first time interval T!
The time interval is set to a time point smaller than /2. Furthermore, the pulse component h" at the time point t is the first
Also input to BCD counter CTI as a reset signal,
This first BCD counter CT is reset, but at this time point tc the third data type flip-flop F
F3 is not cleared, so from time point tc to t (from time point td to 1, after the third time interval 1゛4 has elapsed, which is 6 counts)
When the output of G6 becomes LOW, the latch of the flip 70-tube FF4 is inverted and its Q terminal output (el becomes HIGH, that is, the gate release level again.

The third time interval T4 is set to a time interval from the end point 1c of the second time interval T3 to a time point that is twice the carrier wave period T.

Then, in response to the gate control signal te11 from the gate control signal generation circuit as described above, the gate circuit G! At time t2 from G3, the generation of pulse components in the second pulse train fn+kl is prohibited, and C1 is guided to the frequency phase comparator (9) to extract a normal carrier wave fkl.

As detailed above, according to the present invention, the first time interval T2 is smaller than the carrier wave period T1 and larger than 1/2 of the carrier wave period T, starting from the midpoint of the input carrier wave period #1. becomes the gate prohibition level, and the first time interval T
from the end point of 2 to the second less than 3/2 of the carrier period T1.
Generates a gate control signal that remains at the gate release level for a time interval T3 and then remains at a gate prohibition level for a third time interval T4, which is less than twice the carrier wave period T, from the end point of the second time interval T3. A gate control signal generation circuit is provided, and this gate control signal controls the gate circuit to generate a second pulse train having a pulse component synchronized with the input carrier wave pulse, and guide this to the frequency phase comparator. , without causing any inversion in the extracted carrier wave,
Even if the input information signal is PwM and the pulse width changes continuously, it is possible to stably extract a normal carrier wave.

Furthermore, since it can be constructed from a digital circuit, it can be easily integrated into an integrated circuit and can be used as a nonverbalization circuit.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a conventional carrier wave extraction device.
2(a) to Qυ and 3rd part (a) to Qυ are time charts for explaining the operation of the same device, and FIG. 4 is a block circuit diagram showing an embodiment of the carrier extraction device according to the present invention. , FIG. 5 (al~(kl) is a time chart for explaining the operation of the same embodiment. 1: Input terminal 9: Frequency phase comparator 10; Loop filter 11: Voltage controlled multivibrator (voltage side 1flll
Clock signal oscillator) 12: Ripple counter 13: Output terminal 15: Pulse train generation circuit cT
hCT,: first and second BCD counters FFI to FFs
: Data type flip-flop FF4 : 7 rip 70 lub G+ = exclusive or gate 02 to G9: NAND gate TI = input carrier wave period T2: 1st time interval T3: 2nd time interval T4: 3rd time interval Clarion Co., Ltd. agent Person Ashi 1) Naoe

Claims (1)

[Scope of Claims] A carrier wave extraction device that extracts a carrier wave synchronized with an input carrier wave pulse from an input signal obtained by phase-shift modulating a carrier wave pulse with a digital information signal, the carrier wave extraction device comprising: a rise of a signal waveform in the input signal; and a pulse train generating circuit that generates a first pulse train synchronized with the falling edge, starting from approximately the midpoint of the input carrier wave period, which is smaller than the carrier wave period (T+), and smaller than the carrier wave period (1/2 of TO). The gate prohibition level is not reached for a first time interval (T2) which is greater than the first time interval (T2), and a second time interval (T3) which is less than 3/2 of the carrier wave period (T1) from the end point of the first time interval (1'2). ) becomes the gate release level, and further the second time interval (T
3) a gate control ID generation circuit that generates a gate control signal that is at a prohibition level for a third time interval (T4) smaller than twice the carrier wave period (TI) from the end point of the first pulse train; a gate circuit that is introduced and controlled by the gate control signal to output a second pulse train having a pulse component synchronized with the input carrier pulse; a frequency phase comparator, a loop filter, a voltage controlled clock signal oscillator, and the voltage controlled clock; A counter for counting a required number of clock signals from a signal oscillator is provided, and a carrier wave synchronized with the input carrier wave pulse is output by introducing the second pulse train into the frequency phase comparator and comparing the phase with the output of the counter. A carrier wave extraction device characterized by comprising a phase-locked loop.