JPS593890B2 - synthesizer receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synthesizer receiver, and more particularly to a synthesizer receiver characterized in that a sweep operation is performed by sequentially controlling a counter.

In recent years, the adoption of frequency synthesizer circuits using PLL (phase locked loop) in radio receivers has made it possible to accurately set the receiving frequency and to display the frequency digitally. It is also being considered that multi-functions such as time display can be achieved by using the same circuit as the above circuit.

On the other hand, since it differs greatly from the concept of conventional receivers, the operation and internal circuitry are complicated, and the internal circuitry is difficult to control, especially during the sweep operation.

For example, it has been difficult to selectively sweep between automatic sweep and manual sweep, to automatically start sweep by band switching, and to comprehensively control preset operations during sweep operation.

The present invention eliminates the above-mentioned drawbacks of the conventional circuit by sequentially controlling the counter, thereby realizing the simplification of one circuit.

FIG. 1 is a diagram showing the operation and display panel of a digital display receiver according to an embodiment of the present invention.

1 is a display circuit, and an indicator lamp 2 indicates the sweep direction during sweeping.
For example, if the FM frequency range is 760 to 89.9 KHz, and the AM frequency range is 535 to 1605 KHz, FM is 3 digits and AM
displays the frequency in digits with 4 digits.

4 and 5 are FM and AM buttons, which are used when switching the band from FM to AM or from AM to FM.When the band is switched, the sweep from the lowest frequency of the switched band is automatically started. , the lamp inside the button lights up to display the band.

For example, if you press FM button 4 while receiving AM,
The lamp inside the FM button 4 lights up, and the number display circuit 3 shows 76.
．． 0 is displayed and the upward direction indicator lamp 2 is lit, and the frequency is swept in the higher direction.

Sweeping is also started using the automatic sweep button 6 and the manual sweep button 7, and the former automatically sweeps until a receivable station is selected by sweeping, similar to the sweep when switching bands, and selects the receiving station. When this happens, pause for 5 seconds.

If the sweep stop button 8 is not pressed during the 5 second pause to stop the sweep, the sweep will be restarted and the next receivable station will be selected.

The sweep direction can be freely selected between the high and low frequency directions by selecting either up or down, and is configured to be automatically reversed when the upper or lower limit of the frequency range is reached.

On the other hand, the manual sweep button 7 is composed of a seesaw switch, and is caused to sweep by pressing either of the left or right arrows, but when the pressure is released, the sweeping also stops.

For example, pressing the right arrow will sweep in the direction of higher frequencies, and pressing the left arrow will sweep in the lower frequency direction.

9 is a preset button, and you can select 6 stations from 1 to 6.
It has a lamp inside and is preset to AM.

Select and memorize the FM frequency, turn on the button 9 lamp pressed by pressing button 9, and directly select AM or FM.
Set to the selected frequency.

Reference numeral 10 denotes a memory button, which is used to preset the selected frequency by pressing memory button 10 when a certain frequency is selected and not during sweeping, and then pressing preset button 9. When pressed, the internal lamp lights up, and while the lamp is lit, presetting is possible.

Normally, when presetting multiple stations, the memory button 10 is pressed to enable presetting, and multiple stations are preset by pressing the preset button 9 and selecting by sweeping, and can also be done by switching bands. .

After the preset is completed, press the memory button 10 again to turn off the lamp and leave the preset in a state where it is impossible to preset.
If the preset button 9 is pressed in a state where presetting is not possible, the preset station mentioned above is directly selected.

Reference numeral 11 is a power switch/volume switch, which, together with a tone knob 12, turns the power on and off and adjusts the volume and sound quality.

The above-mentioned FM and AM buttons 4 and 5, memory button 10 and preset button 9 are automatic return push button switches each having a lamp inside. .5, a changeover switch may be used so that when only one of the switches is in the pressed state, the other is always in the released state, so that there is no need to display the pressure using a lamp;
The internal lamp of the preset button 9 may be omitted, and a display using a light emitting diode or the like may be provided near the preset button 9, or the display may be completely unnecessary.

Next, the internal circuit shown in FIG. 1 will be explained using the block diagram shown in FIG. 2.

In the figure, 13 is an antenna, and received radio waves are tuned and amplified via an RF amplifier 14, a mixer 15, and an IF amplifier 16, and converted into audible sound by a detection and low frequency circuit 17.

Reference numeral 20 denotes a synthesizer part that adds a local oscillation frequency to the mixer 15 described above, converts the output of the RF amplifier 14 into an intermediate frequency, and introduces the intermediate frequency into the IF amplifier 16.

The synthesizer part 20 is composed of a PLL (phase locked loop), in which the frequency of the local frequency oscillator 21 is divided by a frequency divider 22 and further divided by a programmable frequency divider 23. The phase comparison circuit 25 compares the phases of the frequency and the reference frequency from the reference frequency oscillator 24, and if there is a phase shift, the local frequency oscillator 21, which is a voltage-controlled oscillator, is controlled by the DC voltage passed through the low-pass filter 26. It adjusts the local oscillation frequency, and since changing the frequency division ratio of the programmable frequency divider 23 changes the local oscillation frequency, variable tuning is performed by changing the frequency division ratio.

For example, if the FM frequency is in the range of 76, 0 to 89.9 MHz and the intermediate frequency is 10.7 MHz, the local oscillation frequency is 653 to 79.2 or 86.7 to 100.6 MHz.
z, but if it is now 65.3 to 79.2 MHz, when the frequency division ratio of the frequency divider 22 is 100, it will be 653 to 792IG (z
L changes.

On the other hand, if the reference frequency is I KHz, the frequency division ratio of the programmable frequency divider 23 will be 653 to 792, and by changing the frequency division ratio by 1 in this range, it will be 76.0 to 89.9.
It is possible to select stations in the MHz range in 100KHz increments.

Also, when the AM frequency is 535 to 1605 KHz and the intermediate frequency is 455 KHz, the local oscillation frequency is 990 to 2
060 KHz, and when compared without going through the frequency divider 22, the reference frequency I. Programmable frequency divider 2
The frequency division ratio of 3 is 990 to 2060, and by changing the frequency division ratio by 1, IIG(
It changes every z, and when the frequency division ratio is changed by 10, it changes every 10KHz.

Reference numeral 30 denotes a counter control section which freely changes the division ratio of the programmable frequency divider 23 to vary the tuning frequency.

Reference numeral 31 denotes a counter, and since the frequency division ratio of the programmable frequency divider 23 is cleared when the frequency is divided, the frequency division ratio is introduced from the counter 31 every time the frequency is divided.

Therefore, by varying the contents of the counter 31, the tuning frequency is indirectly changed.

The contents of the counter 31 are normally varied by 1 in the case of FM and by 10 in the case of AM by the sweep pulse from the sweep circuit 40, and by 100 KHz or 1 at the tuned frequency.
Selected every 0 KHz.

Also, if you press the preset button 9 mentioned above, FM, AM
When the buttons 4 and 5 are pressed, the contents that are always held from the memory circuit 50 are introduced into the counter 31 via the gate 32, and the contents of the counter 31 are changed to new contents.

Counter 3 based on sweep pulses from the sweep circuit 40
1, the determination circuit 60 must determine a count value that corresponds to the upper or lower limit of the frequency and perform control.

For example, in the case of FM, the count value is in the range of 653 to 792, and 1 is sent to the counter 31 during the sweep toward the higher frequency.
When the upper limit of 792 is reached, the counter 31 must be inverted and swept to a lower frequency and subtracted by 1 from the counter 31. When the lower limit of 653 is reached by subtraction, it must be reversed in the same way as above.

A determination circuit 60 determines the upper and lower limits, and is sequence-controlled together with the sweep circuit 40 by a sequence circuit 70 to perform a sweep operation.

The sequence circuit 70 also controls the memory circuit 50, which always stores the contents, by the signal from the input circuit 80, and also instantaneously changes the contents of the counter 31 to new contents via the gate 32.

The input circuit 80 is a circuit that includes the above-mentioned FM and AM buttons 4.5, automatic and manual sweep buttons 6 and 7, a sweep stop button 8, a preset button 9, and a memory button 10. The input circuit 80 is a circuit that stores outputs related to the control of the counter 31. 50 and a sequence circuit 70.

The band switching output of the input circuit 80 is connected to the RF amplifier 14.
, mixer 15, IF amplifier 16, detection and low frequency circuit 1
7, a local frequency oscillator 21 of the synthesizer part 20,
The signal is supplied to the frequency divider 22, and each circuit is switched according to the FM and AM bands.

Further, the received signal from the detection and low frequency circuit 17 is introduced into a sequence circuit 70 to perform a sequence control operation.

Further, the outputs of the counter 31 and the determination circuit 60 are also supplied to the display circuit 1 shown in FIG. 1, and four display circuits are used to indicate the sweep direction and the frequency.

Details of the counter control section 30 will be explained with reference to FIG. 3.

First, the input circuit 80 introduces a button circuit 81 that takes out signals from the FM and AM buttons 4 and 5, automatic and manual sweep buttons 6 and 7, sweep stop button 8, preset button 9, and memory button 10, and the output of the button circuit 81. and a pickup circuit 82 that generates a pickup signal, a band input device 83 that temporarily stores a button signal in response to the pickup signal, a sweep input device 84, a preset input device 85, a memory power device 86, and a stop input device 87. has been done.

When the output of the button circuit 81 is introduced into the timing signal generator 71 of the sequence circuit 70, a timing signal is generated to drive the control circuit 72 and simultaneously drive the pickup circuit 82 to generate a pickup signal.
The button signal is stored in the corresponding input device by the pickup signal.

The timing signal is also introduced into a sweep pulse circuit 41 of the sweep circuit 40 to generate a sweep pulse.

The timing signal generator 71 is driven to 1 by the button signal and is stopped when the button signal disappears and the operation of the control circuit 72 ends.

The memory circuit 50 includes a ROM (read only memory) circuit 51, a RAM (random access memory circuit 52), and a selector 53, and is connected to the power switch 1 in FIG.
The ROM circuit 51 stores the upper and lower limits of the count values for the FM and AM bands in advance in non-volatile memory, so the memory will not be erased even when the power is turned off. It is constantly driven by a power supply together with the RAM circuit 52, and the output of the band input device 83 of the input circuit 80 and the contents stored by the frequency mode circuit 61 of the determination circuit 60 are read out as specified, and are read out via the gate 32. You will be led to counter 31.

The RAM circuit 52 stores six count values and their bands corresponding to the six preset buttons 9 in FIG. R A indicated by the device 85]! The output of the quadband input device 83 of the counter 31 is written to the address position of the vf circuit 52,
If there is no output from the memory power generator 86, the count value at the address position of the RAM circuit 52 designated by the preset input device 85 is supplied to the counter 31.

The band output is supplied to the band input device 83 to change the contents of the counter 31 and the band input device 83.

The selector 53 switches the gate 32 to select the RAM circuit 52.
or output from the ROM circuit 51 to the counter 31
Alternatively, it is supplied to the determination circuit 60, and is configured by a pass-through flip-flop to hold the control signal from the control circuit 72 and switch the gate 32.

The determination circuit 60 includes a circuit 62 that compares the content A of the counter 31 and the numerical value B from the gate 32, and a comparison circuit 6.
2, a circuit 63 for instructing the sweep direction, and a comparison circuit 6
2 indicates the upper and lower limit modes of the frequency, and indicates the sweep direction and the upper and lower limit modes of the frequency,
Before starting sweeping by band switching, the contents of the ROM circuit 51 are selected so that the lower limit of the frequency is introduced into the counter 31, and when the upper limit or lower limit is reached during the sweep, the ROM circuit 51
1 output from the lower limit to the upper limit or from the upper limit to the lower limit.

The sweep circuit 40 includes a circuit 41 that generates a sweep pulse by a timing signal generator 71 of a sequence circuit 70, and a circuit 4 that generates a signal to perform sweep control by a control circuit 72.
27. It consists of an AND gate 43 that takes the AND of the outputs of both circuits 41 and 42, and the counter 31 has a value of 1 in the case of FM.
In the case of AM, ten pulses are intermittently introduced to perform a sweep operation.

The sequence circuit 70 that constitutes the main part of the present invention
consists of a timing signal generator 71 and a control circuit 72, each composed of a large number of flip-flops, and a counter 3.
1. It sequentially controls the rewording circuit 50, judgment circuit 60, and sweep circuit 40 in synchronization with a timing signal, and can select automatic sweep or manual sweep to sweep, or automatically set the lower limit of frequency by band switching. This is to comprehensively control the start of the sweep from and preset operations during the sweep operation.

Next, the operation controlled by the output of the control circuit 72 is
This will be explained using the sequence diagram shown in the figure and the timing diagram shown in FIG.

In FIG. 4, the letters A to C represent the states of a sequence organized by a large number of flip-flops, which are normally in state A, which maintains the receiving state.

In state A, the timing signal generator 71 of the sequence circuit 70 is stopped and no timing signal is generated, so no sequence operation is performed.

When any button is pressed in state A, the timing signal generator 71 is driven by the output from the button circuit 81 of the input circuit 80 in FIG. 3, and the timing signal continues until the state returns to state A. be done.

T1 to T+o in Fig. 5 show specific timing signal waveforms, which occur repeatedly with the TW period as one cycle, and the TW period is usually called a 1-word period. , a clock signal for each word period, that is, a word clock pulse CPW, are simultaneously generated.

Such a timing signal generator 71 is very commonly used in digital computers and is well known, so the details will be omitted.

When the timing signals T1 to T1o and word clock signal CPW are generated, the pickup circuit 82 of the input circuit 80 in FIG. 3 is driven by 1, and when the button signal from the button circuit 81 is stable, the button signal is sent to each input device. to remember.

For example, when the FM button 4 in FIG.
Memory of the M signal is released.

Similarly, when a certain signal is stored in other input devices, the signal storage in the input device is canceled.

If the button is pressed incorrectly, no pickup signal is generated, so no malfunction occurs due to incorrect suppression.

When the pickup signal is generated, the control circuit 72 is driven, and the sequence operation from state P to state C begins.

The control circuit 72 is composed of a large number of flip-flops, and sequentially executes the sequence from states P to C in synchronization with the word cross pulse CPW.

The waveform diagram from P to C in Figure 5 shows an example of this. After the 3-word P state, a long S state (sweep state)
, and in the S state, a relatively long PLL state,
R state for 1 word, W state for 5 seconds, ■D state for word
followed by the state of , and the state of 1 word C.

As shown in Fig. 4, the operation in each state is to set the contents of the counter 31 in the P state, for example, to introduce a count value into the counter 31 using the preset button 9, or by using the band button and sweep button. Before starting the sweep, a count value corresponding to the upper or lower limit of the frequency is introduced into the counter 31.

When the P state ends, in the case of an operation using the preset button 9, the device does not move to the next S state and stays in the A state again.

In the W state described above, the device is in a standby state for 5 seconds and the received content is listened to, so if the received content is forcibly cut off in states other than the W and A states, noise during sweeping can be prevented.

In the above state S, first start from the PLL state,
In the PLL state, for example, approximately 5
It takes 0 milliseconds to stabilize the circuit operation.

Thereafter, it is determined whether radio waves are received at a stable frequency in the R state, and if not, the state moves to the D state without passing through the next W state.

When the message is received, the message is on standby for 5 seconds in the W state, and the user can listen to the message received.

If you wish to continue listening to the current reception frequency, press the stop button 8 to immediately cancel the S state and change to the A state.

If the stop button 8 is not pressed, it moves to the next state D, determines the upper and lower limits of the count value, and if it is not the upper or lower limit, enters the C state and displays the counter 31 with 1 for FM and 10 for AM. Addition and subtraction are performed to perform a substantial sweep operation.

In the case of the upper limit or lower limit, the S state is canceled to stop the sweep, the state returns to the P state, and the same operation as described above is performed from the P state.

Further, when another button is pressed in the S state, the S state is immediately canceled and the state shifts from the T state to the PU state.

For example, pressing another sweep button or switching bands during a sweep will cause a new sequence to occur.

Next, specific sequence operations based on button signals and control of the counter 31 will be described with reference to FIGS. 3 and 4.

First, when the power switch 11 shown in FIG. 1 is turned on, it enters the state A in the sequence shown in FIG.
When the power is turned on, the contents of the button will be displayed, and similarly, if the contents of the band input device 83 of the input circuit 80 disappear, when the power is turned on, either band will be selected. Therefore, the counter 31 and the band input device 83 are either held by a battery regardless of the power switch 11, or are configured with a non-volatile memory so that the contents are always held.

Therefore, even if the pond circuit is turned off when the power is turned off, when the power is turned on again, the counter 31 and the band input device 83
The band and frequency are specified by , and the receiving station before the power was turned off can receive the signal again.

Since the memory circuit 50 in FIG. 3 is also held by a separate power supply like the counter 31 and the band input device 83,
The ROM circuit 51 stores the count values of the upper and lower limits of the band, the RAM circuit 52 stores the count values and bands of six stations, and the selector 53 stores the count values of the upper and lower limits of the band.
Alternatively, which output of the RAM circuit 52 is to be switched by the gate 32 is stored.

For example, before the power is turned off, the RAM circuit 52 outputs an output of -1-3.
2 to the counter 31, that is, even if the preset contents are read by the preset input device 85, when there is no write signal from the control circuit 72, the contents of the counter 31 are the pulses from the sweep circuit 40. It is controlled by the determination signal from the determination circuit 60.

For example, when the FM band is selected in the above state, the first
When the up button of the automatic sweep button 6 shown in the figure is pressed, a timing signal is generated in the state shown in FIG. (In the above case, it is a preset and there is no memory of the sweep), and the sweep in the up direction is memorized.

The control circuit 72 in FIG. 3 is driven by the pickup signal, and the state shifts to state P in FIG. 4.

In state P, the control circuit 72 instructs the sweep direction designation circuit 63 of the determination circuit 60 in the up direction, sets the 1-frequency mode circuit 61 to the upper limit, and at the same time changes the selector 53 to change the gate 32 from the RAM circuit 52 to the ROM circuit 5.
It can be switched to 1.

As a result, the upper limit count value of the FM band of the ROM circuit 51 is guided to the counter 31 via the gate 32 by the band input device 83 and the frequency mode circuit 61, but since there is no write signal from the control circuit 72, the contents of the counter 31 are It doesn't change and remembers a certain count value for the FM band.

Further, the counter 31 is turned up in the sweep direction instruction circuit 63, that is, in an addition state, and the pulse from the sweep circuit 40 enables the addition operation.

Next, the sequence moves to a sweep of the state of S, and the stability of the PLL is measured in the state of the PLL.

Normally, the PLL becomes stable in about 10 milliseconds, but it is better to set it to 40 to 50 milliseconds with some margin.

Since the contents of the counter 31 change and another frequency is selected, it is determined whether radio waves are received in the R state.

When received, a signal is supplied from the received signal input terminal t to the control circuit 72, and the control circuit 72 enters the W state, but when there is no signal, it immediately enters the D state.

In the W state, the system simply waits for 5 seconds, and if the stop button 8 in FIG. 1 is pressed during this time, the S state is canceled and the A state is returned.

When the stop button 8 is not pressed, the upper limit or lower limit is determined in the next D state.

In this case, the content A of the counter 31 added by the comparison circuit 62 of the determination circuit 60 is compared with the upper limit count value B of the FM band of the ROM circuit 51 introduced via the gate 32.

In the case of the upper limit, the condition A=B, so the control circuit 72
The state is released and the state returns to P state.

If it is not the upper limit, the sweep control circuit 42 is driven by the signal from the control circuit 72 in state C, and the sweep pulse circuit 41
When the pulse is led to the counter 31 via the AND gate 43, the contents of the counter 31 are incremented by one.

After the C state, it returns to the PLL state again, and from the PLL to the C state.
The state is repeated until A=B, and after the counter 31 reaches the upper limit, the S state is canceled and the state returns to the P state.

In the case of the upper limit, the state returns to P, and the control circuit 72 gives priority to the condition A=B even if the output of the sweep input device 84 is in the up direction, sets the sweep direction indicating circuit 63 of the determination circuit 60 in the down direction, and controls the counter 31. At the same time, the frequency mode circuit 61 is switched to the lower limit and the ROM circuit 51 is changed to the lower limit count value of FM in step 2-.

After that, the S state sweep operation starts again and the same operation as above is performed until the counter 31 reaches the lower limit.

When the town direction sweep button 6 is pressed during the up direction sweep, the S state is immediately canceled and the state passes through the T and PU states.
The sequence operation is performed again from the P state.

The same procedure is performed when sweeping in the up direction while sweeping in the down direction.

When performing a manual sweep, press the arrow on either the left or right side of the manual sweep button 7 to start it in the same manner as the automatic sweep described above.

The difference is that when the manual sweep button 7 is released, the input circuit 8
Since a release signal is supplied from the zero sweep input device 84 to the control circuit 72, when the release signal is generated, the S state is released, and the counter 31 contents at the time of press release are held and the state is changed to A. .

In other words, this corresponds to the case where the S state is canceled by pressing the stop button 8 during automatic sweeping.

In addition, in the case of the automatic sweep described above, the PLL state is set at 40 to 50 milliseconds, but in the case of manual sweep, the PLL state is changed to a longer period of about 500 milliseconds to about 1 second so that the user can judge the received content. Configure as possible.

In the above case, a manual sweep was performed in the up direction, but a similar operation is performed in a manual sweep in the down direction.

Further, when the manual sweep button 7 is pressed during the automatic sweep, the S state is canceled by the push button signal, and a new sequence starts from the T and PU states, and automatic sweep in the desired direction is started.

Next, a case will be described in which the AM band is selected when a certain station on the FM band is being received in the A state.

By pressing the AM button 5 in FIG. 1, the input circuit 80 in FIG.
is driven, and after the FM storage of the band input device 83 is canceled in the PU state, AM is newly stored.

In the P state of the post-storage sequence, first the sweep direction instructing circuit 63 of the determination circuit 60 is instructed in the down direction, and the frequency mode circuit 61° is set to the lower limit to specify the lower limit of AM of the ROM circuit 51. The gate is switched to the ROM circuit 51 side using .

Next, a write signal is supplied from the control circuit 72 to the counter 31, and the lower limit count value of AM of the ROM circuit 51 is instantaneously written into the counter 31.

Thereafter, the sweep direction indicating circuit 63 is turned upward again, the frequency mode circuit 61 is switched to the upper limit, and the output of the ROM circuit 51 is set to the upper limit count value of AM.

Then, the operation moves to the next S state sweep operation, and after the PLL state, the operation is the same as in the case of automatic sweep.

The same operation as above is performed when switching from the AM band to the FM band.

When a band is switched during an automatic sweep, the band is normally switched and the sweep from the lowest frequency is automatically started by a new sequence, similar to the other sweep operation during the sweep described above.

In the above example, the sweep is performed from the lowest frequency when switching bands, but it is also possible to sweep from the highest frequency.

Next, the preset operation will be described.

When the preset button 9 in FIG. 1 is pressed, the S state ends, the T and PU states occur, and the state shifts to the P state, even during automatic sweeping as in the example described above.

The selector 53 is activated by driving the control circuit 72 in the P state.
switches the gate 32 from the ROM circuit 51 to the RAM circuit 52, and the RAM specified by the preset input device 85
The memory of circuit 52 is led to counter 31.

Next, when a write signal is supplied from the control circuit 72 to the counter 31, the contents of the counter 31 are instantly transferred to the RAM circuit 5.
The count value is changed from 2.

Immediately thereafter, the state returns to state A and the operation ends.

On the other hand, if the content is not stored in the RAM circuit 52, the count value of the receiving station selected by the automatic or manual sweep described above is led to the RAM circuit 52 and stored.

First, when receiving in state A, press memory button 1 in Figure 1.
If you press 0, the memory status will be set in the PU status.
After passing through the states, it returns to state A.

When the preset button 9 is pressed in this state, the write signal from the control circuit 72 is supplied to the RAM circuit 52 in the P state, and the contents of the counter 31 are stored in the corresponding address position of the RAM circuit 52.

Thereafter, when a sweep is performed to select another station and another preset button 9 is pressed, the contents of the counter 31 are stored in another address position of the RAM circuit 52 in the same manner as described above.

By the above operation, the counter 31 is transferred to the RAM circuit 52.
When the presetting operation is completed, the memory button 10 is pressed again to release the memory state.

Sequence control is performed using each of the above states from P to C, and performs selective sweep between automatic sweep and manual sweep, automatic sweep start when switching bands, preset operation during sweep, and comprehensive control of each operation. I can do things.

Next, a specific control circuit 72 that performs the above sequence control
A configuration diagram of the flip-flop is shown in FIG.

In the figure, P1 to P3 are flip-flops corresponding to the states, and S, PLL, R, W, D, and C are also flip-flops corresponding to each state, and are reset first and synchronized with the word clock pulse CPW. Set S, Reset R
Generates a set signal Q or a reset signal Q when there is an input to the signal.

ORI to OR8 are OR gates, A1 to A5 are AND gates, 11 and 12 are impark, 1m1 to Tm3 are timer circuits, respectively, 40 to 50 milliseconds, 0,5 to 1 second, and 5
The input signal is delayed by a period of seconds, and the delayed signal is again synchronized with the word clock pulse CPW in the synchronization circuit at t, to t3.

Also, SW is a switch for automatic sweep and manual sweep.
The S terminal receives an upper limit or lower limit determination output, and the B terminal receives a signal indicating whether or not it has been received.

When a pickup signal is input to the PU terminal, the flip-flops P1 to P3 sequentially generate signals in synchronization with the word clock pulse CPW, and the output of P3, which forms the 3-word signal in the P state in Fig. 5, is sent to the S terminal. When there is a sweep signal, it is transmitted to the set S of S, and at the same time as S is set, the reset signal Q of S is released, and the flip-flops of PLL, R, W, D, and C can be set. is set first.

The PLL set signal Q is transmitted to H by an automatic/manual changeover switch SW via a timer corresponding to the sweep and a synchronization circuit.

The set signal Q of R is transmitted to W or directly by the received signal of the b terminal.

The set signal Q is transmitted to reset R and Pl of S when there is an upper and lower limit signal at the S terminal, and is transmitted to C when there is no signal.

When the signal is transmitted to C, it is guided again to the PLL and performs the same operation as above.

On the other hand, when the reset of S is transmitted to l-R and Pl, S is reset and PLL and R are reset.

W, D, and C are also forcibly reset, but Pl is set again and the same operation as above is performed from Pl.

When S is set, if a manual sweep button release signal or button signal is introduced to the c and d terminals, S is reset and the sequence control ends.

Among the button signals, for signals other than the stop button, a pickup signal is input to the PU terminal again, and the sequence operation starts again from Pl.

In the above example, the timing signal is generated by the button signal,
Although it disappears when sequence control ends, it goes without saying that the timing signal may be generated all the time.

In addition, it is possible not only for AM and FM bands but also for other bands, and the sweep direction is the same not only for reciprocating but also for one-way, and even when the inter-station frequency changes in the AM band, the above-mentioned sweep pulse By changing , not only can the same implementation as described above be possible, but also various changes and improvements can be made based on the gist of the present invention.

In the above example, when the sweep button is operated in the S state,
I am trying to release the S state.

In the case of a button operation unrelated to the sweep of the S state, an operation by suppressing the button can be performed without canceling the S state.

For example, in the case of suppressing a memory button, it is setting and resetting the memory input device, and is not directly related to sweeping. Therefore, without canceling the S state, operate the PU state and create a sequence that disappears after passing through the next P state. , a so-called parallel sequence operation may be performed in which the S state and the S state are generated simultaneously.

The advantage of this parallel sequence operation is that, for example, if the device is configured to double as a time display, switching between the time and frequency display can be performed even while sweeping the S state. You can know the time by switching.

If it also serves as a time display, the display can be effectively utilized by switching the display depending on whether the receiver is on or off.

For example, when the receiver is turned on, you can switch to the time display, and conversely, while the time is being displayed, instead of switching, you can automatically switch from the time display to the frequency display according to the sweep operation of the receiver. It can be configured to always display the time when the machine is off.

As described above, the present invention provides a synthesizer receiver that performs a tuning operation using a frequency divider with a variable frequency division ratio, which includes a counter for setting the frequency division ratio of the frequency divider, and a synchronization of the contents of the counter with a timing signal. By performing sequence control, the sweep operation is greatly simplified, and since the sequence is skipped or interrupted by various signals, a wide variety of button operations are possible. In addition, after taking an appropriate waiting time in the middle of the sequence and first stabilizing the PLL, if there is a station that can be received, a long waiting time is allowed to perform stable reception selection, and then determine the upper and lower limits. Since addition and subtraction of the contents of the counter are performed at the end, it is possible to select even the receiving station at the upper or lower limit.During the sweep, pulses are intermittently added by repeating the sequence, so accurate sweep operation can be performed using the timing signal. In addition, if a timing signal is generated in response to a button signal, and the timing signal also disappears when the sequence ends and the button signal disappears, unnecessary circuits will become inactive during reception, and malfunctions due to noise can be prevented. Furthermore, if only the counter is powered on and maintained at all times, the previous receiving station will be memorized even when the power is turned off, so there is no need to select a station every time the power is turned on, and the timing signal is also supplied to the display circuit. It may also be used as a timing signal for dynamic display, and the circuit of the pond may also be an LSI.
(Large-scale integrated circuit) and miniaturization can be realized.

[Brief explanation of drawings]

FIG. 1 is a display panel diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the internal circuit of FIG. 1, FIG. 3 is a detailed block diagram of the main part of FIG. 3 is a sequence diagram explaining the operation, FIG. 5 is a timing signal waveform diagram, and FIG. 6 is a circuit diagram of a part of FIG. 3. 1 is a display circuit, 4 and 5 are band switching buttons, 6 is an automatic sweep button, 7 is a manual sweep button, 8 is a sweep stop button, 9 is a preset button, 10 is a memory button, 11 is a power volume switch, 1
2 is the tone knob, 13 is the antenna, 14 and 16 are the RF
and IF amplifier, 15 is a mixer, 20 is a synthesizer part, 21 is a local frequency oscillator, 22 is a frequency divider, 23 is a programmable frequency divider, 24 is a reference frequency oscillator, 26 is a low-pass filter, 30 is a counter control section , 31 is a counter, 40 is a sweep circuit, 50 is a memory circuit, 51 is R
OM circuit, 52 is a RAM circuit, 60 is a determination circuit, 70 is a sequence circuit, 71 is a timing signal generator, 72 is a control circuit, and 80 is an input circuit.

Claims (1)

[Claims] 1. A synthesizer receiver that performs a tuning operation using a frequency divider with a variable frequency division ratio, comprising a frequency division ratio setting means for setting the frequency division ratio of the frequency divider, a timing signal generation means, and the timing signal. A synthesizer receiver comprising: sequence means for sequentially controlling the frequency division ratio of the frequency division ratio setting means in synchronization with the timing signal of the generation means.