JPS5937859B2 - power circuit - Google Patents
power circuitInfo
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- JPS5937859B2 JPS5937859B2 JP51110254A JP11025476A JPS5937859B2 JP S5937859 B2 JPS5937859 B2 JP S5937859B2 JP 51110254 A JP51110254 A JP 51110254A JP 11025476 A JP11025476 A JP 11025476A JP S5937859 B2 JPS5937859 B2 JP S5937859B2
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- Prior art keywords
- cmos
- power supply
- voltage
- resistor
- circuit
- Prior art date
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Control Of Electrical Variables (AREA)
Description
【発明の詳細な説明】
本発明は、ＣＭＯＳ−ＩＣ（コンプリメンｌリィＭ０５
集積回路）の電源回路に関するもので、前記ＭＯＳ−Ｉ
Ｃが有するラッチアップ現象を防止するための新規な電
源回路を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a CMOS-IC (Complementary M05
This relates to the power supply circuit of the MOS-I integrated circuit).
The present invention provides a new power supply circuit for preventing the latch-up phenomenon of C.
前記ＣＭＯＳ−ＩＣのラッチアップ現象というのは、正
常動作状態で入力端子又は出力端子に過大な電圧や電流
など力旧功口された場合に、ＣＭＯＳ−ＩＣの電源端子
とアース間に異状電流が流れ、前記の過大な信号がなく
なつてもその異状電流が持続し、電源を〒度遮断し再び
投入しなおさないともとの正常動作はもどらない現象を
いう。The latch-up phenomenon of the CMOS-IC described above occurs when an abnormal current is generated between the power supply terminal of the CMOS-IC and the ground when an excessive voltage or current is applied to the input terminal or output terminal during normal operation. This is a phenomenon in which the abnormal current continues even after the excessive signal is removed, and normal operation cannot be restored unless the power is turned off and then turned on again.
この現象について第６図ａ、ｂ、ｃでさらに詳しく説明
する。This phenomenon will be explained in more detail with reference to FIGS. 6a, b, and c.
前記ＣＭＯＳ−ＩＣの構造は、第６図ａに示すようにＮ
−ＢＵＬＫ上にＰ−ＷＥＬＬが構成され、Ｎ−ＢＵＬＫ
にはｐ＋が拡散されてＰチャンネルを形成し、Ｐ−ＷＥ
ＬＬにはＮ＋が拡散されてＮチャンネルを形成している
。The structure of the CMOS-IC is as shown in FIG.
- P-WELL is configured on BULK, and N-BULK
p+ is diffused into to form a P channel, and P-WE
N+ is diffused into LL to form an N channel.
Ｐ−ＭＯＳとＮ−ＭＯＳのゲート同志は接続されて入力
端子ＩＮとなり、Ｎ−ＢＵＬＫは電源端子ＶＤＤに、Ｐ
−ＷＥＬＬはアースＶｓｓにそれぞれ接続されている。
第６図ａの構成より明らかなようにＣＭＯＳ−ＩＣはＰ
ＮＰＮの４層構造になつており、図のようにＰＮＰトラ
ンジスｉＴ、、Ｔ２およびＮＰＮトランジスタＴ３３Ｔ
４が形成されている。第６図ｂに第６図ａの等価回路を
示すが、今出力端子ＯＵＴに正の過大電圧が印加された
場合について考える。この場合、トランジスタＴ２のエ
ミッタから抵抗に３、抵抗に、を介して電源端子ＶＤＤ
に電流が流れトランジスタＴ２が導通し、その結果ＯＵ
Ｔ−★Ｔ２→に５→に１０→Ｖｓｓの電流経路が形成さ
れ、抵抗に１０に電圧降下が生じる。この抵抗に、Ｏの
電圧降下によりトランジスタＴ４が導通し、ＶＤＤＨｒ
１Ｈｒ７９Ｔ４ＨＶＳＳの電流経路が形成され抵抗に、
にも電圧降下が生じ、この抵抗に、での電圧降下によつ
てトランジスＩＴ、も導通し、さきに生じた抵抗に３Ｏ
の電圧降下を増加するように、ＶＤＤ→Ｔｌ→に４→に
、Ｏ→ｖｓｓの電流経路が形成される。これによつてト
ランジスｌＴ４は導通状態を維持し、抵抗に、の電圧降
下は持続さわ、トランジスタＴ、も導通状態を維持して
、トランジスタＴ３、Ｔ４から成るＰＮＰＮのサイリス
タ構造が導通状態を保持し、出力端子ＯＵＴの過大電圧
を取り除いても電流保持現象は維持されている。The gates of P-MOS and N-MOS are connected to form the input terminal IN, and N-BULK is connected to the power supply terminal VDD, and P-MOS is connected to the input terminal IN.
-WELL are respectively connected to ground Vss.
As is clear from the configuration of Figure 6a, the CMOS-IC has P
It has a four-layer NPN structure, as shown in the figure, PNP transistors iT, , T2 and NPN transistor T33T.
4 is formed. FIG. 6b shows an equivalent circuit of FIG. 6a, and now consider the case where a positive excessive voltage is applied to the output terminal OUT. In this case, the power supply terminal VDD is connected from the emitter of the transistor T2 to the resistor 3 and to the resistor.
A current flows through the transistor T2, and as a result, OU
A current path of T-★T2→5→10→Vss is formed, and a voltage drop occurs across the resistance. Transistor T4 becomes conductive due to the voltage drop across this resistor, and VDDHr
A current path of 1Hr79T4HVSS is formed and the resistor
A voltage drop occurs at the resistor, and due to the voltage drop at the resistor, the transistor IT also becomes conductive, and the previously generated resistor becomes 3O
A current path O→vss is formed from VDD→Tl→4→ so as to increase the voltage drop of . As a result, the transistor T4 maintains the conductive state, the voltage drop across the resistor continues, the transistor T also maintains the conductive state, and the PNPN thyristor structure consisting of the transistors T3 and T4 maintains the conductive state. , the current holding phenomenon is maintained even if the excessive voltage at the output terminal OUT is removed.
この現象からＣＭＯＳ−１Ｃを正常動作にもどすために
は、電源端子Ｖ。In order to restore CMOS-1C to normal operation from this phenomenon, it is necessary to connect the power supply terminal V.
Ｏを一度遮断するか、又は電源端子ＶＤＤから供給され
る電流を保持電流以下に下げなければならない。第６図
ｃにＣＭＯＳ−１Ｃの代表的なＶ。The current supplied from the power supply terminal VDD must be lowered below the holding current. Figure 6c shows a typical V of CMOS-1C.
Ｏ−１００特性を示す。図において、ＶＢＯはブレーク
オーバ電圧、１１［０は保持電流である。ラツチアツプ
現象を防止するために従来行われていた対策としては、
ＣＭＯＳ−１Ｃの入、出力端子１Ｎ，０ＵＴ又は電源端
子ＶＩ］）に過大電圧等のノイズが入らない様に雑音対
策をとる方法が行われていた。Shows O-100 characteristics. In the figure, VBO is the breakover voltage and 11[0 is the holding current. The conventional measures to prevent the latchup phenomenon are as follows:
Noise countermeasures have been taken to prevent noise such as excessive voltage from entering the input/output terminals 1N, 0UT or power supply terminal VI] of the CMOS-1C.
具体的には、１電源端子Ｖ。に直列に抵抗を接続する。
２入、出力端子１Ｎ、０ＵＴとアース間及び入、出力端
子と電源間にそれぞれダイオード等の保護回路を接続す
る。Specifically, 1 power supply terminal V. Connect a resistor in series with .
Connect protection circuits such as diodes between the 2 input and output terminals 1N and 0UT and the ground, and between the input and output terminals and the power supply.
３電源端子とアース間に極当なコンデンサを接続する。3 Connect an appropriate capacitor between the power supply terminal and ground.
等の方法が行われていたが、２の方法は全ての入、出力
端子に保護回路を設けるために構成が複雑でかつ高価で
あり、３の方法では完全な効果は期待できない欠点があ
る。また１の方法はＣＭＯＳ−１Ｃが消費する電流によ
つて、電源端子に直列に接続された抵抗の両端に電圧降
下が生じ、消費電流のバラツキを考えた場合ＣＭＯＳ−
１Ｃの電源電圧。However, method 2 has a complicated and expensive structure because a protection circuit is provided at all input and output terminals, and method 3 has the disadvantage that it cannot be expected to be completely effective. In addition, in method 1, the current consumed by CMOS-1C causes a voltage drop across the resistor connected in series with the power supply terminal.
1C power supply voltage.
ｏが変化することが考えられる。一方、ＣＭＯＳ−１Ｃ
の入力端子１Ｎに供給できる入力電圧レベルは＝般に（
ＶＤＤ＋０．３）Ｖ以下と規定されているため、電源電
圧Ｖ。Ｏが変化することは、他の回路とＣＭＯＳ−１Ｃ
とのインｌフエースを考慮してシステム設計を行う場合
、大きな制約を受けることになる。本発明は、上記従来
例の欠点を除去し、かつＣＭＯＳ−１Ｃのラツチアツブ
現象を防止するための新規な電源回路を提供するもので
ある。It is possible that o changes. On the other hand, CMOS-1C
The input voltage level that can be supplied to the input terminal 1N of is generally (
VDD+0.3)V or less, so the power supply voltage is V. Changing O means that other circuits and CMOS-1C
When designing a system taking into account the interface with the computer, there are significant restrictions. The present invention provides a new power supply circuit that eliminates the drawbacks of the conventional example and prevents the latch-up phenomenon of CMOS-1C.
すなわち、本発明はＣＭＯＳ−１Ｃと他の回路のインタ
フエースを確実に行つた上で、異常状態が生じた場合で
も電源端子。からＣＭＯＳ−ＩＣに供給される電流を保
持電流以下に制限することにより、ＣＭＯＳ−１Ｃのラ
ツチアツプ現象を防止するものである。第１図にその基
本回路を示す。That is, the present invention provides a reliable interface between the CMOS-1C and other circuits, and even if an abnormal state occurs, the power supply terminal can be maintained. By limiting the current supplied to the CMOS-IC from below to the holding current, the latch-up phenomenon of the CMOS-1C is prevented. Figure 1 shows its basic circuit.
図において、１は第１の電圧源、２は抵抗で、前記第１
の電源１とＣＭＯＳ−１Ｃ６の電源端子６−１との間に
挿入され、電圧。In the figure, 1 is a first voltage source, 2 is a resistor, and the first
The voltage is inserted between the power supply 1 of the CMOS-1C6 and the power supply terminal 6-1 of the CMOS-1C6.
をＣＭＯＳ−ＩＣ６に供給する。また抵抗２の電源端子
側端子はダイオード３を介して別の電圧源５に接続され
ている。一方、電圧源５は回路ブロツク７の電源端子７
一１に直接接続されて回路ブロツク１を作勅している。
６−２，７−２はそれぞれＣＭＯＳ−ＩＣ６、回路プロ
ツク７のアース端子、４はＣＭＯＳ−１Ｃ６の電源端子
６−１とアース端子６−２との間に接続されたコンデン
サで低周波フィルタの機能をもつている。is supplied to the CMOS-IC6. Further, the power supply terminal side terminal of the resistor 2 is connected to another voltage source 5 via a diode 3. On the other hand, the voltage source 5 is connected to the power terminal 7 of the circuit block 7.
11 to create circuit block 1.
6-2 and 7-2 are the ground terminals of the CMOS-IC 6 and circuit block 7, respectively, and 4 is a capacitor connected between the power terminal 6-1 and the ground terminal 6-2 of the CMOS-1C6, which serves as a low frequency filter. It has a function.
また６−３，７−３は、それぞれＣＭＯＳ−１Ｃ６、回
路プロツク７の信号入力端子であり、６−４，７−４は
、それぞれ信号出力端子である。この場合回路プロツク
１の出力端子７一４は、ＣＭＯＳ−１Ｃ６の入力端子６
−３に直接接続され、ＣＭＯＳ−１Ｃの出力端子６−４
回路プロツク７の入力端子７一３に直結されている。こ
こで、ラツチアツプ現象を起さないための回路定数とし
て抵抗２の抵抗値について詳細に説明する。Further, 6-3 and 7-3 are signal input terminals of the CMOS-1C6 and circuit block 7, respectively, and 6-4 and 7-4 are signal output terminals, respectively. In this case, the output terminals 7-4 of the circuit block 1 are the input terminals 6 of the CMOS-1C6.
-3 directly connected to output terminal 6-4 of CMOS-1C.
It is directly connected to the input terminals 7-3 of the circuit block 7. Here, the resistance value of the resistor 2 will be explained in detail as a circuit constant for preventing the latch-up phenomenon.
今、第６図ｃにおけるＣＭＯＳ−１Ｃ６の保持電流をＩ
ＨＯ、保持電流１Ｈ０のときの電源端子６−１の電圧を
Ｖ，、正常動作時におけるＣＭＯＳ−１Ｃ６の最大動作
電流をＩ。Now, the holding current of CMOS-1C6 in Fig. 6c is I
HO, the voltage of the power supply terminal 6-1 when the holding current is 1H0 is V, and the maximum operating current of CMOS-1C6 during normal operation is I.
、電圧源１の電圧をＥ，、電圧源５の電圧をＥ２、ダイ
オード３の順方向電圧をＶ。ｌとすると、抵抗２の抵抗
値Ｒは、に選べばよい。, the voltage of voltage source 1 is E, the voltage of voltage source 5 is E2, and the forward voltage of diode 3 is V. 1, the resistance value R of the resistor 2 may be selected as follows.
この場合、正常動作時のＣＭＯＳ一ＩＣ６の電源端子６
−１の電圧Ｖ。Ｏはとなり、回路プロツク７の動作電圧
がＥ，であるから、ＣＭＯＳ−１Ｃ６の入力端子６−３
に入力される信号レベルは、Ｅ２以下であるので、イン
タフェースの点でも問題は生じない。In this case, power supply terminal 6 of CMOS-IC6 during normal operation.
-1 voltage V. Since the operating voltage of the circuit block 7 is E, the input terminal 6-3 of the CMOS-1C6
Since the signal level input to the terminal is equal to or lower than E2, no problem arises in terms of the interface.
なお、回路プロツク７から入力端子６−３に加えられる
入力信号レベルをＣＭＯＳ−１Ｃ６の電源電圧ＶＤＤに
出来るだけ近ずけるには、ダイオード３に、ゲルマニユ
ームダイオードを用いてＶ。ｌの値を低くすれば可能で
ある。第２図、第３図は他の実施例を示すもので、第１
図の基本回路における、抵抗２とダイオード３の接続点
と、ＣＭＯＳ−１Ｃ６の電源端子６−１との間に第２図
の実施例ではダイオード８を挿入し、第３図の実施例で
は、抵抗９を挿入した場合を示す。Incidentally, in order to bring the input signal level applied from the circuit block 7 to the input terminal 6-3 as close as possible to the power supply voltage VDD of the CMOS-1C6, a germanium diode is used as the diode 3. This is possible by reducing the value of l. Figures 2 and 3 show other embodiments.
In the basic circuit shown in the figure, a diode 8 is inserted between the connection point between the resistor 2 and the diode 3 and the power supply terminal 6-1 of the CMOS-1C6 in the embodiment shown in FIG. 2, and in the embodiment shown in FIG. The case where a resistor 9 is inserted is shown.
なお１〜７については、第１図と同一である。第２図の
場合における抵抗２の抵抗値Ｒおよび、電源端子６−１
の正常動作時の電圧Ｖ。Note that 1 to 7 are the same as in FIG. The resistance value R of the resistor 2 and the power supply terminal 6-1 in the case of FIG.
Voltage V during normal operation.
Ｏは、となる・ただし・ＶＤ２は−ダイオード８の順方
向電圧である。４式でＶ。O is the following. However, VD2 is the forward voltage of the -diode 8. V in 4 formulas.
ｌ＝：：ＶＯ２となる様にダイオード３および８を選べ
ば、ＶＯＯ＝Ｅ２となり、ＣＭＯＳ−１Ｃ６の電源電圧
は回路プロツク７の動作電圧と等しくなり、インｌフエ
ースの点でさらに有利である。また第３図の場合におけ
る抵抗２の抵抗値Ｒ、および正常動作時の電源端子６−
１の電圧Ｖ。If diodes 3 and 8 are selected so that l=::VO2, then VOO=E2, and the power supply voltage of CMOS-1C6 becomes equal to the operating voltage of circuit block 7, which is further advantageous in terms of interface. Also, the resistance value R of the resistor 2 in the case of Fig. 3, and the power supply terminal 6- during normal operation.
1 voltage V.
Ｏは、ＶＶ４−ν慮−一Ｖ−υ１となる。O becomes VV4−ν×−1V−υ1.
但しＲ，は抵抗９の抵抗値である。同様′に２ におい
て、Ｒ，ＩＯ＝ＶＯ，になる様にＲ，を選べば、ＶＯＯ
＝Ｅ２となり、第２図の実施例同様インノブニーズの点
で有利である。However, R is the resistance value of the resistor 9. Similarly, in 2, if R is chosen so that R,IO=VO, then VOO
=E2, which is advantageous in terms of in-knob needs, similar to the embodiment shown in FIG.
しかしながらこの場合ＣＭＯＳ−１Ｃの正常動作電流に
、バラツキがあることを考慮すると第２図の方法が有利
である。第４図は、さらに他の実施例で第１図における
抵抗２の代りに定電流回路１０を用いた場合である。However, in this case, considering that there are variations in the normal operating current of CMOS-1C, the method shown in FIG. 2 is advantageous. FIG. 4 shows still another embodiment in which a constant current circuit 10 is used in place of the resistor 2 in FIG.
定電流回路１０の具体回路例は第５図に示すようにＰＮ
Ｐトランジスタ１２と抵抗１１，１３，１４から成つて
おり、１５は第４図の３〜７をまとめて表わした定電流
回路１０の負荷である。A specific circuit example of the constant current circuit 10 is a PN circuit as shown in FIG.
It consists of a P transistor 12 and resistors 11, 13, and 14, and 15 is a load of the constant current circuit 10, which collectively represents 3 to 7 in FIG.
この場合の定電流値１Ｃ０ＮＴはに選べばよい。In this case, the constant current value 1C0NT may be selected as follows.
又、第４図の場合においても第２図、第３図の実施例と
同様に定電流回路１０とダイオード３の接続点と、ＣＭ
ＯＳ−１Ｃ６の電源端子６−１の間に、ダイオード８、
又は抵抗９を挿入すればインタフエースの点で有利にな
ることは明らかである。Also, in the case of FIG. 4, the connection point between the constant current circuit 10 and the diode 3 and the CM
A diode 8,
Alternatively, it is clear that inserting the resistor 9 would be advantageous in terms of interface.
以上説明したように本発明＆丸電圧源１と回路プロツク
１の電圧源５の間に抵抗２又は定電流源回路１０とダイ
オード３を直列に接続し、抵抗２又は定電流源回路１０
とダイオード３の接続点をＣＭＯＳ−１Ｃ６の電源端子
６−１に接続するだけの簡単な回路構成でＣＭＯＳ−１
Ｃ６と回路プロツク７のインタフエースを確実に行い、
さらにＣＭＯＳ−１Ｃの最大の問題であるラツチアツプ
を防止することができる。As explained above, the resistor 2 or the constant current source circuit 10 and the diode 3 are connected in series between the round voltage source 1 and the voltage source 5 of the circuit block 1.
CMOS-1 with a simple circuit configuration that just connects the connection point of diode 3 and diode 3 to the power supply terminal 6-1 of CMOS-1C6.
Ensure the interface between C6 and circuit block 7.
Furthermore, latch-up, which is the biggest problem with CMOS-1C, can be prevented.
第１図は本発明の一実施例における電源回路の回路図、
第２図、第３図、および第４図は本発明の他の実施例を
示す回路図、第５図は第４図における定電流回路の具体
回路図、第６図Ａ，ｄ，ｃ、はＣＭＯＳ−１Ｃの構成お
よびラツチアツブ現象を説明するための等価回路と、特
性図である。
１・・・・・・第１の電圧源、２，９・・・・・・抵抗
、３，８・・・・・・ダイオード、５・・・・・・第２
の電圧源、６・・・・・・ＣＭＯＳ−１Ｃ、７・・・・
・・ＣＭＯＳ−１Ｃとインｌフエースされる回路プロツ
ク。FIG. 1 is a circuit diagram of a power supply circuit in an embodiment of the present invention,
FIGS. 2, 3, and 4 are circuit diagrams showing other embodiments of the present invention, FIG. 5 is a specific circuit diagram of the constant current circuit in FIG. 4, and FIGS. 6A, d, c, These are an equivalent circuit and a characteristic diagram for explaining the configuration of CMOS-1C and the latch-up phenomenon. 1...First voltage source, 2,9...Resistor, 3,8...Diode, 5...Second
voltage source, 6...CMOS-1C, 7...
...Circuit block interfaced with CMOS-1C.
Claims (1)
イオードと、第２の電圧源とを直列接続し、前記インピ
ーダンス素子と第１のダイオードの接続点をＣＭＯＳ−
ＩＣの電源端子に接続したことを特徴とする電源回路。 ２ インピーダンス素子を定電流回路でもつて構成した
ことを特徴とする特許請求の範囲第１項記載の電源回路
。 ３ インピーダンス素子と第１のダイオードの接続点と
、前記ＣＭＯＳ−ＩＣの電源端子との間に第２のダイオ
ード又は抵抗器を挿入したことを特徴とする特許請求の
範囲第１項記載の電源回路。[Claims] 1. A first voltage source, an impedance element, a first diode, and a second voltage source are connected in series, and the connection point between the impedance element and the first diode is connected to a CMOS-
A power supply circuit characterized in that it is connected to a power supply terminal of an IC. 2. The power supply circuit according to claim 1, characterized in that the impedance element is constituted by a constant current circuit. 3. The power supply circuit according to claim 1, characterized in that a second diode or a resistor is inserted between the connection point between the impedance element and the first diode and the power supply terminal of the CMOS-IC. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51110254A JPS5937859B2 (en) | 1976-09-13 | 1976-09-13 | power circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51110254A JPS5937859B2 (en) | 1976-09-13 | 1976-09-13 | power circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5335142A JPS5335142A (en) | 1978-04-01 |
| JPS5937859B2 true JPS5937859B2 (en) | 1984-09-12 |
Family
ID=14531012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51110254A Expired JPS5937859B2 (en) | 1976-09-13 | 1976-09-13 | power circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5937859B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57157557A (en) * | 1981-03-23 | 1982-09-29 | Fujitsu Ltd | Complementary mis integrated circuit |
| JPH01115257U (en) * | 1988-01-28 | 1989-08-03 | ||
| JP2570919B2 (en) * | 1991-04-19 | 1997-01-16 | 株式会社デンソー | Integrated circuit |
-
1976
- 1976-09-13 JP JP51110254A patent/JPS5937859B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5335142A (en) | 1978-04-01 |
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