JPS5936785B2 - Scan-in method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scan concept in fault diagnosis of a general-purpose digital computer, and particularly to an improvement in a scan-in method for scan-in data.

In fault diagnosis of general-purpose digital computers that adopts the scanning concept, a group of flip-flops (registers, counters, etc.) included in the parts to be diagnosed that are addressed in advance are used.
The scan-in data is scanned in bit serially. However, for a group of flip-flops (hereinafter collectively referred to as registers) in which the clock input terminal and reset input terminal are commonly used for each flip-flop,
Scan-in data cannot be scanned into bit serial. Therefore, a method has been adopted in which the scan-in data to these registers is temporarily buffered in a scan-in buffer register that can be scanned in bit-serially, and then the scan-in data is scanned in bit-parallel from this scan-in buffer register to the corresponding register. ing. However, since the scan-in buffer register controls the buffering action for all registers of the part to be diagnosed that cannot be scanned in bit serially, even if the scan-in buffer register is not specified for scan-in, the scan-in data for other registers is is scanned in.

For this reason, even if unique scan data is scanned into the scan-in buffer register in advance, its contents may be destroyed, and in this case, normal simulation whitening cannot be expected. In order to solve this problem, conventionally, the scan-in data specific to the scan-in buffer register is scanned into the scan-in buffer register after the scan-in data to all registers included in the part to be diagnosed is completed. The input order is specified. However, such scan-in ordering functionality requires software assistance and
Furthermore, the conventional method has problems that need to be improved, such as the need for a lot of manual intervention in order to designate the scan-in order for all the parts to be diagnosed that include scan-in buffer registers. It is an object of the present invention to provide a scan-in method that eliminates the problems of the prior art as described above, and is characterized by the fact that during the buffering operation of the scan-in buffer register, the scan-in buffer register is The contents of the buffer register are saved to the save register, and after the buffering operation is completed, the contents saved to the save register are returned to the scan-in buffer register.

Hereinafter, the scan-in method according to the present invention will be specifically explained using one embodiment.

FIG. 1 is a block diagram showing one embodiment of the present invention.

REG-A is a data bus buffer register in normal logic, but during failure diagnosis, it is a register REG-A that cannot be scanned into the bit serial included in the part to be diagnosed.
This register has a shift function and functions as a scan-in buffer register for C (generally a collection of flip-flops, including counters, etc.), and can scan in bit serially. REG
-B is a save register with a shift function. Although there are usually a plurality of registers corresponding to register REG-C, only one is shown for the sake of simplicity. FIG. 2 is a time chart for explaining the operation of FIG. 1.

The scan timing STA is the timing for bit-serial scan-in of the scan-in data into the scan-in buffer register REG-A, and the scan timing STB is the timing for bit-serial scan-in of the scan-in data into the scan-in buffer register REG-A. This is the timing for scanning in from REG-A, and there is a phase difference of half a cycle between the scan timing STB and the scan timing STA. The scan timing STC is the timing when the scan-in data saved from the scan-in buffer register REG-A to the save register REG-B is returned to the scan-in buffer register REG-A. Each time scan-in to register REG-C is completed by STC, one cycle is counted. Now, scan-in buffer register REG-A is a scan-in buffer register for register REG-C, and is also a buffer register for the normal logic data bus.
The scan-in buffer register REG-A itself may be designated as a diagnostic target.

However, if scan-in data is scanned into the scan-in buffer register REG-A and then another register REG-C is executed as the scan-in target, the scan-in data is scanned into the scan-in buffer register REG-A first. The contents scanned in will be destroyed. In order to avoid this inconvenience, the present invention provides a save register REG-B to save and save the contents of the scan-in buffer register REG-A. Scan in buffer register REG-A
The scan-in data targeted for scan-in is scan timing S supplied via OR gate 0R2.
The register REG-A is unconditionally scanned in by TA, but at this time the address REGADRS-A
is enabled and the rescan timing STC is suppressed by the AND gate A3, so the contents of the save register REG-B are transferred to the scan-in buffer register R after the scan-in to the scan-in buffer register REG-A is completed.
It will not be returned to EG-A.

After the above operations are completed, the address REGADRS-C that specifies the register REG-C becomes valid, and the register REG-C becomes valid.
When scan-in to G-C starts, register REG
- The scan-in data targeted at C is sent to the scan-in buffer register RE by the scan timing STA.
Scanned into G-A in bit serial format.

Then, the scan-in data buffered by the scan-in buffer register REG-A is sent to the scan-in timing STB, which is supplied via the AND gate A4 opened by the address REGADRS-C.
is scanned into register REG-C in bit parallel. Also, along with this scan-in operation,
The scan-in data scanned in first to the scan-in buffer register REGA is scanned at scan timing S.
The bits are shifted out one by one by the TA. This shifted out scan-in data is sent to the save register REG via AND gate A1 and OR gate 0R1.
-B, and is shifted into the save register REG-B at scan timing STA. Thus, when the scan-in to the register REG-C is completed, the scan-in data targeted for the scan-in buffer register REG-A is completely saved to the save register REG-B. After that, before the next scan-in operation (a scan-in operation that does not target the scan-in buffer register REG-A) is executed, the contents of the save register REG-B are changed to the scan-in buffer register REG-B by the scan timing STC. An operation to return to A is executed.

In addition, at this time, the scan in buffer register REG
The address REGADRS-A specifying -A is invalid, and the AND gate A3 is open. In this way, the scan-in data targeted at the scan-in buffer register REG-A is always saved after being scanned into the register REG-A.

As described above, in the scan-in method of the present invention, once the scan-in data targeted for the scan-in buffer register is scanned in, the scan-in data is saved by the function of the save register. Therefore, a normal simulation can be expected without considering the scan-in order, and therefore, software support or manual intervention for specifying the scan-in order is unnecessary.

[Brief explanation of the drawing]

1 and 2 are a block diagram and a time chart, respectively, showing an embodiment of the present invention. STA, STB, STC...-Scan timing, REGADRS-A, REGADRS-B, REG
ADRS-C・・・Register specified address, RE
G-A...Scan in buffer register, R
EG-B...Evacuation address, REG-C...
...Registers that cannot be bit-serial scanned in.

Claims (1)

[Claims] 1. When scanning bit-serial scan-in data into one diagnostic target flip-flop group that can be scanned in bit-parallel in the diagnostic section, the scan-in data is transferred to a scan-in buffer register that can be scanned-in bit-serially. At the same time, the scan-in data that was previously scanned into the scan-in buffer register is saved to the save register, and the scan-in data buffered in the scan-in buffer register is transferred to the flip-flop to be diagnosed. A scan-in method characterized in that the contents of the save register are returned to the scan-in buffer register after scanning into a group of buffers in bit parallel.