JPS5936045Y2 - Receiver pulse noise removal circuit - Google Patents

Receiver pulse noise removal circuit

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Publication number
JPS5936045Y2
JPS5936045Y2 JP12455477U JP12455477U JPS5936045Y2 JP S5936045 Y2 JPS5936045 Y2 JP S5936045Y2 JP 12455477 U JP12455477 U JP 12455477U JP 12455477 U JP12455477 U JP 12455477U JP S5936045 Y2 JPS5936045 Y2 JP S5936045Y2
Authority
JP
Japan
Prior art keywords
amplitude
pulse noise
circuit
voltage
noise removal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12455477U
Other languages
Japanese (ja)
Other versions
JPS5449807U (en
Inventor
浩司 三宅
幸広 川本
敏文 伊東
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP12455477U priority Critical patent/JPS5936045Y2/en
Publication of JPS5449807U publication Critical patent/JPS5449807U/ja
Application granted granted Critical
Publication of JPS5936045Y2 publication Critical patent/JPS5936045Y2/en
Expired legal-status Critical Current

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  • Noise Elimination (AREA)

Description

【考案の詳細な説明】 本考案は受信機、殊にAM受信機のパルス性゛ノイズ除
去回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse noise removal circuit for a receiver, particularly an AM receiver.

第1図は従来のAM受信機〔例えば市民バンドCB)ラ
ンシーバーの受信機部〕のパルス性ノイズ除去回路を示
す回路図で、1は中間周波トランス、Dl、C1は検波
回路2を構成する検波ダイオード、及びバイパスコンデ
ンサ、3は自動利得制御(AGC)信号伝送線路、D2
は検波出力からパルス性ノイズを除去するための振幅制
限用ダイオード、R1−R6は夫々電源電圧+VB0及
びリバースAGC電圧を前記ダイオードにバイアス電圧
として印加するためのバイアス抵抗で、該バイアス抵抗
にてパルス性ノイズを除去するための設定電圧、即ち検
波出力の振幅を制限する設定電圧(以下検波出力の振幅
制限設定電圧と称す)を定めている。
FIG. 1 is a circuit diagram showing a pulse noise removal circuit of a conventional AM receiver (for example, the receiver section of a citizen's band CB) transceiver. Diode and bypass capacitor, 3 is automatic gain control (AGC) signal transmission line, D2
is an amplitude limiting diode for removing pulse noise from the detection output, and R1-R6 are bias resistors for applying the power supply voltage +VB0 and reverse AGC voltage as bias voltages to the diodes, respectively. A set voltage for removing natural noise, that is, a set voltage for limiting the amplitude of the detected output (hereinafter referred to as an amplitude limiting set voltage for the detected output) is determined.

C2は電解コンデ゛ンサ、4は音声信号出力端子である
C2 is an electrolytic capacitor, and 4 is an audio signal output terminal.

第1図の回路に於いて、中間周波トランス1の同調コイ
ルLで得られた信号は、検波ダイオードD1で負検波さ
れ、バイパスコンデンサC1により高周波成分は側路さ
れ、音声信号成分のみが音声信号出力端子4側へ伝送さ
れる。
In the circuit shown in Fig. 1, the signal obtained by the tuning coil L of the intermediate frequency transformer 1 is negatively detected by the detection diode D1, the high frequency component is bypassed by the bypass capacitor C1, and only the audio signal component becomes the audio signal. It is transmitted to the output terminal 4 side.

ところでスイッチング動作する振幅制限用ダイオードD
2は、バイアス抵抗R1〜R6により通常順方向電流が
流れるように設定され、ON状態になっている。
By the way, the amplitude limiting diode D that performs switching operation
2 is set so that a forward current normally flows through bias resistors R1 to R6, and is in an ON state.

しかし検波後の出力電圧は負であり、更にパルス性ノイ
ズが入って検波出力電圧が下がると、ダイオードD2の
アノード側の電圧が下がり、パルス性ノイズが入った期
間のみ該ダイオードはOFF状態になる。
However, the output voltage after detection is negative, and when pulse noise enters and the detection output voltage decreases, the voltage on the anode side of diode D2 decreases, and the diode becomes OFF only during the period when pulse noise occurs. .

従ってパルス性ノイズ戊分は、抵抗R2及び電解コンデ
ンサC2を通ってアースに流される。
Therefore, the pulsed noise component is passed through the resistor R2 and the electrolytic capacitor C2 to ground.

然しなから第1図のような従来のノイズ除去回路であれ
ば、検波出力からパルス性ノイズを除去するための検波
出力の振幅制限設定電圧vLは、第2図イ9口に示す様
に入力電界強度に対してほとんど一定である。
However, in the case of a conventional noise removal circuit as shown in Fig. 1, the amplitude limit setting voltage vL of the detection output for removing pulse noise from the detection output is inputted as shown in Figure 2, A9. It is almost constant with respect to electric field strength.

従って検波出力の振幅制限設定電圧が低い場合には、大
入力信号を受信したとき音声信号の一部をも除去して歪
率を悪化させることになり、文運に検波出力の振幅制限
設定電圧が高い場合には、小人力信号受信時第2図イに
示す様にパルス性ノイズNを殆んど除去することが出来
なくなる等の欠点があった。
Therefore, if the amplitude limit setting voltage of the detection output is low, when a large input signal is received, part of the audio signal will be removed, worsening the distortion rate, and the amplitude limit setting voltage of the detection output If this is high, there is a drawback that it becomes almost impossible to remove the pulse noise N when receiving a small human power signal, as shown in FIG. 2A.

本考案は斯る点に鑑み、入力信号レベルの増幅に伴なっ
て、検波出力の振幅制限設定電圧を変化させることによ
り、上述の欠点を解消せんとするもので、以下CB)ラ
ンシーバーに用いた本考案の一実施例を第3図に従い説
明する。
In view of this, the present invention attempts to eliminate the above-mentioned drawbacks by changing the amplitude limit setting voltage of the detection output as the input signal level is amplified. An embodiment of the present invention will be described with reference to FIG.

尚第3図に於いて、第1図と同一部品については第1図
と同一の図番を用いることにする。
In FIG. 3, the same numbers as in FIG. 1 are used for the same parts as in FIG. 1.

第3図の回路では、検波ダイオードD1の出力端子(ア
ノード)と、振幅制限用ダイオードD2の入力端子(ア
ノード)との間に位相反転用のトランジスタQを設け、
検波ダイオードD1の出力側から得られる自動利得制御
電圧(例えばリバースAGC電圧)の極性を前記トラン
ジスタQにて反転し、極性が反転されたこの電圧(例え
ばフォワードAGC電圧)を抵抗R7を介して振幅制限
用ダイオードD2の入力端子(アノード)にバイアス電
圧として印加する様にしている。
In the circuit shown in FIG. 3, a phase inversion transistor Q is provided between the output terminal (anode) of the detection diode D1 and the input terminal (anode) of the amplitude limiting diode D2.
The polarity of the automatic gain control voltage (e.g., reverse AGC voltage) obtained from the output side of the detection diode D1 is inverted by the transistor Q, and the amplitude of this voltage (e.g., forward AGC voltage) with the inverted polarity is passed through the resistor R7. A bias voltage is applied to the input terminal (anode) of the limiting diode D2.

斯様に構成した回路に於いて、前述の位相反転増幅され
たAGC電圧は人力電界強度に応じて高くなるため、入
力信号レベルが増大すればそれに比例して振幅制限用ダ
イオードD2のアノードに印加される順方向のバイアス
電圧は高くなる為、ダイオードD2の内部インピーダン
スが減少し、パルス性雑音を除去するための検波出力の
振幅制限設定電圧■L′が高くなる。
In the circuit configured in this manner, the phase-inverted and amplified AGC voltage described above increases in accordance with the strength of the human electric field, so as the input signal level increases, it is applied to the anode of the amplitude limiting diode D2 in proportion to the increase in the input signal level. Since the forward bias voltage applied becomes higher, the internal impedance of the diode D2 decreases, and the amplitude limit setting voltage L' of the detection output for removing pulse noise becomes higher.

〔第4図口〕。従って大入力信号受信時(強電界時)音
声信号の一部が振幅制限されて歪率が悪化するというよ
うな懸念がなくなる。
[Figure 4 entrance]. Therefore, when receiving a large input signal (during a strong electric field), there is no concern that part of the audio signal will be amplitude-limited and the distortion rate will deteriorate.

逆に入力信号レベルが減少すれば、振幅制限用ダイオー
ドD2のアノードに印加される順方向のバイアス電圧は
低くなる為、ダイオードD2の内部インピーダンスが増
大し、検波出力の振幅制限設定電圧VL′が低くなる。
Conversely, if the input signal level decreases, the forward bias voltage applied to the anode of the amplitude-limiting diode D2 will decrease, so the internal impedance of the diode D2 will increase, and the amplitude-limiting setting voltage VL' of the detection output will decrease. It gets lower.

〔第4図イ〕。従って小入力信号受信時(弱電界時)で
もパルス性ノイズを除去する効果を充分果たすことが出
来る。
[Figure 4 A]. Therefore, even when receiving a small input signal (weak electric field), the effect of removing pulse noise can be sufficiently achieved.

尚第5図は入力電界強度対検波出力の振幅制限設定電圧
の関係を示す図で、曲線Aが第1図の従来回路を用いた
場合、曲線Bが第3図の本考案回路を用いた場合の特性
を夫々示している。
Fig. 5 is a diagram showing the relationship between the input electric field strength and the amplitude limit setting voltage of the detection output, where curve A is when the conventional circuit shown in Fig. 1 is used, and curve B is when the inventive circuit shown in Fig. 3 is used. The characteristics of each case are shown.

第5図から明らかな様に検波出力の振幅制限設定電圧は
第1図の回路では入力電界強度に対して略一定であるの
に対し、第3図の回路では入力限界強度に伴なって大き
く変化していることが判る。
As is clear from Figure 5, the amplitude limit setting voltage of the detection output is approximately constant with respect to the input electric field strength in the circuit of Figure 1, whereas in the circuit of Figure 3 it increases as the input limit strength increases. It turns out that things are changing.

以上の様に本考案に係る受信機のパルス性ノイズ除去回
路に依れば、検波回路から得られるAGC電圧を増幅す
る増幅手段を設け、この増幅手段の出力電圧を振幅制限
用ダイオードに印加して人力信号の増大に伴なって振幅
制限用ダイオードの内部インピーダンスを減少させるこ
とにより小入力信号受信時におけるノイズ除去と大入力
信号受信時における歪率悪化の防止をなすようにしたの
で、大入力信号受信時音声信号の一部が振幅制限されて
除去され歪率が悪化するというような懸念がなくなると
共に小入力信号受信時でもパルス性ノイズを除去する効
果が非常によくなる。
As described above, according to the pulse noise removal circuit for a receiver according to the present invention, an amplification means for amplifying the AGC voltage obtained from the detection circuit is provided, and the output voltage of this amplification means is applied to the amplitude limiting diode. By reducing the internal impedance of the amplitude limiting diode as the human input signal increases, noise is removed when receiving small input signals and prevention of deterioration of distortion rate when receiving large input signals is achieved. There is no concern that part of the audio signal will be amplitude-limited and removed during signal reception and the distortion rate will worsen, and the effect of removing pulse noise is very good even when receiving a small input signal.

又、回路設計の自由度を増すことが出来る。Furthermore, the degree of freedom in circuit design can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の受信機のパルス性ノイズ除去回路を示す
回路図、第2図イ5口は第1図の回路を用いた場合の弱
電界入力時及び強電界入力時に於ける入力信号波形と検
波出力の振幅制限設定電圧を示す図、第3図は本考案に
係る受信機のパルス性ノイズ除去回路を示す回路図、第
4図イ9口は第3図の回路を用いた場合の弱電界入力時
及び強電界入力時に於ける入力信号波形と検波出力の振
幅制限設定電圧を示す図、第5図は入力電界強度対検波
出力の振幅制限設定電圧の関係を従来回路と本考案回路
とで比較して示す図である。 2・・・・・・検波同図、D2・・・・・・振幅制限用
ダイオード、Q・・・・・・位相反転用トランジスタ。
Figure 1 is a circuit diagram showing a pulse noise removal circuit of a conventional receiver, and Figure 2 (a) shows the input signal waveforms when the circuit in Figure 1 is used when a weak electric field is input and when a strong electric field is input. Figure 3 is a circuit diagram showing the pulse noise removal circuit of the receiver according to the present invention. A diagram showing the input signal waveform and the amplitude limit setting voltage of the detection output when a weak electric field is input and a strong electric field is input. Figure 5 shows the relationship between the input electric field strength and the amplitude limit setting voltage of the detection output in the conventional circuit and the inventive circuit. FIG. 2...Detection same figure, D2...Diode for amplitude limiting, Q...Transistor for phase inversion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 検波回路の出力側に、検波出力からパルス性ノイズを除
去するための振幅制限用ダイオードを設けた受信機に於
いて、前記検波回路から得られるAGC電圧を増幅する
増幅手段を設け、この増幅手段の出力電圧を前記振幅制
限用ダイオードに印加して入力信号の増大に伴なって前
記振幅制限用ダイオードの内部インピーダンスを減少さ
せることにより、小入力信号受信時におけるノイズ除去
と大入力信号受信時における歪率悪化の防止をなすよう
にした受信機のパルス性ノイズ除去回路。
In a receiver including an amplitude limiting diode for removing pulse noise from the detection output on the output side of the detection circuit, an amplification means for amplifying the AGC voltage obtained from the detection circuit is provided, and the amplification means is applied to the amplitude-limiting diode to reduce the internal impedance of the amplitude-limiting diode as the input signal increases. A receiver pulse noise removal circuit that prevents deterioration of distortion rate.
JP12455477U 1977-09-12 1977-09-12 Receiver pulse noise removal circuit Expired JPS5936045Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12455477U JPS5936045Y2 (en) 1977-09-12 1977-09-12 Receiver pulse noise removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12455477U JPS5936045Y2 (en) 1977-09-12 1977-09-12 Receiver pulse noise removal circuit

Publications (2)

Publication Number Publication Date
JPS5449807U JPS5449807U (en) 1979-04-06
JPS5936045Y2 true JPS5936045Y2 (en) 1984-10-04

Family

ID=29084657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12455477U Expired JPS5936045Y2 (en) 1977-09-12 1977-09-12 Receiver pulse noise removal circuit

Country Status (1)

Country Link
JP (1) JPS5936045Y2 (en)

Also Published As

Publication number Publication date
JPS5449807U (en) 1979-04-06

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