JPS628568Y2 - - Google Patents

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Publication number
JPS628568Y2
JPS628568Y2 JP8018178U JP8018178U JPS628568Y2 JP S628568 Y2 JPS628568 Y2 JP S628568Y2 JP 8018178 U JP8018178 U JP 8018178U JP 8018178 U JP8018178 U JP 8018178U JP S628568 Y2 JPS628568 Y2 JP S628568Y2
Authority
JP
Japan
Prior art keywords
load
circuit
detection
detection circuit
anl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8018178U
Other languages
Japanese (ja)
Other versions
JPS54180654U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8018178U priority Critical patent/JPS628568Y2/ja
Publication of JPS54180654U publication Critical patent/JPS54180654U/ja
Application granted granted Critical
Publication of JPS628568Y2 publication Critical patent/JPS628568Y2/ja
Expired legal-status Critical Current

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  • Noise Elimination (AREA)

Description

【考案の詳細な説明】 本考案は検波出力に含まれるノイズを除去する
ための自動ノイズミツター回路(以下(ANL回
路と称す)を備えたAM受信機例えば市民バンド
CBトランシーバーの検波回路に関するものであ
る。
[Detailed description of the invention] This invention is an AM receiver equipped with an automatic noise limiter circuit (hereinafter referred to as ANL circuit) for removing noise contained in the detection output.
This relates to the detection circuit of a CB transceiver.

ANL回路を具備したCBトランシーバーの検波
回路として従来第1図に示す回路が知られてい
た。D1は検波用ダイオード、はANL回路であ
る。
The circuit shown in FIG. 1 has been known as a detection circuit for a CB transceiver equipped with an ANL circuit. D1 is a detection diode, and D1 is an ANL circuit.

第1図の回路に於いて、中間周波信号は、検波
用ダイオードD1で負検波され、負荷容量C1によ
り高周波成分は側路され、音声信号成分のみが音
声信号出力端子(検波出力端子)側へ伝送され
る。ところで、スイツチング動作するANL回路
の振幅制限用ダイオードは、ANL SW ON
時、バイアス抵抗により通常順方向電流が流れる
ように設定され、ON状態になつている。しか
し、検波後の出力電圧は負であり、更にパルス性
ノイズが入つて検波出力電圧が下がると、ダイオ
ードのアノード側の電圧が下がり、パルス性ノイ
ズが入つた期間のみ該ダイオードはOFF状態に
なる。従つて、パルスノイズ成分は、ANL回路
の抵抗及び電解コンデンサを通つてアースに流
される。斯様にしてノイズ除去動作は達成され
る。
In the circuit shown in Figure 1, the intermediate frequency signal is negatively detected by the detection diode D1 , the high frequency component is bypassed by the load capacitor C1 , and only the audio signal component is sent to the audio signal output terminal (detection output terminal). transmitted to the side. By the way, the ANL circuit that performs switching
1 amplitude limiting diode is ANL SW ON
Normally, the bias resistor is set so that a forward current flows, and the switch is in the ON state. However, the output voltage after detection is negative, and when pulse noise enters and the detection output voltage decreases, the voltage on the anode side of the diode decreases, and the diode becomes OFF only during the period when pulse noise enters. . Therefore, the pulse noise component is
1 resistor and an electrolytic capacitor to ground. In this way the noise removal operation is achieved.

然し乍ら、第1図の様な回路の場合、下記の様
な欠点があつた。
However, the circuit shown in FIG. 1 has the following drawbacks.

(a) 検波段の直流電流をIDC、直流抵抗をR、交
流電流をIAC、交流抵抗を|Z|とすると、変
調度mはm=IAC・|Z|/IDC・Rと表わすこと
が出来、一 般にR>|Z|であるからIACがIDCより大きく
なつた時、IACの負の部分が検波ダイオードのカ
ツトオフ点に入り、歪を生じる。そのため、検波
出力における無歪最高変調度は直流電流と交流電
流とが等しいとすると、直流負荷と交流負荷との
比よつて定められる。
(a) If the DC current of the detection stage is I DC , the DC resistance is R, the AC current is I AC , and the AC resistance is |Z|, then the modulation degree m is m=I AC・|Z|/I DC・R. In general, R>|Z|, so when I AC becomes larger than I DC , the negative part of I AC enters the cutoff point of the detection diode, causing distortion. Therefore, the highest distortion-free modulation degree in the detected output is determined by the ratio of the DC load to the AC load, assuming that the DC current and the AC current are equal.

然し、第1図の場合近似的に直流負荷がR2
R3=160KΩ、交流負荷が10KΩとなるため、無
歪最高変調度は小となり、大入力高変調時(例え
ば100%変調)、SG60dBμ以上)の検波波形に歪
を生じ易い。
However, in the case of Fig. 1, the DC load is approximately R 2 +
Since R 3 = 160KΩ and the AC load is 10KΩ, the maximum distortion-free modulation degree is small, and distortion is likely to occur in the detected waveform when large input and high modulation (for example, 100% modulation) exceeds SG60dBμ.

(b) 小入力高変調時の歪の改善度は、検波用ダイ
オードD1の負荷容量C1と直流負荷との時定数
により定められるものであるが、小入力時には
検波用ダイオードD1のインピーダンスが大き
いので、検波回路の時定数〔τ=C1・(R2
R3)〕が大きく、小入力高変調度の信号(例え
ば100%変調、SG0dBμ以下)の検波時には周
波数が低くなるほど追随出来なくなり歪率が悪
くなる。
(b) The degree of improvement in distortion during small input and high modulation is determined by the time constant of the load capacitance C 1 of the detection diode D 1 and the DC load, but when the input is small, the impedance of the detection diode D 1 is large, so the time constant of the detection circuit [τ=C 1・(R 2 +
R 3 )] is large, and when detecting a signal with a small input and high modulation degree (for example, 100% modulation, SG0dBμ or less), the lower the frequency, the less tracking becomes possible and the distortion rate worsens.

本考案は斯る点に鑑み、ANL回路を備えたAM
受信機の検波回路に於いて、大入力高変調時の検
波歪、及び小入力高変調時の検波歪を改善せんと
するもので、以下本考案の一実施例を第2図に従
い説明する。
In view of this, the present invention is an AM system equipped with an ANL circuit.
In the detection circuit of the receiver, the detection distortion during large input high modulation and the detection distortion during small input high modulation are to be improved.One embodiment of the present invention will be described below with reference to FIG.

尚、第2図に於いて第1図と同一部品について
は第1と同一の符号を用いることにする。
In FIG. 2, the same reference numerals as in FIG. 1 are used for the same parts as in FIG. 1.

第2図から明らかな様に本考案の回路は、検波
用ダイオードのアノードとアース間に設けたコン
デンサC1と並列に、抵抗R4を接続したことを特
徴とする。
As is clear from FIG. 2, the circuit of the present invention is characterized in that a resistor R4 is connected in parallel with a capacitor C1 provided between the anode of the detection diode and the ground.

抵抗R4として例えば10KΩのものを選んでやれ
ば、近似的に検波回路の直流負荷はR4=10KΩ、
交流負荷は抵抗R1,R4の並列回路抵抗値即ち
・R/R+R=5KΩとなる。
For example, if you choose a resistor R 4 of 10KΩ, the DC load of the detection circuit will be approximately R 4 = 10KΩ,
The AC load has a parallel circuit resistance value of resistors R 1 and R 4 , that is, R 1 ·R 4 /R 1 +R 4 =5KΩ.

従つて検波回路の直流負荷と交流負荷の差が小
さくなり、大入力高変調時の検波歪を改善出来
る。
Therefore, the difference between the DC load and the AC load of the detection circuit becomes small, and detection distortion at the time of large input and high modulation can be improved.

又、抵抗R4を設けることにより検波回路の時
定数は小さくなる(τ′=C1・R4)ので、小入力
高変調時の検波歪も改善ることが出来る。
Furthermore, by providing the resistor R 4 , the time constant of the detection circuit becomes smaller (τ'=C 1 ·R 4 ), so detection distortion during small input high modulation can also be improved.

以上の様に本考案は、ANL回路を備えたAM受
信機の検波回路に於いて、直流負荷を1個追加す
るだけで、大入力高変調時の検波歪及び小入力高
変調時の検波歪を改善することが出来る。
As described above, the present invention enables detection distortion during large input high modulation and detection distortion during small input high modulation by simply adding one DC load in the detection circuit of an AM receiver equipped with an ANL circuit. can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のAM受信機の検波回路を示す回
路図、第2図は本考案に係るAM受信機の検波回
路を示す回路図である。 ……ANL回路、D1……検波用ダイオード、
R4……抵抗。
FIG. 1 is a circuit diagram showing a detection circuit of a conventional AM receiver, and FIG. 2 is a circuit diagram showing a detection circuit of an AM receiver according to the present invention. 1 ...ANL circuit, D 1 ...detection diode,
R 4 ...Resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 自動ノイズミツター回路(ANL回路)を備え
たAM受信機の検波回路に於いて、検波用ダイオ
ードの負荷容量と並列で且つANL回路の入力側
に前記検波回路の直流負荷となると共に前記検波
回路の交流負荷の抵抗値以下の抵抗値を有する抵
抗を設け、該抵抗にて前記検波回路の直流負荷と
交流負荷との差を小さくすると共に前記検波回路
の直流負荷と負荷容量の時定数を調整し、以つて
大入力高変調時及び小入力高変調時の検波歪を改
善するようにしたことを特徴とするAM受信機の
検波回路。
In the detection circuit of an AM receiver equipped with an automatic noise mitter circuit (ANL circuit), the DC load of the detection circuit is connected in parallel with the load capacitance of the detection diode and the AC load of the detection circuit is connected to the input side of the ANL circuit. A resistor having a resistance value equal to or lower than the resistance value of the load is provided, and the resistor reduces the difference between the DC load and the AC load of the detection circuit, and adjusts the time constant of the DC load and the load capacity of the detection circuit, A detection circuit for an AM receiver, characterized in that detection distortion is improved during large input high modulation and small input high modulation.
JP8018178U 1978-06-09 1978-06-09 Expired JPS628568Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8018178U JPS628568Y2 (en) 1978-06-09 1978-06-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8018178U JPS628568Y2 (en) 1978-06-09 1978-06-09

Publications (2)

Publication Number Publication Date
JPS54180654U JPS54180654U (en) 1979-12-20
JPS628568Y2 true JPS628568Y2 (en) 1987-02-27

Family

ID=28998844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8018178U Expired JPS628568Y2 (en) 1978-06-09 1978-06-09

Country Status (1)

Country Link
JP (1) JPS628568Y2 (en)

Also Published As

Publication number Publication date
JPS54180654U (en) 1979-12-20

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