JPS5936031Y2 - synthesizer receiver - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a device for indicating the tuning mode of a synthesizer type receiver.

A synthesizer type AM receiver is configured as shown in FIG. 1, for example.

That is, in FIG. 1, 10 indicates a receiving system, and 11
1 is a high frequency tuning circuit, 12 is a high frequency amplifier, 13 is a mixer circuit, 14 is a local oscillation circuit, 15 is an intermediate frequency amplifier, 1
6 is a detection circuit, 17 is a low frequency amplifier, and 18 is a speaker.

Further, 20 indicates a PLL, the oscillation circuit 14 is made into a VCO, the oscillation signal is supplied to the programmable counter 21 and divided into a frequency of 1/H, and the divided signal is supplied to the phase comparison circuit 22. At the same time, an oscillation signal serving as a reference is formed in the oscillation circuit 23, and this signal is supplied to the frequency dividing circuit 24, where the frequency is divided into a signal having a frequency of, for example, 9 kHz, and this signal is supplied to the comparison circuit 22.

The comparison output of the comparison circuit 22 is the local oscillator circuit (VCO).
14 and the variable capacitance diode of the tuning circuit 11, for example, as a control voltage.

Therefore, in steady state, the frequency of the output signal of the counter 21 is equal to the frequency of the divided signal from the frequency dividing circuit 24, 9 kHz, so the oscillation frequency of the local oscillator 14 at this time is Nx9 kHz, and therefore, at this time, Frequency N
Broadcasting at 9-450 kHz has an intermediate frequency of 45Q k
It is converted into a Hz intermediate frequency signal.

Therefore, the frequency division ratio N of the counter 21 is set to N = 109~
If you change it by 1 between 229, 531 to 1611 k
It can receive the Hz band in 9 kHz steps.

Furthermore, 30 shows a control circuit for scanning the receiving frequency by changing the frequency division ratio N, and 31 is an up/down counter (scan counter) for the scanning, and the column number N of this counter 31 is the counter. 21 and becomes its frequency division ratio N.

Further, 32 is a pulse forming circuit that forms a pulse (scan pulse) with a frequency of about lQ Hz that is a count input of the counter 31, Su is a normally open up switch for scanning the receiving frequency in an upward direction, and Sd is a normally open down switch for scanning in the downward direction, 35
．． 36 is a falling trigger type RSS flip-flop circuit. The output Q36 of the flip-flop circuit 36 is supplied to the counter 31 as a control signal for count mode, and when Q36="1", it is in up count mode,
When Q36="O", the down count mode is set.

Further, 37 and 38 indicate a detection circuit (decoder), and the detection circuit 37 is configured so that the count value N of the counter 31 is the maximum value 22.
The detection circuit 38 detects this when the count value N of the counter 31 reaches the minimum value 109.

And 41 is a detection circuit that detects and shapes the intermediate frequency signal to detect the presence or absence of broadcasting, and the detection circuit 41 detects the presence or absence of broadcasting by detecting and shaping the intermediate frequency signal.
When it is equal to or greater than th, the output signal Q41 of the detection circuit 41 becomes "1".

Further, 50 indicates a control circuit for controlling other operations of this receiver, which is configured as a microcomputer in this example, 51 is a CPU (including an interface), and 52 is a control circuit for controlling other operations of this receiver. A ROM in which a program for controlling the operation of the Sm is written, 53 is a RAM
1 is a memory switch for storing broadcast frequency data, and S□ to S7 are channel selection switches for selecting channels 1 to 7.

Note that these switches are all normally open switches, and their hot sides are pulled up inside the CPU 51.

Therefore, for example, when the up switch Su is turned on,
This switch output is supplied as a set input to the flip-flop circuit 35 through the OR circuit 34, and its output Q
35 becomes "1".

Therefore, the pulse P3□ from the forming circuit 32 is supplied to the counter 31 through the AND circuit 33 as a count input.

Also, at this time, the flip-flop circuit 36 is set by the output of the switch Su, and its output Q35 becomes "1".
Therefore, the counter 31 is placed in up-count mode.

Therefore, the count value N of the counter 31 is equal to the pulse P32.
The counter 21 increases by 1 for each
The frequency division ratio N also increases by 1.

Therefore, the receiving frequency is changed by 1 step, i.e. 9
It increases by kHz.

Then, when the reception frequency reaches a certain frequency fi, if the broadcast can be received, the output Q41 of the detection circuit 41 becomes "1", and this is sent as a reset input to the flip-flop circuit 35 through the OR circuit 39. The output Q35 becomes "0".

Therefore, the pulse P3□ is no longer supplied to the counter 31, and the gaunt of the counter 31 is stopped, so that the receiving state at this frequency fi continues thereafter.

On the other hand, when the down switch Sd is turned on, the pulse P3° is similarly supplied to the counter 31, and the flip-flop circuit 36 is reset by the output of the switch Sd, so that Q36=°“0”. 3
1 is the down count mode.

Therefore, the count value N of the counter 31 is equal to the pulse P32.
The received frequency is 9kHz.
It goes down step by step.

Then, if the broadcast can be received, the output Q4 of the detection circuit 41
□ stops at that receiving frequency.

Therefore, by operating the switches Su and Sd, the receiving frequencies are scanned and broadcasting on any frequency can be selected.

Then, when a broadcast of a certain frequency fi is received, if any switch Sj of the channel selection switches S1 to S7 is turned on while the memory switch Sm is turned on, the current value Ni of the counter 31 corresponds to the correspondence of the RAM 53. is written to memory address Aj.

Note that writing of this count value Ni, that is, writing of broadcast frequency data can be performed for seven stations corresponding to the switches S1 to S7.

When broadcast frequency data is written in the RAM 53, when any switch Sj among the channel selection switches S1 to S7 is turned on, the frequency data Ni is read from the corresponding memory address Aj in the RAM 53. served,
This is set in the counter 31.

Therefore, the frequency division ratio N of the counter 21 is also Ni, and henceforth the reception state of the broadcast of the corresponding frequency fi is established.

Note that the preset to the RAM 53 and the preset channel selection are performed according to a program written in the ROM 52.

In addition, the receiving frequency increases by operating the switch Su,
When the frequency reaches the highest frequency in the receiving band, the counter 31's current value is N = 229.
When this happens, this is detected by the detection circuit 37,
Since the detection output is supplied as a reset input to the flip-flop circuit 35 through the OR circuit 39, Q35
="0", and the pulse P3□ is blocked by the AND circuit 33.

Therefore, when the receiving frequency reaches the highest frequency of the receiving band, scanning of the receiving frequency stops there.

Similarly, when the receiving frequency is lowered by operating the switch Sd and becomes the lowest frequency in the receiving band, that is, when the current value of the counter 31 is N = 10.
When it reaches 9, it is detected by the detection circuit 38, and its detection output is supplied as a reset input to the flip-flop circuit 35 through the OR circuit 39, so that Q
35="0", and the pulse P3□ is blocked by the AND circuit 33.

Therefore, when the receiving frequency reaches the lowest frequency of the receiving band, scanning of the receiving frequency stops there.

In this way, in the receiver of FIG. 1, the reception frequency can be scanned and received by operating the switches Su and Sd, the frequency data can be preset by operating the switch Sm, and by operating the switches S1 to S7, You can select preset broadcasts.

Further, when scanning is performed, the scanning is automatically stopped when the receiving frequency reaches the highest frequency or the lowest frequency, thereby preventing operational errors.

However, with the above configuration, the reception frequency is not displayed, so even if scanning stops at the highest or lowest frequency, the user cannot know this and ends up waiting for a channel to be selected.

Furthermore, even if the scanning is stopped due to temporary disturbance noise, for example, this cannot be distinguished from the case where the scanning is stopped due to reaching the highest or lowest frequency, which is still inconvenient for channel selection.

In this case, if the receiver is large, sufficient space can be secured for the receiving frequency display means (dial display device), mode display means, etc., but if the receiver is used like a pocket radio, When miniaturized, it becomes impossible to secure space for such a display means.

Further, these displays are performed using electro-optical elements, but when operated by batteries, the power consumption of the display element and related circuitry becomes a problem.

This invention solves the above-mentioned problems by using existing circuits without using any special parts or circuits, and particularly makes it possible to do this reliably.

An example of this will be explained below.

In Fig. 2, Dl is a detection diode, R1 is a variable resistor for volume adjustment, and this includes resistors R2 and R3.
is connected.

Also, Jl is an earphone shack.

Further, the frequency divided signal from the frequency dividing circuit 24 is supplied to another frequency dividing circuit 61 that performs frequency division by 174, and the frequency is 2°25kHz.
z signal Sa, and this signal Sa is sent to the AND circuit 7.
1.73.74, and is also supplied to a frequency divider circuit 62 that performs frequency division by 172, where it is divided into a signal sb with a frequency of 1.125 kHz, and this signal sb is supplied to an AND circuit 72.

Furthermore, the detection outputs of the detection circuits 37 and 38 are output from the AND circuit 71.
．． At the same time, the output pulse of the AND circuit 33 is supplied to the AND circuit 73.

Furthermore, the hot side of the switches S1 to S7 is connected to the AND circuit 7.
6, its AND output is supplied to a falling trigger type monostable multivibrator 77, and the output pulse P7□ of this multivibrator 77 is supplied to an AND circuit 74.

Then, the outputs of the AND circuits 71 to 74 are outputted to the OR circuit 75.
The signal is further supplied to the input terminal of the amplifier 17 through a low-pass filter 78 .

Note that the filter 78 is placed near the OR circuit 75,
The line between OR circuit 75 and filter 78 is shortened.

Furthermore, the collector and emitter of the transistor T1 are connected in parallel to the output terminal of the detection circuit 16, for example, before the amplifier 17, and the output terminal of the OR circuit 75 and the transistor T1 are connected in parallel.
A diode D1□ is connected between the base of the transistor T1 and a capacitor C1 is connected in parallel between the base and the emitter of the transistor T1.

Further, the output Q35 of the flip-flop circuit 35 is supplied to the base of the transistor T□ through the diode D02, and the output pulse P7 of the multivibrator 77 is supplied to the base of the transistor T□.
7 is supplied to the base of transistor T1 through diode D13.

According to such a configuration, when a broadcast is preset by operating one of the switches S1 to S7, or when a preset broadcast is selected, the output of the AND circuit 76 becomes "0'', this triggers the multivibrator 77 to form a pulse P77, which is supplied to the transistor T1 through the diode D13.

Therefore, during the period when the pulse P7□ is "1", the transistor T1 is turned on and the audio signal from the detection circuit 16 is muted.

Also, at this time, pulse P77 is supplied to AND circuit 74.

Therefore, during the period when P7□="1", the signal Sa is supplied to the amplifier 17 through the AND circuit 74 and the OR circuit 75, and further through the filter 78, so that the signal Sa is output from the speaker 18 as shown in the first column of FIG. , the sound of the signal Sa is played for a short time.

Therefore, it can be confirmed from this reproduced sound which of the switches S0 to S7 has been operated.

Also, when switch Su or Sd is operated,
Scanning is performed, but at the same time as this switch is operated, Q3
5=“1”, and this Q35-“1” state continues during scanning, and this output Q35 is connected to the diode D1□
The voltage is supplied to the transistor T1 through the transistor T1.

Therefore, the transistor T1 is on during the scanning period from when the switch Su or Sd is operated, and the audio signal from the detection circuit 16 (this signal is
During scanning, inter-station noise, etc.) is muted.

At this time, the scan pulse P3□ from the AND circuit 33 is supplied to the AND circuit 73, so the signal Sa
is supplied to the amplifier 17 through an AND circuit 73, an OR circuit 75, and a filter 78.

In this case, since the scan pulse P3□ is a pulse train, the signal Sa is intermittently supplied to the amplifier 17, and the speaker 18 outputs the sound of the signal Sa as shown in the second column of FIG. is played intermittently.

At this time, since the reception frequency changes by one step for each scan pulse P3°, the scan is performed by one step for each intermittent sound from the speaker 18.

In this way, it can be confirmed by this intermittent sound that scanning is being performed.

Then, when the scanning continues and the receiving frequency reaches the highest frequency of the receiving band, the scanning is stopped by the detection output of the detection circuit 37, and this detection output is supplied to the AND circuit 71, so that the signal Sa becomes AND circuit 71
and is supplied to the amplifier 17 through the OR circuit 75 and further through the filter 78.

At the same time, the signal Sa from the OR circuit 75 is rectified and smoothed by the diode D1□ and the capacitor C1□ to become a muting signal, and this signal is supplied to the transistor T1.

Therefore, when the receiving frequency reaches the highest frequency, the detection circuit 1
The audio signal (interstation noise) from No. 6 is also muted.

As long as the receiving frequency is the highest frequency and scanning is stopped, the detection output of the detection circuit 37 is continuously obtained, so the sound of the signal Sa is output from the speaker 18 as shown in the third column of FIG. Plays continuously.

Therefore, from this continuous sound, it can be known that the scan has stopped at the upper limit.

On the other hand, when scanning continues and the receiving frequency becomes the lowest frequency of the receiving band, the scanning is stopped by the detection output of the detection circuit 38, and this detection output is supplied to the AND circuit 72, so that the signal sb is The signal is supplied to the amplifier 17 through an AND circuit 72, an OR circuit 75, and a filter 78.

Also, at this time, the signal sb from the OR circuit 75 is rectified and smoothed by the diode D1□ and the capacitor C1l and supplied to the transistor T1, and the audio signal (interstation noise) from the detection circuit 16 is muted. Therefore, the sound of the signal sb is continuously reproduced from the speaker 18 as shown in the fourth column of FIG.

Since the frequency of the signal sb is lower than the frequency of the signal Sa, it is possible to know from the continuous sound from the speaker 18 that the scan has stopped at the lower limit.

Thus, according to this invention, as shown in FIG. 3, when the switches S1 to S7 are operated, the confirmation sound is e.g.
During scanning, the operation sound becomes "beep beep...", and when the scan reaches the upper limit, it becomes a "beep" sound effect, and when it reaches the lower limit, it makes a "baud" sound. It becomes another sound effect.

Therefore, you can know the mode of the receiver by these sounds, and you may not notice that scanning is not being performed due to a mistake in operating the switches Su or Sd, or
There is no need to wait for a channel to be selected even though the scan has reached the upper or lower limit and stopped.

Furthermore, if a channel is not selected due to a mistake in operating the switches S1 to S7, the user does not assume that it is a malfunction, and if the switches Su, Sd, or S1 to S7 are pressed by mistake, a warning sound is generated.

Moreover, in this case, when playing the sound effect, the audio signal from the detection circuit 16 is muted, so the S/N of the sound effect is improved, and the sound effect is masked by the broadcast sound, music, or noise. You can definitely hear the sound effects without any trouble.

In addition, especially according to this invention, the muting signal when the receiving frequency reaches the highest frequency or the lowest frequency of the receiving band is obtained by rectifying and smoothing the signals Sa and Sb, which are sound effects, using the diode D1□ and the capacitor C1l. The configuration is simple and inexpensive.

As described above, according to this invention, the mode of the receiver can be known by the sound effect, which gives a very sense of security and ease of use.

Further, since a display means for displaying the reception frequency and mode is not required, the receiver can be made smaller and lower in cost, and there is no power consumption for the display means, so that reception can be performed for a long time using batteries.

Furthermore, even when the receiver is placed in a pocket and listened to through earphones, it is easy to select a channel and it is easy to use.

Furthermore, since a piezoelectric buzzer or the like is not used to produce sound effects, the signals Sa and Sb are supplied to the amplifier 18, so there is no increase in cost and miniaturization is possible.

Further, the sound effects can be heard whether the broadcast is being listened to through the speaker 18 or through earphones.

In addition, in the above, instead of the signals P7□ and Q35,
It is also possible to shape the error voltage of the comparator circuit 22, thereby applying muting when operating the switches S1 to S7 and during scanning.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an example of a receiver, FIG. 2 is a system diagram of the main part of this invention, and FIG. 3 is a diagram for explaining the same. 10 is a receiving system, 20 is a PLL, 30 is a tuning control circuit, 6
1.62 is a frequency dividing circuit.

Claims (1)

[Scope of utility model registration request] In a synthesizer receiver configured to receive broadcast waves of a desired frequency by changing a frequency division ratio of a programmable counter, a detection circuit detects a maximum value and a minimum value of values set in the programmable counter;
It has a circuit that forms a sound effect signal and a low frequency amplifier to which the audio signal from the detection circuit is supplied, and when the detection circuit detects the maximum value or the minimum value, the detection output produces the sound signal. A synthesizer receiver which mutes the signal and supplies the sound effect signal to the low frequency amplifier to notify by sound effect that the reception frequency has reached the highest frequency or the lowest frequency.