JPS593530A - Input/output control device - Google Patents
Input/output control deviceInfo
- Publication number
- JPS593530A JPS593530A JP57112878A JP11287882A JPS593530A JP S593530 A JPS593530 A JP S593530A JP 57112878 A JP57112878 A JP 57112878A JP 11287882 A JP11287882 A JP 11287882A JP S593530 A JPS593530 A JP S593530A
- Authority
- JP
- Japan
- Prior art keywords
- control device
- actuation
- bus
- cpu
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004913 activation Effects 0.000 claims description 13
- 230000007935 neutral effect Effects 0.000 abstract description 3
- 238000001994 activation Methods 0.000 description 10
- 238000012545 processing Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明1・土、複数のパスより共用される磁気ディスク
制御装置に係り、特に、サービスの単一系に対する片寄
りを防止する機構を備えた共用装置制御方式に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention 1 relates to a magnetic disk control device shared by a plurality of paths, and is particularly provided with a mechanism to prevent services from being biased towards a single system. Concerning shared device control methods.
従来、磁気ディスク制御装置等のI10制御装置は、ホ
ストからの起動がかかった際、その時点で、サービス処
理が可能でを】れば、無条件に起動を受は付けていた。Conventionally, when an I10 control device such as a magnetic disk control device is activated by a host, if service processing is possible at that time, the I10 control device accepts the activation unconditionally.
しかし、前記磁気ディスク制御装置等のI10制御装置
が、処理能力の異なるホストCPUに共用され、高速ホ
ストCPUからの起動が頻発するようになると、他系す
なわち低速ホス)CPUからの起動に対して応答できな
くなり、複数ホス)CPUから共用されているにもかか
わらず、そのサービス処理が著しく単一系に片寄るとい
う欠点があった。However, when the I10 control device such as the magnetic disk control device is shared by host CPUs with different processing capacities, and startup from the high-speed host CPU occurs frequently, it becomes difficult to start from another system (i.e., low-speed host) CPU. Despite being shared by multiple host CPUs, the service processing is significantly biased toward a single system.
本発明の目的は、高速ホス)CPUからの起動が多発し
た場合においても、低速ホス)CPUからの起動による
サービス要求も受けつけられるような、起動受付制御装
置を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a startup acceptance control device that can accept service requests from low-speed host CPUs even when startups from high-speed host CPUs occur frequently.
本発明は、磁気ディスク制御装置等のI10制御装置の
チャネルスイッチの各パス毎に起動受理回数を計数する
カウンタを設け、一定時間内に同一パスよりある回数以
上の起動があった場合、前記パスよシの新たな起動に対
しては、磁気ナイスり制御装置等のI10制御装置のハ
ードウェアが自動的にコントロール・ユニット・ビジィ
(使用中)を報告し、特定パスへのサービスの片寄りを
抑制し、他糸パスに対するサービスも行なえるようにし
だものである。The present invention provides a counter for counting the number of startup acceptances for each path of a channel switch of an I10 control device such as a magnetic disk control device, and if startup is received from the same path more than a certain number of times within a certain period of time, the said path For new power ups, the I10 controller hardware, such as the magnetic nice controller, automatically reports control unit busy and directs service to specific paths. It is designed to suppress the flow rate and also allow services for other thread paths to be performed.
図は、覆設のホス)CPUから共用される、磁勿ディス
ク制御装置(DKC)の例を示す。DKC4がどちらの
CPU(la、lb)からの起動を受けていない状態で
は、チャネル・スイッチ5は、中立漬にあり、たとえば
、CPU1aから、DKC4に起動がかかると、チャネ
ル・スイッチ5はA側に倒れる。そしてこのチャネル・
スイッチがA側に倒れている間、CPU1bから起動が
かかっても受W#Lf、コントロール・ユニット・ビジ
ィとなる。The figure shows an example of a magnetic disk controller (DKC) shared by a hidden host CPU. When the DKC4 is not activated by either CPU (la, lb), the channel switch 5 is in neutral mode. For example, when the DKC4 is activated from the CPU 1a, the channel switch 5 is switched to the A side. falls down. And this channel
While the switch is on the A side, even if the CPU 1b starts up, it will receive W#Lf and the control unit will be busy.
CPU1aに対するサービスが終了すると、再び中立点
に戻る。 −
このとき、CPU1aに対してはサービス終了の報告、
そしてCPU1bに対してはビジィ解璋の報告がなされ
るが、両者間には、数10マイクロ秒の時間差が生じる
。この時漬で、両CPUともDKC4に対してのサービ
スが必要な場合、前記報告がさハた直後に、DKC4に
起動をかけようとするが、前記の時間差のため、2つの
CPUの処理速度が同じ、あるいけ、CPU1aの方が
速い場合、CPU1aの起動が受理されCPU1bのサ
ービス要求は、コントロール・ユニット・ビジィとなっ
てしまう。この状態は、CpUlaのサービス要求が同
様な間隔で続、く限り継続し、CPU1bのサービス要
求は受理されないことになる。When the service for the CPU 1a ends, it returns to the neutral point again. - At this time, the CPU 1a is notified of the end of the service,
Then, a report of busy release is sent to the CPU 1b, but there is a time difference of several tens of microseconds between the two. In this case, if both CPUs require service for DKC4, they will try to start up DKC4 immediately after the above report is sent, but due to the time difference, the processing speed of the two CPUs will be If they are the same, or if the CPU 1a is faster, the activation of the CPU 1a will be accepted and the service request of the CPU 1b will become control unit busy. This state will continue as long as CpUla's service requests continue at similar intervals, and the CPU 1b's service requests will not be accepted.
また、一般に、磁気ディスク制御装置は、あるデバイス
に対するサービス終了報告を、行った彼、シーク、セッ
ト・セクタによシ突き放されていた、他のデバイスから
の終了割込みを処理するアイドル・ループに戻るまでに
100マイクロ秒はど後処理時間を必要とする。従って
、あるホス) CPUが非常に高速で、サービス終了報
告から、次の起動までの時間が前記後処理時間よシも短
い場合にt=、Dr<:cは、前記高速CPUのサービ
スを連続して処理し続けることになシ、アイドルループ
で行なうべき処理が全くできない。Additionally, the magnetic disk controller typically returns to an idle loop to process termination interrupts from other devices that have reported termination of service to one device, had been abandoned by the seek, set sector, etc. A post-processing time of 100 microseconds is required. Therefore, if the CPU on a certain host is very fast and the time from the service termination report to the next startup is shorter than the post-processing time, t=, Dr<:c means that the high-speed CPU's service continues If the idle loop continues processing, the processing that should be performed in the idle loop cannot be done at all.
これらの事態を防止するために、本発明では、前記チャ
ネル・スイ多チの各パスごとに、起動の1fij数を計
数するカウンタを設け、同一パスから、ある定められた
単位時間に、一定回数の起動が多発してかかった場合、
たとえ、その時点で、DKCが起動受理可能な状態であ
ったとしても、当該パスからの新たな起動に対しては、
コントロール・ユニット・ビジィを報告し、同一パスか
らの起動多発を抑止し、前記DKC独占状態に陥るのを
防止する。この動作は、DKCファームウェアを介さず
に行なわれ、DKCハードウェアが単独に処理する。起
動抑止は、ある一定時間続けられ、その間に1デバイス
の終了割込みや、他のパスからの起動を受理することが
できる。In order to prevent these situations, in the present invention, a counter is provided for counting the number of activations for each path of the channel switch multiplier, and a counter is provided for counting the number of activations for each path of the channel switch multiplier, and a counter is provided for counting the number of activations for each path of the channel switch multiplier, and a counter is provided for counting the number of activations from the same path a certain number of times in a certain predetermined unit time. If it starts up too often,
Even if the DKC is in a state where it can accept booting at that time, for a new boot from the relevant path,
Control unit busy is reported, and frequent activation from the same path is suppressed to prevent the DKC from falling into the monopolized state. This operation is performed without going through the DKC firmware and is processed solely by the DKC hardware. The activation suppression continues for a certain period of time, during which time a termination interrupt from one device or activation from another path can be accepted.
E゛発明効果〕
本発明によれば、複数ホストにより共用される、I10
制御装置に対する単−系からの起動の多発にlトなうサ
ービスの片寄りを防止することができる。E゛Inventive Effects゛According to the present invention, I10 shared by multiple hosts
It is possible to prevent services from becoming unbalanced due to frequent activation of the control device from a single system.
図は、本発明の一実施例を示す。さらに図において各番
号は下記のものを示す。
la、lb:中央処理装置(cpU)、2a、2b:チ
ャネル装置、3a、3b:起動回数カウンタ、4:磁気
ディスク制御装置1e(nKc)、 5:チ+ネル・ス
イッチ、6:磁気ディスク・アダプタ、7:磁気ディス
ク装置。The figure shows an embodiment of the invention. Further, in the figures, each number indicates the following. la, lb: central processing unit (cpU), 2a, 2b: channel device, 3a, 3b: boot count counter, 4: magnetic disk control unit 1e (nKc), 5: channel switch, 6: magnetic disk Adapter, 7: Magnetic disk device.
Claims (1)
ネルスイッチを備えたI10制御装置において、各パス
毎に、当該パスより起動が多発した事を検出する手段を
備え、前記起動多発状態にあるパスからの起動に対して
、前記I10制御装置を寸使用中の旨を報告することを
特徴とする17勺制御装置。In an I10 control device equipped with a channel switch that is shared by a plurality of paths and has a plurality of contacts, means is provided for each path to detect that activation occurs frequently from the path, and the path in the frequent activation state is provided. 17. A 17-inch control device, characterized in that it reports that the I10 control device is currently in use in response to activation from .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57112878A JPS593530A (en) | 1982-06-30 | 1982-06-30 | Input/output control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57112878A JPS593530A (en) | 1982-06-30 | 1982-06-30 | Input/output control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS593530A true JPS593530A (en) | 1984-01-10 |
Family
ID=14597787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57112878A Pending JPS593530A (en) | 1982-06-30 | 1982-06-30 | Input/output control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS593530A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60139187U (en) * | 1984-02-24 | 1985-09-14 | 古河電気工業株式会社 | automotive heat exchanger |
JPS63128457A (en) * | 1986-11-12 | 1988-06-01 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Controller and control of access to input/output device |
-
1982
- 1982-06-30 JP JP57112878A patent/JPS593530A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60139187U (en) * | 1984-02-24 | 1985-09-14 | 古河電気工業株式会社 | automotive heat exchanger |
JPS63128457A (en) * | 1986-11-12 | 1988-06-01 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Controller and control of access to input/output device |
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