JPS593482A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a display device, and in particular to an electroluminescence (EL) display device in which a driving circuit is integrally provided with a pixel and drives each pixel. The present invention relates to such a flat panel display device.

Background of the Technology In recent years, research and development has been conducted on EL display devices in which display elements and drive circuits for the elements are integrally integrated on the surface of a semiconductor substrate.

FIG. 1 is a cross-sectional view of a main part conceptually showing the structure of one conventional pixel of this type of FiL display device, and is a sectional view of a main part of a conventional FiL display device. MOS transistor (T'M) as a switching element
(abbreviated as O8T) 20 O, J: Along with it, an f-vacuum doped layer 3 provided on the whole surface of the substrate l.
A polysilicon lightning pole 4 insulated with, for example, silicon dioxide (SiO2) Nm2 is provided opposite to the pixel electrode 7. 7. On top is E, which is the display medium.
An L layer 9 is formed, and indicum tin oxide (I
A transparent electrode 8 such as TO) is formed. A pixel is defined by the area where the pixel electrode 7 and the transparent electrode 8 face each other, and by applying a driving voltage between these electrodes, it is possible to
The EL layer 9 in the area indicated by PU in the figure is designed to emit light. Note that this is a light shielding film for shielding light from the 5th and 10th EL layers 9.

(C) Prior Art and Problems IP52 is a schematic diagram of the main parts showing the isometric circuit configuration of this KL display device. In the diagram, Q+F! The address switching element is Totoru MO8T.

Q, 2 is the switching element for the driver "MO8T"
It is. When the pulse voltage applied to the scanning line SL becomes high level, MOEIT Q is first turned on. Then, in synchronization with this, another pulse is given to the data line DL, and if this becomes high level, the memory capacitor c
M is charged and MO8TQ2 is turned on. Here, since the driving AC voltage is applied to the terminal 30, MO8
When TQ and 2 are on, the luminescent Yonago PL emits light. The light emitting element EL continues to emit light while the memory capacitor cM is being charged even after MO8T QI is turned off. Note that D2 is a Zener diode provided to prevent dielectric breakdown of MO8TQ,2. , and the memory capacitor cM is connected to the polysilicon electrode 4 and P shown in FIG.
+Q heavily doped layer 3. The memory capacitor CM is configured such that when the display device in which the light emitting elements EI integrated with the drive circuit are arranged in a matrix as shown in the equivalent circuit of FIG. It is for maintaining Ka1
In addition, when erasing the light emitting element EL, a high level pulse is applied to SLK and a low level pulse is applied to the cheetah line DL. DL is discharged, MO8TQ,2 is turned off, and the light emitting element EL is erased.

By the way, since the memory capacitors at and t require relatively large capacitance and occupy a large area, they are formed at the bottom of the collecting electrode 7 as shown in FIG.

On the other hand, when increasing the resolution and size of a display device, it is necessary to reduce the pixel size and increase the number of pixels. Therefore, the area of the pixel electrode must be reduced, and the capacitance of the memory capacitor CM will also be reduced1. On the other hand, the period of one frame will become longer due to the increase in the number of pixels.
On the contrary, a contradictory condition arises in which the capacity of the memory compensator CM must be increased. If this increase in the capacity of the memory capacitor C1/ is not realized, it will be impossible to sustain the light emission of the 9 light emitting elements during one frame period, resulting in a decrease in the average brightness of one surface. (6) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and aims to reduce the capacity of memory capacitors, which conventionally required relatively large customers, and to reduce the average brightness of nine surfaces. The object of the present invention is to provide a display device having a configuration that allows for higher resolution and larger size without causing problems.

(e) Configuration of output q1 The display device according to the present invention uses address switching elements connected to the scanning line and the data line to drive the light emitting element corresponding to one pixel A, 01! In a configuration in which a driver switching element for controlling on/off voltage is selectively operated, a storage capacitor is provided between the control electrode of the driver switching element and a reference potential point, and a storage capacitor is provided in the vicinity of the light emitting element for each pixel. The invention is characterized in that a light receiving element is provided for each light receiving element, and the supply of driving Ao@ pressure to the light emitting element is maintained in an on state by the light receiving output of the light receiving element.

(f) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a schematic diagram of the main parts showing the isometric circuit configuration for one pixel of the EL display device according to the present invention, and FIG. 4 is a cross-sectional view of the main parts showing the structure of the PL display device according to the present invention. .

In FIG. 3, MO8T Ql is an address switching element, which connects the scanning line SL and the data line DL.
are connected to each. Also, MO8TQ2 is a light emitting element K
This is a driver switching element for on/off control of the driving alternating pulse voltage for L, and its λ40S
The storage content C8 is connected between the control electrode of TQ2, that is, the gate G2, and the ground, for example, reference potential points. This storage capacitor C8//'i will be described later, and is composed of a capacitor having a smaller capacity than a conventional memory capacitor.

Furthermore, RP is a light-receiving element provided close to the light-emitting element KL, and the light-receiving element RpVi is composed of a phototransistor, a photodiode, or a photoconductive phosphor such as sulfur domicum (CaS). In this embodiment, the light receiving element has a structure of, for example, a 0 (iSS) photoelectric element, which receives light from the light emitting element EL and changes its photoresistance according to the amount of light, and the light receiving element RP is It is connected in parallel to MOBT Q2. Note that MO8TQ3 is a reset switching element provided to turn off the driving alternating pulse voltage applied to the light emitting element EL during reset 7).

Incidentally, in FIG. 3, storage content is shown enclosed by a dotted line 21 between the blunt doped layer 3 and the polysilicon electrode 4 disposed oppositely on the doped layer 3 with the 8102 layer 2 interposed therebetween.
11j'c8. Furthermore, the 06.8 film 1 is insulated with a 5102 layer 6 on the polysilicon electrode 4],
is formed to constitute the light receiving element RP. And that Ca
A pixel electrode 7 is provided on the S film 11 with an 8102 layer 6 interposed therebetween. The pixel electrode 711-tsTO film or gold (
It is formed of a transparent conductive thin film such as A, u) or aluminum (A]). Further, a KL layer 9 and a transparent electrode 8 are formed on the pixel electrode 7, and the pixel electrode 7 and the transparent electrode &8
The light emitting element BL is configured in the region facing the. 5 is a light shielding film.

Now, the operation of the EL display device configured as described above will be explained with reference to FIG. Now, an alternating pulse voltage for driving the light emitting element ELK is applied to the terminal 30.

Further, a voltage is applied to the terminal 31 to turn on 1408TQ, 3. If the display element EL is in a non-emitting state, that is, in a non-selected state, in order to bring it into a selected state,
MOBT
J is turned on. Then, the storage capacitor C6 is charged, and accordingly, MO8TQ,2 becomes a secondary voltage. At this time, since λ40STQ,3 is also on as described above, the light emitting element BL emits light. At this time, the light-receiving element RpN receives light from the light-emitting element KL and turns on, and the driving alternating pulse voltage continues to be supplied to the first light-emitting element ET to maintain light emission. Here, the condition for maintaining light emission is whether the light emitting element KL needs to emit light at least once during the ON period of MO8TQ2.

By the way, it is possible to consider a method in which the storage content C6 is not provided, but if this storage capacitor C8 is not provided, the driving alternating pulse must be applied at least once to the light emitting element EL while the tilt MO8TQ is on. Yes, it is limited by the frame period d and the repetition frequency of the driving alternating pulse.

However, by providing the storage capacitor C8, once the selection state is established, even if the MOeT Ql is turned off, the M
Since O8TQ2 can maintain the sub-on state for a while, the frame period is no longer limited by the repetition frequency of the driving alternating pulse. Here, the lifetime of the optical carrier of the light receiving element RP needs to be longer than the period of the alternating pulse for the driver 11J. Furthermore, the period during which MO8TQ,2 is kept in the ON state only needs to be longer than the period of the driving alternating pulse, and the capacity of the storage capacitor Cs can be made significantly smaller than that of conventional memory capacitors. .

When resetting the broken light emitting element E-cho, use MO8TO,
You can turn off 3. This method includes MO8TQ,
+I Let Q2 be a Hanegyannel type, MOB
There is a method such as connecting the gate of M(') STQ, 3 to the scanning line one tree in front of the TQ3 as a p-channel tebresion type5. FIG. 2 is a schematic diagram of main parts showing an example isometric circuit configuration.

Identical parts in Figure 3 are given the same reference numerals.

The 41F structure of the part surrounded by the dotted line 21 in the figure is no different from that in FIG.
This point is connected between the reset line RL and the reset line RL to which the voltage vH is applied to turn on the circuit 2. In this case, when the light emitting element EL emits light, the light receiving elements R and P turn on, and the voltage vH applied to the terminal 32 is applied to the gate of MO8TQ, 2, which maintains the on state, so that the light emitting element KL continues to emit light. At this time, the frame period is not limited by the repetition frequency of the driving alternating pulse applied to the terminal 30, and the light receiving element R
When P is on, the storage capacitor C8 continues to be charged, so it becomes necessary to make the lifetime of the photo-parallelization of the light-receiving element RP longer than the period of the driving alternating pulse.

Next, a method for erasing or resetting the light emitting element EL will be explained with reference to FIG. FIG. 6 is a diagram showing the voltage waveforms applied to the reset line RL and the scanning line ELK, with corresponding signs.
The reset pulse applied to the scanning line SL switches to 0 at timing t1, and switches to voltage vH again at timing t3.On the other hand, the scanning pulse applied to the scanning line SL is 2 high and 17 high at timing. Switch to low level at t4. Is it running when the reset pulse is Ov? If it is held at timing t3''!f for the period in which 1/<res is applied (between t2 and t4), the data pulse is not applied to the MO8TQ, l train from the data line D1. Several boxes of C8 weights are sent through the data line DL during the t2-t3 period.

MOEIT9.2 is turned off and the light emitting element KL is erased.

In addition, in the above-mentioned method, when erasing the light emitting elements F and L, a method of applying a reset pulse to the reset line RLK is described, but in addition to the method described below, it is also possible to erase the light emitting element-7EL by the following method. That is, the on-resistance rpos of the light receiving element RP in FIG. 5 is calculated to be sufficiently larger than the on-resistance rlON of MO8TQ,l7.
When the light emitting element PL is in a light emitting state, a voltage V2 sufficient to turn on MO8TQ2 is applied from the center line RL to the gate of MO8TQ2 through the light emitting element IRP.
ON is applied. Here, when the scan/(res) is applied to the gate of MO8TQ1 and MOEIT Q,1 is turned on, the data pulse applied to the drain of MO8TQ1 is a low level signal.

) and rlON (under rPON conditions, MO8TQ
.

If this is expressed as a conditional expression, it becomes K as shown in equation (1).

Here, the DC voltage applied to the VHh reset line RL + (T) is the threshold voltage of FiMO8T Q,2.

Equation (2) is obtained from Equation (1).

By setting the characteristics of each element and the voltage applied to the reset line RL so as to satisfy the condition of equation (2), the reset line RL can be made common within the display device, and the reset line RL can be used in common within the display device. 7) Since there is no need for a response generation circuit, there is also the advantage that the configuration and structure of the display device can be extremely simplified.

(g) Effects of the Invention As is clear from the above description, according to the present invention, the capacity of the storage capacitor can be reduced and the resolution of the display device can be increased without causing a decrease in the surface average brightness. It becomes possible to increase the size, and its practical effects are great.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of main parts showing the structure of a conventional display device;
The figure is a schematic diagram of main parts showing an isometric circuit configuration of a conventional display device, FIG. 3 is a schematic diagram of main parts showing an isometric circuit structure of a display device according to the present invention, and FIG. 4 is a display according to the present invention. FIG. 2 is a cross-sectional view of main parts showing an example structure of the device. FIG. 5 is a schematic diagram of a main part showing an isometric circuit configuration of another embodiment of a display device according to the present invention, and FIG. 6 is a diagram showing an example of a reset pulse and a scanning pulse. In the figure, 1 is the substrate, 2 and 6 are 8102 layers. 3 is an impurity doped layer, 4 is a polysilicon electrode, 5 and ]0 light shielding film, 7 is a pixel electrode, 8 is a transparent electrode, 9id:
F, L layer, 1lFi (3dEI film, SL is scanning line,
rlLke cheetah line, RL [reset line +Q
5+tj address switching element, Q, 2 is a F-Leiper switching element, Q, 3 is a reset switching element, C8 storage capacitor iP#-i light receiving element,
KL and KL respectively indicate light emitting elements. Figure 3 Figure 4 Figure 5 s Figure 6

Claims (1)

[Claims] In a configuration in which a driver switching element for controlling on/off control of a driving AC voltage for a light emitting element corresponding to nine pixels is selectively operated by an address switching element connected to a scanning line and a data line, respectively, the driver switching element is controlled. A single-product capacitor is provided between the electrode and the reference potential point, and a light receiving element is arranged for each pixel in close proximity to the light emitting element, and a driving AC is connected to the light emitting element by the light receiving output of the light receiving element.
A display device characterized in that a voltage supply is maintained in an on state.