JPS5934015B2 - Digital value set circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for setting digital values to a memory, and is constructed so that digital values in a specific range can be set to the memory very easily.

What was conventionally treated as analog values has recently come to be treated as digital values, and conventional analog devices are being replaced by digital devices.

In such digital devices, it is often necessary to set various digital values or preset (initialize) them in advance.

For example, a so-called synthesizer-type radio receiver that can directly set the receiving frequency, which is a digital value,
They are used in a wide range of fields, including television receivers that can store the optimum tuning point for each channel as a digit value, automatic scales that can set various unit prices, and vending machines that can set the list price of various products.

Furthermore, the range of digital values to be set may be limited.

For example, in a synthesizer-type radio receiver, a numerical value related to the reception frequency (for example, "85-I
MHz", but for FM broadcasting, the broadcast frequency is "76".
．． 0MHz to 90.0MHz "corresponds to" 76
Enter a numerical value in the range 0 to 900, or for AM broadcasting to a broadcast frequency of 1'535 KH2 to 1605 Hz.
It is sufficient to set a numerical value in the range of 535 to 1605" corresponding to .

For rice, it has been proposed that such digital values be set (including presets) in digital memory (e.g. magnetic memory, semiconductor memory), but as a method of setting data (digital values) in digital memory, Conventionally, the following methods have already been proposed.

■ Digital switch method.

For example, when setting 3-digit data, three digital switches are provided corresponding to each digit, and the digital switches are set in sequence to the desired value. As the number of digits of data increases, the number of digital switches that must be operated also increases, making it time-consuming to set the data. If you do not know the setting, it is extremely difficult to set it.

■ Tenki one-sided system.

This method uses 10 keys from 0 to 9, and is convenient when the numerical value of the data is known, but as mentioned above, when the numerical value of the data is unknown, It's inconvenient.

■ One-way up/down counter.

This is a method that applies a clock pulse to a counter and uses the count output.

In this method, since the counting output changes sequentially, it is possible to set the numerical value even when the numerical value of the data is unknown.

For example, to set a number associated with a broadcast frequency (e.g., 851, which corresponds to 85.1 MHz) in a synthesizer-based radio receiver, a clock pulse is applied to the counter so that the output of the counter changes. When the number 851 is counted, the number 851 can be set in the memory element by blocking the application of the clock pulse at this time, since the radio broadcast sound can be heard.

However, this method requires two types of operations: up-counting and down-counting, and if the numerical value of the data to be set is 3 digits, the counter output changes from O to 999. Since it takes time, there are two ways to make the clock pulse cycle faster and slower.
The operability is not necessarily good, such as the need to perform various operations.

Furthermore, in the above-mentioned digital switch method and numeral one-way system, it is not possible to limit the range of numerical values to be set, and in the up/down counter one-way system, the counter is set to a predetermined minimum and maximum value. When you take
Although it is possible to detect this with a matching circuit and prevent the counter from being driven beyond a predetermined range, this has the disadvantage that the circuit configuration becomes extremely complicated.

The present invention solves the drawbacks of the above-mentioned systems,
A sawtooth wave generation circuit that changes in synchronization with the output of the counter and a comparison voltage generation circuit that generates a comparison voltage to be compared with the output voltage of this sawtooth wave generation circuit are provided. When they match, a set pulse is generated, and the output of the counter at the time when the set pulse is generated is set in a memory element, and a sawtooth wave is generated by operating a variable resistor or variable capacitor. By changing the output waveform or comparison voltage value of the circuit, and thereby changing the generation timing of the set pulse, it is possible to set the counter output at the time of generation of the set pulse in the memory.

Further, the configuration is such that only counter outputs within a predetermined range limited by the output of the decoder that detects the specific output of the counter and the output waveform of the sawtooth wave generation circuit can be sent to the memory.

Hereinafter, the present invention will be described in detail according to embodiments shown in the drawings.

FIG. 1 shows a block diagram of a digital value cent circuit according to the present invention.

The output of a reference oscillator 1 composed of a crystal is applied to a counter 2 and counted.

A part of the output of the counter 2 is applied to a decoder 3, and the decoder 3 detects specific outputs a and b among the outputs of the counter 2.

That is, when the output of the counter 2 becomes (a), the v1 output of the decoder 3 becomes high level, and when the output of the counter 2 becomes (b), the 2 output of the decoder 3 becomes high level.

The RS flip-frog circuit 4 is set by the v1 output and the Q output v3 becomes high level, and is reset by the v2 output and the Q output (2) becomes low level.

The Q output (3) of the RS flip-flop circuit 4 is applied to the sawtooth wave generating circuit 5.

Therefore, the sawtooth wave generating circuit is changed in synchronization with the specific outputs a and b of the counter 2 detected by the decoder 3.

The set pulse generation circuit 6 compares a comparison voltage V5 set by a comparison voltage generation circuit 7 made of a variable resistor with an output voltage V4 of the sawtooth wave generation circuit east, and sets the set pulse when the two substantially match. It generates pulse ①8.

When this set pulse (8) is applied to the memory 8, the output (content) of the counter 2 at that point in time is set in the memory 8.

Further details will be given with reference to FIG. 2, which shows a specific example of the sawtooth wave generating circuit 5 and the set pulse generating circuit 6, and FIG. 3, which shows operating waveforms.

In the embodiment shown in FIG. 2, the sawtooth wave generation circuit 5 includes two insulated gate field effect transistors (hereinafter referred to as
The set pulse generating circuit 6 includes a voltage comparator 12 consisting of a differential amplifier, three inverters 13, and a capacitor 11.
13, 13 and an AND gate 14.

Now, let the oscillation frequency of the reference oscillator 1 be IMHz, and set the counter 2 as II 20 from 0 to "1999".
Let it be a counter that counts 001+.

Then, the output of counter 2 will be repeated at a cycle of 2m5eCID.

Further, the decoder 3 is a decoder that detects two specific outputs from the outputs of the counter 2, for example, 500 1700''.

Now, when the output of the counter 2 that counts the output of the reference oscillator 1 becomes It 1700 II, the decoder 3's ■
1 output becomes high level (see FIG. 3), RS flip-flop circuit 4 is set, and Q output V3 becomes high level (see FIG. 3 C).

When this 3 output is applied to the gate of the first IG-FET 10, the first IG-FET 1Q becomes conductive, and the charge that had been stored in the capacitor 11 is transferred to the first IG-FET 1Q.
It is instantaneously discharged via T10.

After that, when the output of the counter 2 reaches 500, the V2 output of the decoder 3 becomes high level (see Figure 3), the RS flip-flop circuit 4 is reset, and the Q
Output ■3 becomes low level.

(See Figure 3 C). Then, the first IG-FET 10 is reversed to a non-conducting state, and this time the second IG-FET 10 as a load resistance
A current flows through the G-FET 9 to the capacitor 11, and the capacitor 11 is charged with a time constant determined by the resistance value of the second IG-FET 9 and the capacitance value of the capacitor 11.

When the output of counter 2 becomes 1700, RS
The flip-flop circuit 4 is set and the 3 output becomes high level, the first IG-FET 10 becomes conductive, and the charge stored in the capacitor 11 is instantly discharged.

In this way, the output V4 of the sawtooth wave generating circuit 5 rises in synchronization with the specific output II 5o o II of the counter 2,
It falls in synchronization with the specific output I+ 1700It, and changes as shown in FIG. 3-2.

The output V4 of the sawtooth wave generating circuit 5 becomes one input of the voltage comparator 12, and the output V4 of the comparison voltage generating circuit 7 (see the opening in FIG. 3) becomes the other input of the voltage comparator 12.

The output V6 of the voltage comparator 12 becomes a low level when V4<■5, and becomes a high level when ■4>■ (the third
(See illustration).

The output 6 of the voltage comparator 12 directly becomes one input of the AND gate 14, while the three inverters 13, 13゜1
3 and becomes the other input V7 of AND gate 14 (see FIG. 3).

Thus, when both V6 and V7 become high level, the output 8 of the AND gate 14 becomes high level, which becomes a set pulse for the memristor 8 (see the beginning of FIG. 3).

As is clear from the above explanation, by operating the variable resistor 15 to vary the voltage value of the comparison voltage 5 (see arrow x in Figure 3), it is possible to vary the generation timing of the set pulse. By operating the variable resistor 15, one of the outputs of the counter 2, which is repeated at a cycle of 2 m5ec, can be set in the memory 8.

Next, we will explain how the range of numerical values to be set is limited.

Since the sawtooth wave ■4 is configured to rise when the output of counter 2 reaches 115001', II s o O1
A value less than 1 is never set.

That is, it is limited to a lower limit of 500.

In reality, in order to provide some margin, the lower limit value is set to a value slightly smaller than the minimum value actually required, and the sawtooth wave generation circuit 5
The output voltage does not rise from OV, but is slightly higher than OV, so a correction resistor is connected in series below the variable resistor 15, and the comparison voltage when the variable resistor 15 is operated to the minimum value is The value of OV is set to be slightly larger than OV, and the configuration is such that the minimum value that is actually required can be set at this time.

On the other hand, the upper limit of the numerical value to be set is defined by the output waveform V4 under the sawtooth wave generation circuit.

That is, the upper limit is determined by determining the resistance values of the capacitor 11 and the second IG-FET 9 so that the time when the sawtooth wave V4 reaches its peak voltage coincides with the time when the counter 2 outputs the predetermined upper limit value. Value is specified.

In reality, the tip of the sawtooth wave is rounded, so the upper limit is set to a value larger than the actually required maximum value.

Then, when the variable resistor 15 is operated to its maximum value, the value of the comparison voltage 5 is set to be lower than the maximum voltage value of the sawtooth wave, and the set pulse generated at this point causes The maximum value actually required is set in the memory 8.

Therefore, if the 10B power source of the sawtooth wave generation circuit 5 and the 10B power source of the comparison voltage generation circuit 7 are the same power source, it is necessary to connect a correction resistor in series above the variable resistor 15.

Furthermore, decoder 3 outputs the specific output of counter 2 "1700".
However, this is not necessary to define the upper limit of the set value, but is necessary to indicate the falling edge of the sawtooth wave.

Therefore, the value may be any value as long as it is in the range between the upper limit and It 1g g g II or from 0 to 500.

By configuring as described above, only the counter output within a specific range among the outputs of the counter can be set in the memory 8 in response to the operation of the variable resistor 15.

In addition, by connecting a correction resistor to the variable resistor 15, the operating range of the variable resistor and the range of numerical values to be set will completely match, and the set value will be changed during operation of the variable resistor. This prevents the operational inconvenience that the set value does not change even if the variable resistor is operated after reaching the upper or lower limit.

In the embodiment described above, the variable resistor 15 was operated to change the comparison voltage v5, but the comparison voltage v5 was set to a constant value, and the capacitor 11 in the sawtooth wave generation circuit 5 was set as a barrier pull capacitor. The generation timing of the set pulse can also be varied by changing the waveform of the sawtooth wave by varying the value (see broken line in FIG. 3).

Further, as is clear from the above explanation, although it is a problem that the tip of the sawtooth wave is blunted, the linearity is not as important as shown above, so the charging current of the capacitor 11 does not need to be a constant current.

Therefore, the second IG-FET 9 having constant current characteristics may be replaced with a resistor, or this resistor may be used as a variable resistor, and the output waveform of the sawtooth wave generating circuit 5 may be varied by operating the variable resistor. It's good as well.

In the case where the output waveform of the sawtooth wave generation circuit 5 is changed in this way, in order to limit the range of numerical values to be set, the lower limit is The value can be limited by the decoder, and the upper limit value can be limited by the output waveform of the sawtooth wave generation circuit.

In this case, even if the variable capacitor etc. in the circuit 5 is operated so that the rise of the sawtooth wave outputted from the sawtooth wave generation circuit 5 is the steepest, it will still rise to a certain comparison voltage value to some extent. Therefore, it is necessary to set the lower limit value to a value slightly smaller than the actually required minimum value.

On the other hand, when the variable capacitor, etc. in the circuit 5 is operated so that the fall of the sawtooth wave outputted from the sawtooth wave generation circuit 5 is the gentlest, the point at which the sawtooth wave reaches the peak voltage and the counter 2 The upper limit value is determined by determining the circuit constants of the sawtooth wave generating circuit 5 so that the point at which the sawtooth wave generator outputs a predetermined upper limit value coincides with the point in time when the sawtooth wave generator outputs a predetermined upper limit value. A voltage lower than the peak voltage of the wave is used as a comparison voltage, and a set pulse generated when the sawtooth wave rises to this comparison voltage writes the actually necessary maximum value smaller than the upper limit value into the memory 8. Configure.

The explanation so far has been about the case where the counter 2 is an up counter, but of course the counter 2 may also be a down counter.

In this case, the upper limit value is defined by the force decoder 1, and the lower limit value is defined by the output waveform of the sawtooth wave.

In addition, we used a sawtooth wave with a gradual rise and a steep fall to make the rise period of the sawtooth wave correspond to the change period of the counter output, but conversely, we used a sawtooth wave with a slow rise and a steep fall. The falling period of the sawtooth wave may be made to correspond to the period of change of the counter output using a method.

For example, the digital value setting circuit according to the present invention can be applied to a radio receiver called a digital synthesizer type.

What is a digital synthesizer one-way radio receiver?
The configuration is such that the local oscillation output is obtained from a phase-locked loop.

A phase-locked loop is a reference oscillator (its oscillation frequency is f).
A phase comparator compares the output of the voltage-controlled oscillator whose frequency is divided by a frequency divider (its frequency division ratio is set to 17N) and the output of the voltage-controlled oscillator (its frequency is set to fO). , a voltage signal proportional to the phase difference is taken out as a DC output through a low-pass filter, and this DC output is fed back to the voltage controlled oscillator. When this feedback loop is stable (so-called locked state), the oscillation frequency of the voltage controlled oscillator and This circuit is configured such that the relationship between the oscillation frequencies of the reference oscillator is fo=N-fr.

Therefore, in order to change the local oscillation frequency in a synthesizer receiver, it is sufficient to change the frequency division ratio of the frequency divider.

This frequency divider is commonly called a programmable counter.

Conventionally, a sweeping counter called a scan counter was connected in parallel to the programmable counter and a sweep pulse was applied to the scan counter to sweep the broadcast frequency.

In other words, since the contents of the scan counter change by applying a sweep pulse to the scan counter, the contents of the programmable counter are changed according to the output of this scan counter, and thus the frequency division ratio of the programmable counter is changed. It is.

By the way, when the digital value setting circuit according to the present invention is used, the contents of the memory 8 are applied to the programmable counter, and the contents of the memory 8 are applied to the programmable counter.
For example, by changing it by operating the variable resistor 15, it is possible to sweep the broadcast frequency.

When a radio receiver is configured for two bands, FM broadcasting and AM broadcasting, the broadcasting frequency ranges are different, so by providing a decoder and a sawtooth wave generation circuit for each band, it is possible to The broadcast frequency is 76.0
Only numbers in the range "760 to 900" corresponding to MHz to 90.0 MH21', and for AM broadcasting, broadcast frequencies "535 KHz to 605 KHz"
Only numbers in the range 535 to 1605 corresponding to can be set in memory.

According to the digital value setting circuit according to the present invention described above, the output waveform or comparison voltage value of the sawtooth wave generation circuit is changed by operating the variable resistor or the variable capacitor, thereby generating the set pulse. Since it is configured so that the counter output at the time of the set pulse generation can be set in memory by varying the timing, the digital value setting is compared to the conventional digital switch method, one-way numeric key system, and one-way up/down counter method. This has made it extremely easy.

Further, according to the present invention, only the outputs within a specific range among the outputs of the counter can be set in the memory with an extremely simple configuration.

To limit the range of numbers that can be set, counter 2
It would be fine to make the counter itself a counter that only outputs numbers within a specific range, but if two or more limited ranges are required, two counters must be provided correspondingly, making it complicated. Moreover, it is expensive.

However, according to the present invention, it is only necessary to provide a decoder and a sawtooth wave generation circuit for each limit range, which is much simpler and cheaper than the case where two counters are provided. .

Furthermore, as a method to limit the range of the set value by 1, without providing a decoder, the counter output from 0 to "1999"
For example, the sawtooth wave can be set to correspond to the output from 0 to IO.
V, and the range of change of the comparison voltage created by a variable resistor is not limited to 10cm from OV, but is limited to a narrower range of change than this, and the counter output corresponding to this narrow range of change of comparison voltage is It is also possible to set only the change range in memory.

However, in this case, the extremely narrow range of change in the comparison voltage corresponds to the range of change in the required digital value, and even a slight change in the comparison voltage results in a large change in the set digital value. Therefore, it becomes extremely difficult to operate the variable resistor so that the desired digit value is set.

According to the present invention, a sawtooth wave is caused to rise in synchronization with a predetermined output (lower limit value) detected by a decoder, and when the sawtooth wave reaches a peak voltage, the counter output reaches the predetermined upper limit value. Since the waveform of the sawtooth wave is defined as follows, the change range of the digital value corresponds to the entire voltage change range of the sawtooth wave, making it easy to operate to set the desired digital value. It is something.

In reality, as mentioned earlier, due to reasons such as the tip of the sawtooth wave being blunted, it is not possible to make the desired digit value change range correspond to the entire voltage change range of the sawtooth wave. Although this corresponds to a narrow voltage change range, it is still much easier to operate than a method that limits the change range of the comparison voltage value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital value set circuit according to the present invention, FIG. 2 is a wiring diagram showing specific examples of a sawtooth wave generation circuit and a set pulse generation circuit, and FIG. 3 is an operating waveform diagram. Explanation of main figure numbers, 1...Reference oscillator, 2...
...Counter, 3...Decoder, 4...
... Flip flow rough circuit, 5 ... Sawtooth wave generation circuit, 6 ... Set pulse generation circuit, T.
...Comparison voltage generation circuit.

Claims (1)

[Claims] 1. A counter that repeatedly outputs numerical values in a predetermined range at a constant cycle, a digital memory to which the output of this counter is set, and a set pulse that sets the digital memory to a settable state. a set pulse control means that generates the set pulse at the same period as the period of the counter and varies the generation timing of the set pulse; and a control means that limits the generation range of the set pulse, and the set pulse control means is operated. A digital value setting circuit configured to vary the generation timing of the set pulse to output the output of the counter at the time when the set pulse is generated to the digital memory. 2. The control means has a decoder that detects a specific output of the counter, and the set pulse control means changes the output voltage Va of the sawtooth wave generation circuit in synchronization with the output of the decoder. a comparison voltage generation circuit that generates a comparison voltage vb to be compared; an operating means consisting of a variable capacitor or a variable resistor for changing the output waveform of the sawtooth wave generation circuit or the comparison voltage vb; and the output voltage Va. and a set pulse generation circuit that generates a set pulse by detecting that the comparison voltage vb and the comparison voltage vb substantially match, and by operating the operating means to vary the generation timing of the set pulse, the 2. The digital value setting circuit according to claim 1, wherein an arbitrary counter output within a range controlled by the output of the decoder and the output waveform of the sawtooth wave generation circuit is set in the digital memory.