JPS5933981A - Panel type television receiver - Google Patents

Abstract

PURPOSE:To maintain the excellent lifetime characteristic of a liquid crystal panel and to reduce the power consumption, by cutting off the power supply to a liquid crystal driving circuit to prevent application of DC voltage to the liquid crystal panel in case the reception of a TV radio wave is not normal. CONSTITUTION:A turning operation is carried out to receive a TV radio wave of another channel while a liquid crystal panel 181 and an electroluminescence EL light illuminating panel 182 are driven for emission of light. As a result, no vertical synchronizing signal V SYNC is applied to a signal line 221. Then a multiplexer is made stable, and switching elements 202 and 225 are turned off via an FF222. Thus the driving is stopped for both panels 181 and 182. When the tuning operation is through with another TV radio wave, the signal V SYNC is supplied again to the line 221. Then the driving is started for the panels 181 and 182.

Description

[Detailed description of the invention] The present invention relates to a channel type television receiver.

Recently, the display quality of the dotma (IJ) type liquid crystal display for image display has improved considerably, and along with this, efforts are being made to put liquid crystal television receivers into practical use. In a television receiver using a TV, if it is not tuned to the television broadcast radio waves, the video signal is not supplied to the display section, and as a result, DC voltage is applied to the four channels of the liquid crystal display (LCD display). There is a problem of deteriorating the life of the 4-channel.

The present invention has been made in view of the above points, and can prevent DC voltage from being applied to the display panel even when it is not tuned to the TV broadcasting radio waves, thereby improving the life characteristics of the display panel. It is an object of the present invention to provide a /4' channel type television receiver that can maintain the power consumption and reduce power consumption.

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the general configuration of the television receiver, and the circuit boards include an antenna board 10, a knob plate 11, a linear board 12, a power supply circuit board 13, and a display drive control circuit board 1.
4, display drive circuit board 15, each board 10-1
5 constitutes a predetermined circuit. Still each board 10~
In addition to 15, a tuner 16, a speaker 17, and a panel-type image display device 18 are provided. As the panel type image display device 18, for example, a dot matrix liquid crystal display panel or an electroluminescent display panel is used. In this embodiment, an electroluminescent (IEL) panel is provided on the back side of the dot matrix liquid crystal display panel 181 for illumination. For example, the dot matrix liquid crystal display panel 181 may have a display dot number of 120×16.
0 double matrix method and 1/65.67
'TN (twisted nematic) driven by knee
I am using a mold.

The antenna board 10 is connected to a rod antenna 21 provided in the receiver and an external antenna connection jack. And the above rod antenna 2
Television radio waves received by the antenna 1 or an external antenna are sent to the tuner 16. The knob board 1 is still provided with a tuning knob 111 for selectively operating the television-)signal radio waves, and its operation signal is sent to a circuit configured on the linear board 12. The linear board 12 includes a tuner power supply circuit 121, a tuning control circuit 122, a filter circuit 123, a linear circuit 124,
An audio amplification circuit 125 is provided. The tuning control circuit 122 provides a tuning signal to the tuner 16 in accordance with the operation from the tuning knob 111. This tuner 16 selects the television radio waves received by the rod antenna 2 or an external antenna according to the tuning signal from the tuning control circuit 122, converts it into an intermediate frequency, and outputs it to the filter circuit 123. This filter circuit 123 passes only the frequency components of the desired channel selected by the tuner 16, and removes the frequency components of adjacent channels. Then, the linear circuit 124 amplifies the intermediate frequency signal output from the filter path 123, and then performs video detection to separate the video signal, audio signal, and synchronization signal.

The audio signal output from the linear circuit 124 is amplified by an audio amplification circuit 125, then sent to the speaker 17, and output as audio.

Further, the same signal outputted from the linear circuit 124 is sent to a circuit configured on the power supply circuit board 13,
The video signal and the synchronization signal are sent to a circuit configured on the display drive control circuit board 14.

The power supply circuit board 13 is provided with a power supply circuit 13 channel drive circuit 132, and the power supply circuit 131 supplies an operating voltage to the tuner power supply circuit 121 and a display drive power supply circuit 144 to be described later. . The gloss drive circuit 132 also supplies a synchronization signal from the linear circuit 124 and a light emission operating voltage to the EL lighting panel 182 via a communication circuit 145 formed in the display drive control circuit 14, and also supplies a light emission operating voltage to the display drive control circuit board. A switching signal is applied to the circuit configured in 14.

The display drive control circuit board 14 includes an analog/digital conversion circuit (hereinafter referred to as an A/D converter) 141,
An auto level control circuit 142, a display drive control circuit 143, and a display drive power supply circuit 144 are provided. The display drive power supply circuit 144 changes the voltage to the output depending on the switching signal from the panel drive circuit 132.
It is FF-controlled, and its output voltage is supplied as an operating power source to the display drive control circuit 143 and the display drive circuit 15 configured on the display drive circuit board 15. The auto level control circuit 142 detects the level of the video signal from the linear circuit 124 and provides an upper limit reference potential v)I and a lower limit reference potential vL to the A/D converter 144. This A/D converter 141 operates at the reference potential V
, t VL converts the video signal from the above-mentioned near circuit 124 into digital data of 4 bits and 16 gradations, and -
``Input to display drive control circuit 143.

This display drive control circuit 143 operates in synchronization with the synchronization signal from the linear circuit 124, and supplies a drive signal to the scanning side type □ pole of the dot matrix (IJ) liquid crystal display tunnel 181, and also supplies the A to the display drive circuit 151. /D converter 1
Outputs 4-bit data from 41.

As shown in FIG. 2, the display drive power supply circuit 144 is composed of a liquid crystal drive power supply 201 and a switching element 202, and is turned on and off by a switching signal from the panel drive circuit 132. Ru.

The liquid crystal driving power supply 201 has a switching element 202
Display drive control circuit 143 and display drive circuit 15 via
1. The display drive control circuit 143 has an A/
A positive/negative conversion circuit 211 that outputs the data from the D controller 141 as is or inverted, and a switch 212 that specifies the operation of this positive/negative conversion circuit 211.
, a scanning side liquid crystal drive circuit 213 which operates in response to the output of the positive/negative conversion circuit 211 and a synchronization signal from the linear circuit 124. The output of the scanning side liquid crystal drive circuit 213 is sent to the liquid crystal display panel 181 and the signal side display drive circuit 151. The positive/negative inversion circuit 211 is connected to the liquid crystal display. This is to obtain a positive or negative video signal in accordance with the function of the channel 181.

Further, the signal side display drive circuit 151 is constituted by first to fourth four chips 311L to 31d, and is configured to drive the signal side of the liquid crystal display panel 181 according to 4-bit data from the scanning side liquid crystal drive circuit 213. Drive the electrodes.

Next, the details of the above /'P channel drive circuit 132 will be explained in the third section.
This will be explained with the help of a diagram. In the figure, 22 is a signal line to which the vertical synchronizing signal 2.5YNC separated from the video signal in the linear circuit 124 is applied. Then, the vertical synchronization signal v given to the signal line 221
-5YNC is input to the set terminal S of the R-8 flip-flop 222, and is also input to the trigger terminal T of the retriggerable multi-novel oscillator 223.

This multi-by-break 223 has an output time width set to be sufficiently long than the synchronization of the vertical synchronization signal v and 5YNC, and its Q side output is set to a timing signal φ having a predetermined time width.
, and are input to the AND circuit 224. The output of this AND circuit 224 is sent to the flip-flop 222 as a set signal'. Then, the Q side output of this free-lag frog 222 is turned on and off to the switching element 225.
Sent as an off control signal. The above switching element 2
25 is provided between the EL drive circuit 227 and a DC power supply 226 of, for example, 100 cm, which is made by boosting the battery voltage.
Controls on/off of power supply to the L drive circuit 227. The EL drive circuit 227 AC drives the KL illumination/armpit 182 in synchronization with the clock pulse when the DC power supply 226 is supplied. In addition, the above frig floc f
The Q side output of 222 is sent to the liquid crystal display driving power supply circuit 144 as an on/off control signal. This display driving power supply circuit 144 is connected to the liquid crystal driving DC power supply 2 as described above.
A switching element 202 is provided in series with 01, and this switching element 202 is controlled on/off by the output of the free-lag frog '222. The DC power supply 201 is supplied via the switching element 202 to the liquid crystal drive circuit 203 and 9, the display drive control circuit 143, and the signal side display drive circuit 16 to drive the liquid crystal display 9 and the signal side display drive circuit 16. fti control is performed.

In the above configuration, the tuning knob 11 in FIG.
When the chainer 16 is tuned to the required TV radio wave by the tuning operation in step 1, the vertical synchronizing signal V-5YNC is applied to the linear circuit 124 and the signal line 221, and the free lag flop 222 is set and its output becomes 1#. , the switching elements 202 and 225 are turned on. When the switching element 202 is turned on, the DC power supply 2
01 is supplied to the liquid crystal drive circuit 203, and the liquid crystal display panel 181 is driven for display.

Further, when the switching element 225 is turned on, the DC power supply 226 is supplied to the EL drive circuit 227. This E
When the L drive circuit 227 is supplied with the DC power supply 226,
The EL lighting panel 182 is AC driven in synchronization with the clock pulse to emit light. The television screen is displayed in monochromatic color due to the light emission from the EL lighting panel 182.

On the other hand, the vertical synchronizing signal V-5YNC given to the No. 46 line 221 is input to the retriggerable multivibrator 223.
trigger. As described above, this multivibrator 223 has an output time width of the vertical synchronizing signal V −5YN
Since the synchronization time of C is set to be sufficiently long, the trigger state is maintained as long as the vertical synchronization signal V.5YNC is normally applied. While this multivibrator 223 is held in the triggered state, its Q side output becomes ``0#'' and closes the dart of the AND circuit 224. Therefore, the timing Nobuhide') is given to the AND circuit 224. Even if the output of the AND circuit 224 is held at '0', the free lag flop 222 is not reset. As a result, while the vertical synchronizing signal V°·5YNC is normally applied, the liquid crystal display panel 18 is driven for display and the EL illumination channel 182 emits light.

Therefore, as described above, the liquid crystal display panel 181 and the EL
In a state where the lighting panel 182 is driven to emit light,
When a tuning operation is performed to receive TV radio waves from other channels and the vertical synchronizing signal V-5YNC is no longer applied to the signal line 221, the multivibrator 223 returns to a stable state and its Q side output becomes "1".
and is input to the AND circuit 224. Therefore, when the timing signal φ5 is given to the AND circuit 224, the output of the AND circuit 224 becomes "1#", and the flip controller f
222 is reset. This is Shiflip Flora f
The output of 222 becomes 10" and the switching element 202
Turn off ゜225. As a result, the liquid crystal drive circuit 203 and the EL drive circuit 227 are connected to the liquid crystal display channels 181, E
The driving operation for the L lighting panel 182 is stopped.

When the tuning operation for other TV radio waves is completed, the vertical synchronization signal VSYNC is again input to the signal line 221, and as a result, as described above, the liquid crystal drive circuit 203 and the EL drive circuit 227 Driving of the liquid crystal display panel 181 and the EL illumination panel 182 is started. That is, while receiving TV waves, the liquid crystal display panel 181 and EL lighting panel 182 are driven, and when TV waves are not being received normally, such as when tuning other channels, the liquid crystal display panel 182 is driven.
81 and the EL lighting panel 182 are stopped to reduce power consumption. If you operate the liquid crystal drive circuit 203 when TV radio waves are not yet being received, a DC voltage will be applied to the liquid crystal display panel 181, so if TV radio waves are being received normally as described above, the liquid crystal display will By cutting off the power to the drive circuit 203, application of DC voltage to the liquid crystal display panel 18 can be prevented. In this liquid crystal display panel 181, the alignment film can be formed thinly, and the contrast can be increased.

As described above, according to the present invention, it is possible to prevent DC voltage from being applied to the display panel even when not tuned to TV radio waves, maintain good life characteristics of the display panel, and maintain power consumption. It is possible to provide a glossy panel television receiver that can reduce consumption of.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram showing the general configuration of a television receiver;
FIG. 2 is a block diagram showing details of the display drive control circuit board, display drive circuit board, and display device portion, and FIG. 3 is a configuration diagram showing details of the glossy drive circuit and display drive power supply circuit portion. 10... Antenna board, 11... Knob board, 12
... Linear board, 13... Power supply circuit board, 14...
- Display drive control circuit board, 15... Display drive circuit board, 202, 225... Switching element, 222...
・Free lag flop, 223... Retriggerable multi-high flake.

Claims (1)

[Claims] In a television receiver that displays images using a display/main panel, a power supply for driving a display panel, a display panel drive circuit to which this power supply is supplied as an operating voltage and drives the display panel according to a video signal; A switching element is provided in series between the display panel drive circuit and the power supply, and a synchronization signal detection means for detecting a synchronization signal from received television radio waves, What is claimed is: 1. A lapel type television receiver comprising means for holding a switching element in an on state and turning off the switching element when the synchronization signal is not detected for a preset period.