JPS5933908A - Signal interrupting circuit - Google Patents

Signal interrupting circuit

Info

Publication number
JPS5933908A
JPS5933908A JP57142841A JP14284182A JPS5933908A JP S5933908 A JPS5933908 A JP S5933908A JP 57142841 A JP57142841 A JP 57142841A JP 14284182 A JP14284182 A JP 14284182A JP S5933908 A JPS5933908 A JP S5933908A
Authority
JP
Japan
Prior art keywords
circuit
signal
transistor
state
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57142841A
Other languages
Japanese (ja)
Inventor
Kazuo Aoki
一男 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57142841A priority Critical patent/JPS5933908A/en
Publication of JPS5933908A publication Critical patent/JPS5933908A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To attain the sufficient suppression up to a high frequency signal, by operating a switching element so as to attenuate an output signal to an amplifier means and making successively plural amplifier elements of the amplifier means into non-operating state. CONSTITUTION:A switching circuit 4 consists of resistors (R)1, R2 and a transistor (TR)1, an amplifier circuit 5 comprises R3-R10, a capacitor (C)2 and the TRs 2, 3 and an output stage circuit 7 is made up of R11, R12, C3, C4, TR4 and TR5. A voltage almost equal to ground potential is given from a synchronism detecting circuit 3 to the circuit 4 under a normal state and the TR1 is brought into non-operating state. Thus, a signal transmitted from a phase synchronism oscillating circuit 2 is amplified at the TRs 2, 3 and outputted via the circuit 7. A negative base potential is given from the circuit 3 to the TR1 under the state of out of synchronism and the TR1 is brought into the operating state. Then, the signal of the circuit 2 is absorbed in the TR1 and the TRs2- 5 are brought into nonconductive state and cut off at the same time.

Description

【発明の詳細な説明】 本発明は入力信号の異常検出時にその入力信号を低下さ
せるとともに出力信号を遮断する信号遮断回路に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal cutoff circuit that lowers the input signal and cuts off the output signal when an abnormality is detected in the input signal.

従来、信号遮断回路は、位相同期回路等の異常検出時に
その出力を遮断するために使用されている。
Conventionally, a signal cutoff circuit has been used to cut off the output of a phase synchronized circuit or the like when an abnormality is detected.

第1図は従来回路を示すブロック図であシ、位相同期発
振器2の同期外れを同期外れ検出回路3によシ検出して
アラーム信号を発生し、このアラーム信号をエミッタま
たはコレクタにリレー几りが接続されたトランジスタT
Rのベースに供給し1て、リレー几りを動作させ、これ
によシ、増幅回路5の後段に設けた接点回路4内のリレ
ー接点を開状態とし、発振器2から9出力信号が端子6
から後段の回路に伝達されるのを防止している。
FIG. 1 is a block diagram showing a conventional circuit, in which out-of-sync detection circuit 3 detects out-of-sync of phase-locked oscillator 2, generates an alarm signal, and relays this alarm signal to the emitter or collector. A transistor T connected to
1 to the base of the oscillator 2 to operate the relay, thereby opening the relay contact in the contact circuit 4 provided after the amplifier circuit 5, and the output signal from the oscillator 2 to the terminal 6.
This prevents the signal from being transmitted to subsequent circuits.

このように、リレーRLを用いた接点回路4を有する従
来回路では、高周波信号に対してリレーの接点間の容量
が影響し、リレーの接点が開放している状態にもかかわ
らず、増幅回路5によシ増幅された出力信号の一部が出
力側端子6に漏洩し、充分な出力信号の抑圧が得られな
いという欠点がある。
In this way, in the conventional circuit having the contact circuit 4 using the relay RL, the capacitance between the relay contacts affects the high frequency signal, and even though the relay contacts are open, the amplifier circuit 5 A part of the amplified output signal leaks to the output terminal 6, and the output signal cannot be suppressed sufficiently.

本発明の目的は上述の欠点を除去した信号遮断回路を提
供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal cutoff circuit which eliminates the above-mentioned drawbacks.

本発明の回路は、複数の増幅素子を有する増幅手段と、
スイッチング素子を有するスイッチング手段とを含み、
該スイッチング素子を動作させることKよシ前記増幅手
段への出力信号を減衰させるとともに前記増幅手段の複
数の増幅素子を順次非Mib作状態にするよう構成され
ている。
The circuit of the present invention includes an amplifying means having a plurality of amplifying elements;
a switching means having a switching element;
By operating the switching element, the output signal to the amplifying means is attenuated, and a plurality of amplifying elements of the amplifying means are sequentially brought into a non-Mib operating state.

次に本発明について図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.

第2図は本発明の一実施例を示すブロック図であシ、参
照数字1は入力端子、同数字2は、位相同期発振回路、
同数字3は同期外れ検出回路、同数字4はスイッチング
回路、同数字5は増幅回路、同数字6は出力端子である
FIG. 2 is a block diagram showing an embodiment of the present invention, in which reference numeral 1 is an input terminal, numeral 2 is a phase synchronized oscillation circuit,
The same number 3 is an out-of-sync detection circuit, the same number 4 is a switching circuit, the same number 5 is an amplifier circuit, and the same number 6 is an output terminal.

図において、本実施例は通常状態では、位相同期発振回
路2の出力信号はスイッチング回路4を介して、増幅回
路5で増幅され、出力端子6に送出されるが、同期外れ
の状態では、同期外れ検出回路3から同期外れのアラー
ム信号がスイッチング回路4に与えられ、位相同期発振
回路2から送出された信号を阻止するとともに、増幅回
路5の増幅機能を停止させ、出力端子6への出力信号を
完全に遮断するよう構成されている。
In the figure, in the normal state, the output signal of the phase-locked oscillation circuit 2 is amplified by the amplifier circuit 5 via the switching circuit 4, and sent to the output terminal 6. An out-of-synchronization alarm signal is given from the out-of-sync detection circuit 3 to the switching circuit 4, which blocks the signal sent out from the phase-locked oscillation circuit 2, stops the amplification function of the amplifier circuit 5, and outputs the output signal to the output terminal 6. It is configured to completely block out

第3図は第2図のスイッチング回路4と増幅回路6とを
詳細に示したブロック図であり、第2図と同一参照数字
は同一構成要素を示す。図において、スイッチング回路
4は、抵抗器R1およびR2とトランジスタTRIとか
ら構成され、増幅回路5は、抵抗器R3〜RIOとコン
デンサC2とトランジスタT It 2およびTR3と
から構成され、出力段回路7は、フ9ツシープル回路を
構成する抵抗器R11およびR12とコンデンサC3お
よびC4とトランジスタ′1°R4およびTR5とから
構成されている。
FIG. 3 is a block diagram showing in detail the switching circuit 4 and amplifier circuit 6 of FIG. 2, and the same reference numerals as in FIG. 2 indicate the same components. In the figure, a switching circuit 4 is composed of resistors R1 and R2 and a transistor TRI, an amplifier circuit 5 is composed of resistors R3 to RIO, a capacitor C2, and transistors T It 2 and TR3, and an output stage circuit 7 is composed of resistors R11 and R12, capacitors C3 and C4, and transistors '1°R4 and TR5, which constitute a fuselage circuit.

図において、通常状態では、同期外れ検出回路3からス
イッチング回路4に接地電位にほぼ等しい電圧が与えら
れており、トランジスタTRIのベース電位は、それの
エミッタ電位とほぼ静しい電位のため、トランジスタT
R1は非動作状態にあシ、そのコレクターのインピーダ
ンスは無限大となっている。このため、位相同期発振回
路2から送出された信号は直流阻止用コンデンサC1を
通して、抵抗器几3およびR4によシ分圧された通常の
バイアスを与えられたトランジスタTR2のベースに人
力され、トランジスタTR2およびT■モ3にニジ増幅
されたあと、トランジスタTR4およびT R5を含む
インピーダンス変換回路7に↓υ低1゛ンビーダンス変
換さ゛れ、コンデンサC4を通して出力端子6から出力
される。
In the figure, in a normal state, a voltage approximately equal to the ground potential is applied from the desynchronization detection circuit 3 to the switching circuit 4, and the base potential of the transistor TRI is approximately a static potential with respect to its emitter potential, so the transistor T
R1 is inactive and the impedance of its collector is infinite. Therefore, the signal sent from the phase-locked oscillator circuit 2 is passed through the DC blocking capacitor C1 to the base of the transistor TR2, which is given a normal bias voltage divided by the resistors 3 and R4. After being amplified by TR2 and TMO3, it is subjected to ↓υlow 1 impedance conversion by an impedance conversion circuit 7 including transistors TR4 and TR5, and is output from an output terminal 6 through a capacitor C4.

−力、同期外れの状態では、同期外れ検出回路3によシ
同期外れが検出されると、検出回路3から適当な負の電
位がスイッチング回路4のトランジスタi’ R1のベ
ースに与えられ、そのベース電位がエミッタ電位より低
くなシトランジスタllI几1 vi動作状態となる。
- When the out-of-sync state is detected by the out-of-sync detection circuit 3, an appropriate negative potential is applied from the detection circuit 3 to the base of the transistor i'R1 of the switching circuit 4, and the The transistor is in an operating state in which the base potential is lower than the emitter potential.

この結果、トランジスタTRIのコレクターのインピー
ダンスはほぼ零となシ、位相同期発振回路2から送出さ
れた出力信号は、コンデンサC1を通ったあと、トラン
ジスぞTR,1に吸収される。
As a result, the impedance of the collector of the transistor TRI becomes almost zero, and the output signal sent from the phase synchronized oscillation circuit 2 is absorbed by the transistor TR,1 after passing through the capacitor C1.

また、同時に、トランジスタTRIのコレ2ターのイン
ピーダンスがは#丁零になるため、トランジスタ’ra
2のベース電位が接地電位にほぼ等しくなシ、このため
、トランジスタT If、 2のエミッタ電位は接地電
位に、コレクターは負の印加電圧となシ、トランジスタ
T R2は非動作状態となる。
At the same time, since the impedance of the collector of transistor TRI becomes zero, the transistor 'ra
Since the base potential of the transistor T If,2 is approximately equal to the ground potential, the emitter potential of the transistor T If,2 is at the ground potential, the collector is at a negative applied voltage, and the transistor T R2 becomes inactive.

これにより、トランジスタ’I”R3の直流1ぽ位もト
ランジスタ’1’ It 2と同様に変化し、トランジ
スタTIt4とTut、2のエミッタ電位は、はぼ負の
電位の1/2から接地電位に変化して、トランジスタT
 I(、2〜1゛几5 i、J:全て非動作状態となり
、増幅回路5の増幅機能は完全に停止されるため、位相
同期発振回路2から送出された信号は、出力端子6に与
えられずに、完全に遮断される。
As a result, the DC 1 potential of the transistor 'I'R3 changes in the same way as the transistor '1' It2, and the emitter potential of the transistors TIt4, Tut, and 2 changes from approximately 1/2 of the negative potential to the ground potential. Change, transistor T
I(, 2 to 1゛几5 i, J: All become inactive, and the amplification function of the amplifier circuit 5 is completely stopped, so the signal sent from the phase synchronized oscillation circuit 2 is not applied to the output terminal 6. completely blocked.

本実施例では、増幅回路5とブツシュ・プル回路からな
るインピーダンス変換回路との構成で説明したが、必要
に応じてブツシュ・プル回路を除去してもよい。
Although the present embodiment has been described with the configuration of the amplifier circuit 5 and the impedance conversion circuit consisting of the bushing-pull circuit, the bushing-pull circuit may be removed if necessary.

以上、本発明にはトランジスタによるスイッチング回路
に加えて同時に、後段の増幅回路の増11)機能をも停
止させる動作を行なうため、高周波の信号まで充分な抑
圧を達成でき、さらにリレー回路を用いないため回路の
簡素化および信頼性の向上を達成できるという効果があ
る。
As described above, in the present invention, in addition to the switching circuit using transistors, the function of the amplifier circuit in the subsequent stage is also stopped at the same time, so that it is possible to achieve sufficient suppression of even high-frequency signals, and furthermore, it does not use a relay circuit. This has the effect of simplifying the circuit and improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の信号遮断回路を丞すブロック図、第2図
は本発明の一実施例を示うノロック図および第3図は第
2図の祥細なブロック図である。 図において、1・・・・・・入力端子、2・・・・・・
位相同期発振回路、計・・・・・同期外れ検出回路、4
・・・・・・スイッチング回路、5・・・・・・増幅回
路、6・・・・・・出力端子、7・・・・・・出力段回
路。 夢 2 図
FIG. 1 is a block diagram of a conventional signal cutoff circuit, FIG. 2 is a Norlock diagram showing an embodiment of the present invention, and FIG. 3 is a detailed block diagram of FIG. 2. In the figure, 1... input terminal, 2...
Phase-locked oscillation circuit, total...out-of-synchronization detection circuit, 4
...Switching circuit, 5...Amplification circuit, 6...Output terminal, 7...Output stage circuit. dream 2 diagram

Claims (1)

【特許請求の範囲】[Claims] 複数の増幅素子を有する増幅刊曲手段と、スイッチング
素子を有するスイッチング手段とを含み、該スイッチン
グ素子を動作させることによシ前記増幅手段への出力信
号を減衰させるとともに前記増幅手段の複数の増幅素子
を順次非動作状態にすることを特徴とする信号遮断回路
It includes an amplifying means having a plurality of amplifying elements, and a switching means having a switching element, and by operating the switching element, the output signal to the amplifying means is attenuated and the plurality of amplifying means of the amplifying means are attenuated. A signal cutoff circuit characterized by sequentially putting elements into a non-operating state.
JP57142841A 1982-08-18 1982-08-18 Signal interrupting circuit Pending JPS5933908A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57142841A JPS5933908A (en) 1982-08-18 1982-08-18 Signal interrupting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57142841A JPS5933908A (en) 1982-08-18 1982-08-18 Signal interrupting circuit

Publications (1)

Publication Number Publication Date
JPS5933908A true JPS5933908A (en) 1984-02-24

Family

ID=15324853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57142841A Pending JPS5933908A (en) 1982-08-18 1982-08-18 Signal interrupting circuit

Country Status (1)

Country Link
JP (1) JPS5933908A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045726A (en) * 2008-08-18 2010-02-25 Sharp Corp Signal amplification apparatus and signal processing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5155655A (en) * 1974-11-11 1976-05-15 Sanyo Electric Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5155655A (en) * 1974-11-11 1976-05-15 Sanyo Electric Co

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045726A (en) * 2008-08-18 2010-02-25 Sharp Corp Signal amplification apparatus and signal processing method

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