JPS5933693A - Sense circuit - Google Patents

Abstract

PURPOSE:To obtain a miniature and a high-speed sense circuit,by controlling a transfer gate transistor with feedback of the output of an amplifying circuit and at the same time amplifying the voltage change of an input signal by feeding it back to an input node. CONSTITUTION:A precharge timing signal phi is set at a high level in a stand-by state, and a bit/sense line 11 and an input nod 15 are precharged up to a high level. When the signal charge is transferred, the line 11 feeds a minute signal A of a low level to a sense circuit. An amplifying circuit 13 amplifies the signal A and delivers a signal B. The signal B is supplied to the gate of a transistor TR17, and therefore the line 11 and an output node 18 approximate to a low level and a high level respectively. At the same time, the load capacity to be discharged from the TR17 is limited only to CS. The sense circuit works at a high speed if the CS is set at a sufficiently low level. In such a way, the miniature and high-speed sense circuit is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a small and high-speed sense circuit in a semiconductor integrated circuit.

2. Description of the Related Art In semiconductor integrated circuits such as semiconductor memory devices and semiconductor photodetector devices (d), sense circuits are used throughout to detect and amplify minute voltage drops and increases to generate signals at desired voltage levels. With these device improvements, the amount of signal charge transferred from the memory cell or the light receiving cell onto the bit/sense line is small, and the voltage change on the bit/sense line, which has a large negative GJ capacity, is gradual and slight. Therefore, the operating speed of the sense circuit is 6. [This is an important factor in increasing the speed performance of the device.]

One way to speed up the sense circuit is to perform the readout from the cell to the bit/sense line and the operation of the J9"4 circuit at different timings, and reduce the load capacitance of the bit/sense line when operating the RQ width circuit. A sense circuit has been proposed that is configured to cut d.

FIG. 1 shows an example of a sense circuit of this type, which is composed of MO8 type field effect transistors. 1 is a bit/sense line, 2 is a clip-flop type jvI width circuit, 3 is a transfer gate transistor to disconnect the load CB of the bit sense line from the input node 4 of the amplifier circuit, and φ1 is a bit/sense IN l preamp. Charge and amplifier circuit 2
The reset timing signal φ2 is the operation timing signal of the amplifier circuit 2. φ3 is a timing signal that controls conduction/non-conduction of transistor 3, and transfers signal charge onto bit/sense line 1 during precharging.
During the period 91, the signal is set to low level, and during the period when the amplifier circuit 3 operates, the signal is set to low level. As a result, the load capacitance during operation of the amplifier circuit 3 is limited to the load capacitance C8 of the node 4, and high-speed 7-rip, 70-tube operation is possible.

However, in this type of circuit h1, it is necessary to supply the timing signal φ3 externally, and it is necessary to add a signal generation circuit ν1 and supply wiring for this purpose.
This is disadvantageous for downsizing the device. Also, when supplying the control timing φ3 in common to multiple sense circuits, bit/
It is difficult to provide the timing I8 of the control timing signal φ3 corresponding to variations in the transfer time of signal charges onto the sense line, and it is difficult to provide the timing I8 with sufficient timing margin. blJ (+iil timing signal φ3 must be designed. This method of using a timing signal to take into consideration the load on the bit/sense line makes circuit design difficult and unnecessarily slows down the production speed. The disadvantage is that it is slow.

The present invention aims to eliminate such drawbacks and provide a small and high-speed sense circuit.The present invention is characterized by the fact that it is provided between the bit/sense line and the input node of the Jj floor 11-4 circuit. The transferred transfer gate transistor is
The two methods are to feed back the output of the amplifier circuit and increase it by +1ilJ (+i41), and to feed back the output of the amplifier circuit to the input node to increase the voltage change of the human signal.

In order to achieve the above object, this book 1 includes an amplifier circuit for converting signal A into signal B, a signal input terminal, and j'17.
a first field effect transistor whose source and drain are connected to the input node of the width circuit; and whose source and drain are connected to /1il between the ground terminal and the input node of the amplification circuit h'6. a second field effect transistor; a third field effect transistor having a source and a drain connected between an input node of the amplifier circuit and a power supply terminal; In this case, a signal C for cutting off the first field effect transistor out of the signal B4 or its logical inversion signal is input to cut off the first field effect transistor, and the signal C is cut off to the gate of the second field effect transistor or the third field effect transistor. On one side of the gate,
To precharge the manual node of the amplifier circuit (
No. N is manually operated, and the other gate is connected to the signal C.
The gist of the invention is a sense circuit characterized in that it is constructed so that the 11th logical inversion (No. 8 of N. 8) is manually operated.

Next, an embodiment of the present invention will be described with reference to the attached 1 m 1 surface.

It should be noted that the embodiment is merely an illustration, and it goes without saying that the glaze may be changed or improved without departing from the spirit of the present invention.

Figure 2 shows how to use MO8 type field effect transistors.
This is an embodiment of the present invention, and is a sense circuit for detecting that a human input signal changes from a high level to a low level.

In the figure, 10 is a sense circuit, 11 is a bit/sense line, 12 is a signal input terminal of the sense circuit, 13 is an inverter type amplifier circuit, and 4 is a load capacity 5 of the bit/sense line.
1 cB and the load capacitance of the input node 15 of the amplifier circuit 13 is 0
8, a transfer gate transistor for disconnecting from the 16il''L precharge transistor controlled by the precharge timing signal φ, and 17 an amplifier circuit 1.
This is a transistor that controls the discharge of the human power node 15 with the output of 3.

Reference numeral 18 indicates an output node of the amplification circuit 13.

Next, the operation of this circuit will be explained.

In the standby state, the precharge timing signal φ is at a high level, the bit/sense 1jll and the human power node 15 are precharged to a high level, and the transistor 14 is on. Further, the output node 18 of the amplifier circuit 13 is at a low level, and the transistor 17 is cut off.

When a read operation begins, the signal φ is at a low level, and the bit/sense a11 and input node 15 are floating at a high level. If no signal charge is transferred to the bit/sense line, the sense circuit does not operate and remains in the same state. If the signal charge is transferred, the bit/sense line inputs a minute low level signal A to the sense circuit. Amplifier circuit 1
3 amplifies the minute signal A and has a large logic amplitude and t'1
Outputs signal B (high level) of ili + logic inversion to node 1
Output to 8. Since the signal B is input to the gate of the transistor 17, the input node and the bit/sense line are set to low level by a flip-flop-like operation.
Output node 18 approaches high level ITI.

At the same time, the signal at input node 15 causes transistor 1 to
4 is cut off, the load capacitance CB of the bit/sense line 11 is disconnected from the input node 15, and the negative j capacitance to be discharged by the transistor 17 becomes only C8. C.B.
If the value is set sufficiently small, the discharge of the manual node 15 will be faster, and the sense circuit? It operates at a speed of +<r, outputs digital signals B and 100, and becomes stable.

FIG. 3 shows a configuration in which the output B of the amplifier circuit 13 in FIG. 2 is fed back to the gate of the transistor 14 through an inverter type buffer circuit 20. The operation is similar to that of the embodiment shown in FIG. 2, and the explanation of gi'-&+I will be omitted. In this embodiment, the signal applied to the gate of transistor 14 is independent of the voltage at its drain, and transistor 14 remains on until the voltage at input node 15 is sufficient to operate amplifier circuit 13.

In the above two embodiments, the bit/sense line load capacity (j
)'H,' The characteristic is that the CB is disconnected by itself and the input node of the amplifier circuit is quickly discharged.

FIG. 4 shows another embodiment of the present invention constructed using MO8 type field effect transistors, and is a sense circuit for detecting that an input signal changes from low level to high level.

30 is a sense circuit, 31 is a bit/sense line, 32 is a signal input terminal of the sense circuit, 33) J is an inverter type amplifier circuit, 34 is the load capacitance CB of the bit/sense line and the load of the human power node 35 of the amplifier circuit. Capacity C! B(!: Transfer gate transistor must be turned off, 36
37 is a transistor for precharging which is controlled by a precharge timing signal φ; 37 is a transistor which controls the charging of the human power node 35 with the jiij inverted digit of the output of the amplifier ll'iA circuit 33; and 39 is an inverter circuit.

Next, the operation of this circuit will be explained.

In the standby state, precharge timing signal φ is at high level, and bit/sense line 31 and input node 35 are precharged to low level. Therefore, the output node 38 of the stomach width circuit 33 becomes high level, the transistor 34 is turned on, and the transistor 37 is cut off.

When the draining operation begins, the signal φt goes to low level, and the bit/sense fdQ31 and input node 35t float at low level. If no signal charge is transferred to the bit/sense line, the sense circuit does not operate and remains in the same state.

If a signal charge is transferred and a minute high level signal A is generated on the bit/sense line, the amplifier circuit amplifies this and outputs a logic inverted signal B (low level) with a large logic amplitude to the output node 38. do. Since No. 46 B is connected to the gate of the transistor 34, when the signal B drops near the output voltage 1, the load capacitance CB of the bit/sense line 31 (l''L input capacitor node 35 disconnects) It will be done.

At the same time, a signal from the output of the inverter 39 is applied to the gate of the transistor 37, and the transistor 37 is turned on to charge the power source 35. Load each set of human power node 35
Since it is small with only C8, the filling is done quickly,
The human power node 35 becomes ;1j44 k'l high level.

The above operation stabilizes the sense circuit and outputs digital signals B and 100.

In this way, in this embodiment, the bit/sense line load is automatically cut off at the rising edge of the signal input to the sense circuit, and the manual node of the amplifier circuit can be quickly connected. It is characterized by the fact that it tries to be full.

As explained above, the present invention can be applied to both cases where the input 4j changes from high level to low level and when it changes from low level to high level, and similar effects can be obtained. .

Furthermore, the above embodiment is a single channel enhancement type M
Is it a case where it is composed of O8 type field effect transistors?
This can also be realized in N shares by using complementary MOS 3 field effect transistors. An example of this is shown in FIG. 5, which is a circuit that detects a change in the input signal from a high level to a low level. 54 is the negative bit/sense line WJ”
41 N, CB, and human power node 15 of the width circuit I3
This is a transfer gate for cutting off the load capacitance Cs of , and consists of a p-channel transistor and an n-channel transistor. Reference numeral 56 denotes a p-channel transistor for precharging the human canode 5, which is set to 1llll by the precharging timing signal γ which becomes low level during standby.
Il111 will be sent.

'In addition, a timing signal φ that becomes low level when the bladder is expelled is input to the gate of the channel transistor 57 in the jf1 width circuit, so that the increase 11
By preventing blood flow current in the B and i circuits, the complementary MO8) transistor circuit effectively achieves low power consumption.

The operation of this circuit is similar to that of the embodiment shown in FIG.
Although detailed explanation is omitted, a p-channel transistor,
This can be easily understood from the fact that n-channel transistors operate in a similar manner by applying reverse Ni+i signals to their gates.

In the above embodiments of the present invention, 'c, iI'IV41 times J
h'F uses an inverter type, but even more sensitive differential j+:! It is also possible to use a width circuit or the like. In addition, the input node precharge can also be of a static type instead of a dynamic type.

As explained above, the present invention reduces the load demand of the bit/sense line and the two nodes of the amplifier circuit by 1'iiU, and increases Using the input timing, the timing signal and the timing signal for operating the amplifier circuit are automatically set in the sense circuit without cutting off the negative capacitance (which is necessary for conventional sense circuits). There is no need to supply it externally, and the timing signal generation circuit and signal supply wiring can be saved, which is effective in downsizing the device.

Furthermore, even if there is a time difference in reading signals to multiple bit/sense lines, each sense circuit operates individually.
It is easier to set the timing, and the crystallization speed of the bladder can be increased.
The design process can be shortened.

In this way, using the sense 1 #'i) of the present invention
This has the advantage of increasing the output speed of the semiconductor memory device (or semiconductor variable device I'tU) and reducing the size of the device.

[Brief explanation of drawings]

Fig. 1 is an example of a conventional sense circuit, Fig. 8112c, j is a sense circuit hh that imprints the change in human power from a high level to a low level in an embodiment of this Komei, and Fig. 3 is an example of a 4tt+ of the present invention. This is an embodiment of the sense circuit in which the embodiment of FIG. Sense times FF), Figure 5? ,I: i:,
j'; 1. shows an embodiment in which the embodiment shown in FIG. 3 is constructed using complementary Mos transistors. 1.11.31--bit/sense line, 10.30...
・Sense circuit, 2, 13. 33... Amplifier circuit, 3゜1
4.34.54...Bit/sense line load capacitance disconnection transformer 7 agate transistor, 16°36.5
6...Amplification circuit input cathode node relay transistor, 17.37...:11,111119. Transistor for charging the B circuit input node, 15.35.
...Input node of the amplifier circuit, 18...Deba node of the amplifier circuit, 12゜32...Signal-U power terminal, 39...Inverter circuit, stone 7...11 N-channel transistors. Figure 2 Figure 3 Figure 0 Figure 4

Claims (1)

[Claims] an amplifier circuit that converts signal A into signal B; a first field effect transistor having a source and a drain connected between a signal input terminal and an input node of the amplifier circuit; and a ground terminal and the input node of the amplifier circuit. a second field effect transistor whose source and drain are connected to the node; and a third field effect transistor whose source and drain are connected between the input node and the power supply terminal of the amplifier circuit. A signal C for canting off the first field effect transistor among the signal B or its inverted signal is inputted to the gate of the first field effect transistor, and the signal C for canting off the first field effect transistor is input to the gate of the first field effect transistor. One of the gate of the field effect transistor or the gate of the third field effect transistor is provided with the following: 1. +r 'l' A signal for precharging the input node of the M circuit is inputted, and a logical inversion signal of the signal C is inputted to the other gate of the gate. sense circuit.