JPS5933262B2 - Channel thickness measurement method for semiconductor devices - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for measuring impurity concentration of a semiconductor device.

MIS in which a channel of an opposite conductivity type is provided on one inner surface of a semiconductor substrate of one conductivity type, a source region and a drain region are provided on both sides of the channel, and at least one electrode is provided on the semiconductor substrate via an insulator layer. This structure is well known in semiconductor devices such as MOS transistor CCD.

Conventional C-V method (G.

5W, Taylor, SolidStateElect
ron-19, 459, 1976) is used.

However, this CV method has the following drawbacks. 1. For example, it is difficult to measure by the CCD itself due to resistance and stray capacitance due to a long channel such as a CCD.

2. There are drawbacks such as large measurement errors.

The present invention has been made in view of the above-mentioned points, and provides a method for measuring the thickness of a channel of a semiconductor device '5, which allows non-destructive measurement of the thickness of a channel with a small error even with a CCD.

That is, the present invention measures the voltage (VBso) between the source region and the semiconductor substrate of the semiconductor device, and calculates the voltage (VBso) from the following equation D: [2εSilV
bi-VBSOI/eNC)″20+(Ns+Nc))
2] is the measurement method to obtain the channel thickness of the channel.

Next, an example will be described in which the method of the present invention is applied to thickness measurement of a 5-channel embedded channel type CCD.

One conductivity type semiconductor substrate, for example, impurity concentration (Ns) is 1.2
5×1015/(V7l2) A channel of a conductivity type different from that of the substrate 1, for example, an impurity concentration (
An n-type buried channel 2 with NO) of 1.31×10 16 /C:Fl2 is provided, a source region 3 on one inner surface of the substrate 1 is provided so as to supply charge to the channel 2, and the charge from the channel 2 is A drain region 4 is provided on the inner surface of the substrate 1 so as to receive the drain region 4, and an insulating layer, for example, with a dielectric constant (ε0x) of 3.8×8.85× is provided on the substrate 1 on the channel 2.
10-12 [Fualad/c:r! The thickness of the channel 2 of the embedded channel type CCD 7 is as follows: a SiO2 film 5 of 1) is formed to a thickness of, for example, 1200 mm, and at least one electrode, for example, a large number of transfer electrodes 6 are provided through the SiO2 film 5. Measure as follows. The dielectric constant (ε81) of the p-type Si substrate 1 is 11.8 x 8.86 x 10-12 [farad/CTn], and the intrinsic carrier concentration (
Ni) is 1.4×1010/Cm2, and the RT of the diffusion potential is
/e is 0.026 [V]. All of the transfer electrodes 6 are electrically connected to make the CCD 7 effectively one MOS transistor.

Connect the commonly connected transfer electrode 6 to the switch circuit 8,
A power source 9.10 is connected to the other terminal of the circuit 8. On the other hand, the source region 3 is grounded as a reference, and the drain region 4
A voltage, for example, a small voltage of 0.1 V is applied from the DC power source 121 via the ammeter 11, and the ammeter 11 detects the current 1D flowing between the source and drain via the channel 2 due to this voltage.

The current D is converted into a voltage value and supplied to the Y axis of the XY recorder 12.

Move switch 8 to side A in the diagram. When set, the transfer electrode 6 is
The substrate 1 connected to a power source 9 is connected to a triangular waveform voltage generator 10 . Further, when the switch 8 is switched to the B side, the transfer electrode is wired to the triangular waveform voltage generator 10 so that the substrate 1 is connected to the DC voltage power source 9. The frequency of the triangular wave voltage of the triangular wave voltage generator 10 is low frequency (for example, 0.0
1 to 0.1 Hz).

In this case, the voltage amplitude is preferably about 10-20V. This voltage is also wired to be input to the X-axis of the X-Y recorder 12. Note that a DC bias power supply 13 is connected in series to compensate for the amplitude and also to shorten the measurement time. The power supply 9,E, disconnects the negative voltage in the case of the n-type embedded channel CCD 7 (positive in the case of the p-type).
This is for supplying to the transfer electrode 6 or the substrate 1 by the changeover switch 8.

The required performance is that it can be continuously variable in the range of about 0 to -30V. The thickness measuring device for channel 2 is configured as described above. Measurement method Step 1: Adjust the power source E to set VGS (gate voltage to source) to a negative voltage (for example, about -20 V) sufficient to maintain the valence band pinning state at all times.

At this time, VBS changes by 1 D by the triangular wave voltage generator 10. The VBS-1D characteristics in this state are
When recorded in the recorder 12, FIG. 2 is obtained. In FIG. 2, region A corresponds to a state where punch-through has not occurred, and region B corresponds to a state where punch-through has occurred. Therefore, with VBS corresponding to the boundary, VB
It can be SO (substrate voltage at which punch-through starts in pinning state). Next, calculation of the thickness of the embedded channel from the VBSO value measured by the above method will be explained.

As shown in Figure 3, the n-type buried channel is SiO, (5)
Let x be the depth from the -Si(1) interface. There is no practical problem even if a depletion layer approximation model as shown in FIG. 4 is assumed as the impurity concentration distribution with respect to x. Based on this assumption, the following equation is obtained by using the one-member Poisson equation to find a solution for the above-mentioned state, that is, the critical state in which punch-through starts in the valence band pinning state.
Therefore, the thickness D of the channel 2 can be determined by substituting the measured values measured by the measuring device shown in FIG. 1 into equations (1) and (2).

For example, when calculating by substituting the values and measured values shown in the above example into equations (1) and (2), the thickness D of the channel at room temperature (3001 K) is 0.85 μm. In the above description, the definitions of the punch-through hexagram and valence band pinning will be explained using FIG. 5.

What is punch-through? When a negative gate voltage VGS is applied to the source (positive in the case of P type), a depletion layer is formed from the surface.

On the other hand, when a negative substrate voltage VBS (positive in the case of P type) is applied, a depletion layer is formed at the p1n junction. By increasing VGS and VBS to a more negative value, the n-layer is completely depleted, and the source and channel are electrically separated. This condition is called punch-through. What is valence band pinning? For an n-channel, even if VGS is increased negative by a certain voltage value or more, the surface potential of the n-layer cannot be lowered below the substrate potential.

This is because holes are supplied through the surface from the p+ layer, which is generally formed as a channel stopper in a CCD. In this case, since the density of states in the valence band is high, holes are sufficiently supplied and the potential does not drop below the substrate potential. This condition is called pinning. As is clear from the above description, the thickness of a channel can be measured by the method of the present invention.

As explained above, according to the present invention, the entire CCD is
As an S transistor, it can be directly measured from a CCD by measuring the voltage-current characteristics, and
- method has the advantage that the wiring capacitance, which causes measurement errors, does not become a cause of errors.

Further, as is clear from FIG. 1, the measuring circuit is a very simple one, which also has the advantage of good measurement accuracy. It goes without saying that the above embodiments can be applied to any structure in which an electrode is provided on a semiconductor substrate via an insulating film, such as a MIS transistor such as a MOS transistor described in the embodiment applied to a CCD.

Furthermore, in the apparatus shown in FIG. 1, the CCD can measure not only the n-type buried channel CCD, but also the p-type buried channel CCD1, as well as the channel impurity concentration and thickness of the depletion type MOSFET.

Furthermore, although an X-Y recorder is used in the apparatus shown in FIG. 1, a CRT having a memory function may also be used instead.

Additionally, instead of a triangular waveform generator, a sinusoidal voltage waveform or a generator with a single voltage waveform that gradually changes from one voltage value to another rather than a repetitive waveform can be used. I can do it. In the example shown in Figure 1, a common voltage was applied to each transfer electrode, but the same voltage as in the example was applied only to a specific electrode, and a large positive DC voltage was always applied to the other transfer electrodes. The channel thickness of a particular electrode F may be measured by applying

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment in which the method of the present invention is applied to measurement of impurity concentration in a CCD channel, FIG. 2 is a VBS-D characteristic curve diagram for explaining the operation of FIG. 1, and FIGS. 4
FIG. 5 is an explanatory diagram for obtaining the impurity concentration from the measurement results shown in FIG. 1... Semiconductor substrate, 2... Channel,
3... Source region, 4... Drain region, 5... Insulator layer, 6... Electrode, 8
...Switch circuit, 9,10.121...
...Power supply, 12...X-Y recorder.

Claims (1)

[Claims] 1. A channel of a conductivity type opposite to that of the substrate is provided on one inner surface of a semiconductor substrate of one conductivity type, a source region is provided on the inner surface of the substrate so as to supply charge to the channel, and a source region is provided on the inner surface of the substrate so as to supply charge to the channel. In a semiconductor device, a drain region is provided on the inner surface of the substrate, and at least one electrode is provided on the channel of the substrate via an insulating layer, so that the thickness D of the channel can be obtained by satisfying the following equation. Features a method for measuring impurity concentrations in semiconductor devices. D=[2ε_s_i|V_b_i−V_B_S_O|/
e￥N_c￥]＾1＾/＾2[1+{N_c/(N_s
+N_c)}^1^/^2] In the above formula, -e: Electron charge amount ε_s_i: Dielectric constant of the semiconductor substrate V_b_i: (RT/e)ln[N_sN_c/ni^
2] V_B_S_O: Voltage between the source region and the substrate R: Boltzmann constant T: Temperature ni: Substrate intrinsic carrier density N_s: Substrate impurity concentration N_c: Channel impurity concentration