JPS5932924B2 - automatic channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an automatic tuning device, especially when radio broadcasts with the same content are transmitted using multiple broadcast waves, the reception state of the broadcast waves exceeds a preset reference level. This invention relates to an improvement in an automatic channel selection device configured to automatically detect good broadcast waves.

Some conventional automatic channel selection devices employ a system called frequency dipancy, which detects the electric field strength level or noise level and compares it with a reference level to switch the reception of broadcast waves. However, in such a conventional system, reception of broadcast waves is simply switched based on a simple judgment based on the result of comparison with the reference level, which is insufficient. For example, if this method is applied to shortwave broadcasting with large fading, the number of switching will be too large.
This causes interruptions in the reproduced sound when switching, and various other problems. There is also a conventional method in which multiple receivers are installed and the output level of each is compared to switch the reception.
0 Considering that it can be packed into a small set for consumer use, it lacks practicality in terms of cost and space.

This statement was made in order to improve the problems of the conventional technique, and it is possible to simply compare the signal level (S level) and noise level (N level) with the preset standard 25 standard level. Instead of switching the reception of the radio waves, the switching condition timing is added according to various radio wave conditions, and if the radio wave conditions of all of the multiple broadcast waves are unfavorable, all of them are set to N level or standard S level. When it is determined that the standard S level is low at 30, it continues to detect broadcast waves with muting applied, and when it is determined that the standard S level is high and it is switched, it performs one round of broadcast wave detection. The 35th feature is that the system is configured to receive the broadcast wave and then make it difficult to switch within a certain period of time. The present invention will be described below with reference to embodiments shown in the drawings. FIG. 1 shows an embodiment in which the present invention is applied to a radio receiver configured with a PLL synthesizer circuit.

In the figure, 1 is a high frequency amplifier, 2 is a mixer, 3 is a local oscillator, 4 is an intermediate frequency amplifier, 5 is a detection circuit, 6 is a muting circuit, and 7 is an audio amplifier, which constitute a known radio receiver. are doing. 8 is an S level detection circuit which detects the carrier level of the received broadcast wave in a narrow band.

Reference numeral 9 denotes an N level detection circuit which extracts components in a band that can be considered as noise in the audio frequency band after detection.

For example, in a shortwave rental machine, this is a circuit that detects level components distributed around 8 KHz to 15 KHz. 10 is P
LL circuit, 11 is a PLL data storage circuit (ROM),
12 is an address decoder for the memory circuit, 13 to 15 are reference level setting circuits, 16 to 18 are comparison circuits, 19 is a differentiation circuit, 20, 21, 25 and 32 are timers, 22 is a counter, and 23 and 24 are up counters. , 26 is a digital comparison circuit, 27 is a mono multivibrator, 28 is a flip-flop circuit, 29 is a down counter, 30 is a shift register, 31 is a data bus, 33 is an automatic power switch, ANDl to ANDl7 are AND circuits, 0R1 to
0R6 is an OR circuit.

Now, an example of broadcasting that transmits the same broadcast content using multiple broadcast waves is radio shortwave broadcasting, but if you look at the radio wave conditions, you will notice that there is fading that is characteristic of shortwave broadcasting. In the case of detection, even if the S level detection comparison is instantaneously performed, it may not always be good. Furthermore, it is not possible to catch broadcast waves with a good S/N ratio by comparing only the S level, and there are cases where it becomes necessary to also compare the N level. Thus, there is a need for a circuit that automatically detects good broadcast waves, taking into consideration the radio wave conditions unique to short waves. For example, as shown in Figure 3A, the standard S
Even if the level is set to 40 dB, fading F, if any, is instantaneous, so there is no need to switch the received broadcast waves.

In addition, in the case of the opening in the same figure, the reference S level is set at 20 dB, and the fading F cannot be said to be instantaneous, so switching is necessary. Furthermore, in the case of C in the same figure, the standard S level (4
0 dB), it is recognized as instantaneous fading F, but comparison with the reference N level shows an increase in the N level, so it is determined that switching is necessary.
Therefore, in the present invention, a reference level for N level comparison and a reference level for S level comparison, for example, levels equivalent to 40 dB and 20 dB, are set in the reference level setting circuits 13 to 15, respectively, and are applied to the comparison circuits 16 to 18, and the S level It is designed to be compared with the outputs from the detection circuit 8 and the N level detection circuit 9. Now, when the automatic power switch 33 is turned on, the automatic detection mode is entered, and the pulse from the differentiating circuit 19 triggers the timer 20 via the OR circuit 0R5, and the timer 20 outputs an output pulse after a predetermined period of time has elapsed.

At this time, since the N level and the reference S level are being compared by the comparator circuit 16, the comparison result is applied together with the output pulse to the AND circuits AND1 and AND2 for determination.

When the N level is high, the output of the comparison circuit 16 is low, so the output of the AND circuit ANDl becomes high, triggering the timer 21. After a predetermined period of time has elapsed, the output pulse of the timer 21 is output to the AND circuit AN along with the output of the comparator circuit 16.
It is applied to D3 and AND4 and judged again. As a result, if the N level is still large, the AND circuit AND3
The output of the PLL circuit 10 becomes high level and operates the address decoder 12 via the OR circuit 0R2 to read out the PLL data previously stored in the memory circuit 11.
to receive the next station's broadcast waves. Also, OR circuit 0
The flip-flop circuit 28 is turned on by the output of R2, the muting circuit 6 is operated by the output, and the PL
Muting is applied when switching the L circuit 10. The reason why the timer 21 is provided here is to determine whether or not the N level is detected again after a predetermined period of time has elapsed, as described above.
This is to determine whether the N level continues to some extent and to switch if it continues.

If the output of the AND circuit AND4 is at a high level, it means that the N level is not maintained, so there is no switching, and the timer 20 operates again.

When the output of the AND circuit AND2 is at a high level, the N level is small, so the operation moves to the next comparison circuit 17. Next, the comparison circuit 17 is supplied with a reference S level signal from the reference S level setting circuit 14, which is set to a high value even at S level (for example, 40 dB). The value of this signal is set to such an extent that it cannot be said whether or not switching is necessary. The output of the comparison circuit 17 is given to the AND circuit AND6 via the AND circuit AND5, but as a result of comparing the S level with the reference S level, if the S level is large, the output of the AND circuit AND6 becomes high level, The up counter 23 is counted up and the timer 20 is operated again via the OR circuit 0R3. And the output of the timer 20 is an AND circuit AND2
It is applied to the counter 22 via the counter 22, causing it to count up. The counter 22 is for accumulating the output count of the timer 20, and when the set count is reached, a signal is output and the counter is cleared. On the other hand, the up counter 23 is used to add up the comparison result by the comparison circuit 17 when the S level is high.
Further, the up counter 24 is used to add up the results when the S level is small.

That is, if the comparison result in the comparison circuit 17 is that the S level is smaller than the reference S level (however, if it is larger than the reference S level given to the comparison circuit 18), the AND circuit AND
7 and AND8, the comparison result is incremented by the up counter 24. The count data accumulated in the up counters 23 and 24 is sent from the counter 22 at a certain period (when the output of the timer 20 reaches the set count)
The signal is input to the digital comparator circuit 26 in response to the signal outputted every time. The circuit 26 includes an up counter 23,
24, that is, the integrated value S1 (output of the up counter 23) of the comparison results of S level ≧ reference S level output from the comparator circuit 17 as described above and the integrated value S1 (output of the up counter 23) of the comparison results of S level < reference S level Value S2 (up counter 24
When S2>S, a high-level output is generated and fed to the OR circuit 0R2, the negative input of the AND circuit 17, and the shift register 30, and the output of the OR circuit 0R2 is Therefore, the address decoder 12 is operated and the PLL circuit 10 causes the PLL circuit 10 to continue receiving if the comparison result by the comparison circuit 17 is S level ≧ the reference S level, and if the S level is less than the reference S level, the switching operation is performed as described above. to move to. Next, the comparison circuit 18 receives a value from the reference S level setting circuit 15 that is low even at the S level (for example, 2
A signal of about 0 dB (a value corresponding to a level at which the signal is weak and difficult to hear) is given.

The comparison result is given to the AND circuit AND9, and when the output becomes high level, the timer 25 is triggered and after a predetermined period of time has elapsed, the timer output is given to the AND circuits ANDlO and ANDll together with the above comparison result. The output of ANDlO is sent to the OR circuit 0R2. As a result, in the same manner as in the case of determining the N level, if the S level continues to be low for a short duration, switching is performed. Now, in the case of radio shortwave broadcasting, there are three broadcasts of the same broadcast content, and as a result of the above comparison, the operation when switching occurs three times in a row will now be described.

If the comparison circuits 16 and 17 switch, the switching continues in search of a strong radio wave and a low N level radio wave. In that case, since the muting circuit 6 is kept on by the output of the flip-flop circuit 28, there is no audio output from the speaker 34.
In this case, depending on the comparison result of the comparator circuit 17, reception switching may be performed three times in a row among the three broadcasts of the same broadcast content in a short period of time.

For example, the following switching based on received field strength can be considered. 'C In the above case, even if the switching is continued, the reception field strength of any broadcast will not improve, and in such a case, the reception of the broadcast that is relatively close to the standard S level (40 dB) of the comparator circuit 17 will be fixed. It's better to do so.

Therefore, in the second embodiment, for example, (3), (4), (6
) and (7), the third received broadcast is (1
) and (2), the first received broadcast is (5
), the configuration is such that the degree of switching is reduced by newly receiving the second received broadcast. To explain its operation, the down counter 29, which is preset to 2, is counted down by the output of the OR circuit 0R2.

The output of the digital comparison circuit 26 is input to the shift register 30, and the number of switching points is stored based on the judgment of the comparison circuit 17. As mentioned above, when the down counter 29 switches three times in a row and the BORO 1 output is output, the BORO 1 output causes the shift register 30 to be switched.
The contents of are sent to the address decoder 12 via the data bus 31 through AND circuits ANDl2 to ANDl4. The address decoder 12 is preset with an initial value for each broadcast reception according to a predetermined switching sequence, and the output of the shift register 30 is added to the initial value in response to the output of the down counter that occurs at the time of switching. By doing so, it is determined which station should be received, and the PLL data corresponding to the address is taken out from the storage circuit 11 and given to the PLL circuit 10 for reception. The down counter 29 and shift register 30 are preset and cleared, respectively, when a BORO-1 output is output and when the comparison circuit 17 determines that the S level is higher than the reference S level. The timer 32 is activated by the output of the down counter 29, but this is to make it difficult to switch to the broadcast wave whose reception has been stopped.

That is, in this case, the output of the timer 32 is output from the AND circuit AN
Since it is applied to the negative inputs of D5 and ANDl5, the determination result of the comparison circuit 17 is disabled for a predetermined period of time, and is enabled after the predetermined period of time has elapsed. In addition, the N level is large for the broadcast wave whose reception has been stopped, and the reference level setting circuit 1
When the S level becomes lower than the reference S level set by 5, the timer 32 is cleared by the output of the OR circuit 0R4 to perform switching.

Regarding cancellation of muting, comparator circuit 1 is used as described above.
If the switching continues based on the judgment results of 6 and 18, the muting circuit 6 continues to operate with the output of the flip-flop circuit 28, but if the judgment result of the comparison circuit 17 is negative, the output of the AND circuit AND6 becomes high level. Muting is canceled at this point.

The mono multivibrator 27 is used to operate the timer 20 at a predetermined timing after the flip-flop circuit 28 is set.

FIG. 2 is a flowchart showing an outline of the switching operation described above.

As is clear from the above explanation, according to the present invention, it is possible to automatically detect broadcast waves that are always in good reception condition and receive the most suitable broadcast waves, and it also uses a PLL channel selection method. Therefore, the synchronization is also good.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a flowchart showing an outline of its operation, and FIG. 3 is an explanatory diagram of the operation of the above embodiment. 2: Mixing circuit, 3: Local oscillator, 4: Intermediate frequency amplifier,
5: Detection circuit, 6: Muting circuit, 8: S level detection circuit, 9: N level detection circuit, 10: PLL circuit,
13-15: Reference level setting circuit, 16-18: Comparison circuit.

Claims (1)

[Claims] 1. Means for detecting a signal level and noise level in a PLL synthesizer radio receiver, means for setting a reference noise level and a reference signal level, and means for detecting a detected signal level, a noise level, a reference signal level, and a reference signal level. means for comparing the comparison results with the noise level, means for integrating the comparison results of the comparing means, and designating an address of the PLL data storage circuit in accordance with the integrated value of the integrating means and in accordance with a predetermined sequence. and a PL for switching the received broadcasting frequency of the radio receiver so that the received signal level increases in response to the output from the designated address of the storage circuit.
An automatic tuning device characterized by comprising an L circuit. 2. A patent claim characterized in that the radio receiver has a muting circuit, and is configured to operate the muting circuit according to the integrated value of the integrating means to interrupt audio output when switching the receiving frequency. Automatic channel selection device according to item 1.