JPS5932873A - Distortion measuring circuit - Google Patents

Distortion measuring circuit

Info

Publication number
JPS5932873A
JPS5932873A JP14301782A JP14301782A JPS5932873A JP S5932873 A JPS5932873 A JP S5932873A JP 14301782 A JP14301782 A JP 14301782A JP 14301782 A JP14301782 A JP 14301782A JP S5932873 A JPS5932873 A JP S5932873A
Authority
JP
Japan
Prior art keywords
distortion
value
measured value
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14301782A
Other languages
Japanese (ja)
Inventor
Mitsuyuki Ara
荒 光之
Kazunori Hirabayashi
平林 和紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ando Electric Co Ltd
Original Assignee
Ando Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric Co Ltd filed Critical Ando Electric Co Ltd
Priority to JP14301782A priority Critical patent/JPS5932873A/en
Publication of JPS5932873A publication Critical patent/JPS5932873A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/16Spectrum analysis; Fourier analysis
    • G01R23/20Measurement of non-linear distortion

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

PURPOSE:To achieve a switching in the measurement of a one-point distortion and a biased distortion with a simple construction by providing a CPU in a distortion measuring circuit. CONSTITUTION:When measuring a one-point distortion, counts of a counter 4 are led by controlling a CPU 9 to convert the led value into a code. The measured value Q thus converted is compared in the magnitude with the previous measured value P. When the current measured value Q is larger than the previous value P, the measured value Q is replaced with the measured value P. Based on the results of the measurement of the one-point distortion, it is determined whether the measured value is updated or left as it is and the max. value of the distortion is always displayed. Then, when measuring a biased distortion, the coded counts of the counter 4 are added and the end of the addition is checked. After the end of the addition, added value divided by addition frequency is calculated to determine the biased distortion. The current measured value is indicated in place of the previous measured value. Thus, each time the biased distortion is measured, the measure value is updated.

Description

【発明の詳細な説明】 この発明は、データ回線の品質チ用ツク川に使用するひ
ずみ1Illl定回路についてのものてあ、る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a distortion constant circuit used for checking the quality of a data line.

i゛−夕回綻のひずみにはバイアスひずろや11.1一
点。
i゛-Evening distortion has bias distortion and 11.1 points.

ひJ” h ’f、1′とかある。バ、イアスひすみは
ある周期についての人力信シラのひrみの平均てあり1
.II+、点ひ・Jみは人力信号の変換点についてのひ
ずのである。
There is such a thing as ``hi J'' h 'f, 1'.Ba, Iasu Hisumi is the average of Hijiri's Hirisumi for a certain period, which is 1.
.. II+, point distortion and Jmi are the distortions at the conversion point of the human input signal.

この、1、うr、(IS!合に使用する従来回路の・例
を第1図に小ず。図て、1は人力喘1”y2は4711
 )、’11弓を加える喘r、3はり−1回路、4はr
)ウノタ、5は+、−1変換回路、6はノノウノタ、7
は゛ノリソブフIIソゾである。j、Qお、第1図の内
容1J1°1願昭5 (i  L 28(i 03号明
細、1:にも記桟されている。
An example of the conventional circuit used in this case is shown in Figure 1.
), '11 add bow r, 3 beam - 1 circuit, 4 is r
) Unota, 5 is +, -1 conversion circuit, 6 is Unota, 7
This is Norisobuf II Sozo. j, Qo, Contents of Figure 1 1J1°1 Gansho 5 (i L 28 (i 03 Specification, 1: is also noted.

ゲート回路で3は喘r +:からの人力(,1弓と1※
’: I′2からのり11ツク信弓を入力とし、人カイ
、1“弓の[11側に対応−4るりUツク信t;を出ツ
ノする。カウンタ4には、あらかしめ人力(1i’ j
Eの〕、(べ’II+”+をカランiするよ、うに設>
jlしてお(:。・力、ノノウ/りにては、あらかしめ
設定したへ力信弓の1′榮り丙し数をカラン+するよう
にする。
In the gate circuit, 3 is pant r +: human power from (, 1 bow and 1 *
': Input 11 tsukushin from I'2 and output 1" corresponding to the [11 side of the bow - 4 tsukushin t;. In counter 4, roughly 1i ' j
E's]、(B'II+"+)
jlshio(:.・For power, non-no-no/ri, set the pre-set number of 1's worth of the Rikishin bow to +1.

ソリノゾフIIノソ゛7は人カイ、i弓の翫ン1.りて
1!〕卜され、カウンタ6の出力でリレノドされる。“
l−ト変換回路5はノノウンク4の出力とソリソブフロ
ップ7の出力を入力とし、カウンタ4の出力をデコード
して入力信号のひずみに変換する。なお、カウンタ4の
出力をそのままひずみ(【°1として使用する場合は、
:+−)変換回路5は不要とへるつ次に、第1図の動(
”+を第2図に17たが−7で説明i 仁 第2図ノ′は71.1 i’ Iからの人力信ぢのiフ
シ1[三てあり、人))イ、:“・、:のゾノ、4側の
部分を1要部として小しでいる。
Solinozov II Noso 7 is human Kai, i bow handle 1. Rite 1! ] and is reloaded by the output of the counter 6. “
The converter circuit 5 inputs the output of the non-unc 4 and the output of the sorisobflop 7, decodes the output of the counter 4, and converts it into a distortion of the input signal. Note that when using the output of counter 4 as it is as a strain ([°1),
:+-) Conversion circuit 5 is unnecessary.Next, the operation (
"+ is 17 in Figure 2, but -7 is explained i. Figure 2' is 71.1 i' Human power belief from I is 1 [3 points, people)) I,: " The zono of , : is made smaller with the 4th side part as one main part.

第2図では喘1′2からのりU、り信ぢであり、第21
×Iつはり一1回路33の出力て、人力(i’j’ ”
Iのブノス側に対応する部分のりIIノクィ1−1弓が
出)J 1.t、する。
In Figure 2, it is from 1'2 to Nori U, Rishinji, and the 21st
×I balance 11 circuit 33 output, human power (i'j' ”
The part corresponding to the Bunos side of I (II Noqui 1-1 bow comes out) J 1. T, do.

第2図1はフリソブソ【tノゾ7の出ツノ、・フシ形1
−あり、第≦≧図アの〜IIりて出力か「1」になり、
入ノJイ、:可のj7トリで「OJにtよ−、ている。
Figure 2 1 shows the frisobuso [the protruding horn of t-nozo 7, the shape of 1
- Yes, the output becomes "1" when ~II of Figure A is present.
In the J7 trilogy: ``I'm in OJ.''

(−れし1、あらか1.め、品定したカラ/9((のカ
ラ/)イ直を1(、:(た 例 て 、  カ  ウ 
/  り  〔l の カ  ウ /  1  ′@ 
た け  )  リ  2ブフII λブ/の出ツノは
[11を保tI工する。
(-reshi 1, rough 1. first, quality Kara / 9 ((kara /) straight 1 (,:
/ ri [l's cow / 1'@
Take) Li 2 Buff II λ B/'s output is [11].

第2図1はカラ/り4の出力てあり、例えば図小のよ“
1に4.つ/ド値50を人カ信シの)、(・ス’l 4
i’F 占1れは、ノノウノタ4はカラノ1f直が50
にj、I:ると、山び0か【゛、カウントを始め、この
リイクルを繰りi:’41でいく。
Figure 2 1 shows the output of Color/Register 4, for example "
1 to 4. ), (・s'l 4)
i'F Fortune 1 is Nonounota 4 is Karano 1F direct is 50
j, I: Then, the mountain becomes 0 or [゛, starts counting, repeats this recycle, and goes to i: '41.

1−1変拉(回路5tこは、第2図Tの−/リップ−/
J、I ソゾ7の出力さ一第2図3のカラ/り・1の出
力か入り、カウンタ4のlj力を一7’ :+−1シ、
−を二へii讐し2、人力信号のび′Jのに変換する。
1-1 Variation (Circuit 5t is -/lip-/ of T in Figure 2)
J, I Output of sozo 7 - 2 - Output of 1 in Figure 3 enters, lj force of counter 4 - 7': +-1,
- to 2 and convert it to 2 and the human input signal is 'J'.

例えば、第2図1のノノウノlfj’f M Oから5
0にi阜jて11fび0からカウントシ、そのカラ/I
・値か5のとき−ノリr −/ y「2ノブ′/か[0
4になった2二覆れば、+ 1変換1111路5の演所
により、ひずみを10%と人手Jる。
For example, from No No No No lfj'f M O in Figure 2
11f to 0 and count from 0, that color/I
・When the value is 5 - Nori r - / y "2 knob' / [0
If 22 is changed to 4, the distortion will be 10% and manually adjusted by +1 conversion 1111 road 5.

4なわ!う、第1図の従来、回路は入))信t;のゾン
ス側た+、Jに対応4−るり【+ツク18号のカラ/1
値から人力信号のひ1みを求めるものである。
4 ropes! U, in the conventional circuit shown in Figure 1, the circuit is input)
This is to find the human signal strength from the value.

なお、第2図アル」は人力信澱のiiウリIへし2周間
か1リイクルの場合の例で、lj点ひ′Jのの測定をし
ている状態を示−4,。
In addition, Fig. 2 shows an example of the case of 2 rotations or 1 recycle of a human-powered feedstock, and shows the state in which the lj point is being measured.

第2図アの人))伝りを繰り返lていくき、ノノウノタ
4は1)す回の結果からカウントを始めるので、リウ/
1値を累積していく。したか1.て、ノノウノク4の出
力をカウンタ((のカラノ1イ1”(で割れば、人力信
−Jの甲均されたバイアスひ−J” Itを求めること
かできる。
Figure 2 Person A)) Repeats the process, and Nonounota 4 starts counting from the result of 1), so Liu/
1 value is accumulated. Did you do it?1. Then, by dividing the output of Nonounoku4 by the counter ((), it is possible to obtain the averaged bias of Human Power Shin-J).

この発明は、第1図と同じよ)に中、f\ひ−J’ =
”1. (’:・・イ“j+ 7ひ4みの71111定
かてき、かつ第1図のご1−1変換回路5、力・°Iフ
ッタ(およびフリ、ブフV’l 、7ゾ7−5: CI
’ L!に置き換えて構成を筒中に“4るととモニ、1
’ 点ひ−4みとバイアスひ4みの7則定のり(臭えを
丁バi Illにてきるようにt−1ごものである。以
ト、図面によりtの発明をICY細に説明する。
This invention is the same as in Figure 1), f\hi-J' =
``1. (':...I''j+ 7hi 4mi 71111 fixed value, and the 1-1 conversion circuit 5 in Figure 1, force/°I footer (and Furi, Bufu V'l, 7zo 7 -5: CI
'L! Replace the configuration with “4” and “1” in the cylinder.
'The seven rules of fixed glue for dot heat and bias heat 4 (it is similar to t-1 so as to bring the odor to the t-bai Ill).Hereinafter, the invention of t will be explained in detail with reference to the drawings. .

;l′、U’ 、この発明による実施例の(1′1テ成
図を第33図に小゛J6第1(図の1〜4は第1図と同
しものなので、その説明を省略するう 第3図のF3はカラ5/夕4の出))を−・時記憶J゛
るーノノーf−回路、9はシソヂ回路乏(の出力を人力
−・(5、バイア入ひ4みのflit nをするC1)
U、IOはCI”[I El l’、)出力を取り出′
1゛ためのラッチ回路てl)る。
; l', U', the (1'1) diagram of the embodiment according to the present invention is shown in Fig. 33. Then F3 in Figure 3 is the output of Kara 5/Ya 4) - time memory circuit, and 9 is the output of Shisoji circuit (output of 4) by human power - (5, via input 4) C1)
U, IO takes out the output of CI'' [I El l',)'
There is a latch circuit for 1).

CI’ [19の処111i時間か短いときし1、ラノ
ヂ回路乏シを省略してもよい。
If the time 111i in CI'[19 is short, then 1, the Rannoj circuit may be omitted.

喘”l’ lからの13号を反転回路11を介してカウ
ンタ4の1ぐ喘rに加えているのは、第2図アのr’f
]・りてノノウ/り4をリセットするためである。また
、反転回路11は、第2し1゛ノ′の立トリてクイミ、
/ゲ信弓を発11さするためのもので、反転回路11か
ら出力か出るとラッチ回路8はカラノ′J71の出力を
記iαす゛る。
The number 13 from ``l'l'' is added to 1gr of the counter 4 through the inverting circuit 11 by r'f in Fig. 2A.
]・This is to reset the Rite-no-now/RI4. In addition, the inverting circuit 11 is connected to
The latch circuit 8 records the output of the Karano'J71 when the output is output from the inverting circuit 11.

次に、第33図により中点ひ1みを4111定する場合
のフ1−チャートの・例を第4図に小t。
Next, FIG. 4 shows an example of a flowchart when determining the midpoint distance by 4111 according to FIG. 33.

第4図はスフツブ21〜2(ンの〔(つのl 7 lゾ
で構成されており、CP U りを制御JるJ−ζ、ニ
ア1、リスノツプ22てカウンタ4の、!1数値をり−
1(5、スフ212丁3てそのり−lイj’fを:+−
)変換する。
Fig. 4 is composed of two blocks 21 to 2, which control the CPU, near 1, listen knob 22, and the !1 value of counter 4. −
1 (5, Sufu 212-cho 3 Tesori-l ij'f: +-
)Convert.

スラツジ24ては、コート変換した測定(j’fかい」
までの測定fj’f J、りも大きいか小さいかを比較
iる。
Slatsuji 24 is a coat converted measurement (j'f Kai)
Measure up to fj'f J and compare whether it is larger or smaller.

いままでの測定値1)よりもつ回の7111定f!1“
IQか人きいときは、スーjソゾ25て測定イ1゛」Q
を71111定値1’ 1.’:置き換え、測定値夏)
よりも71111定値Qか小さいときは、そのままスゲ
ノブ26で終りに1.Cる。
7111 constant f of the times with more than the measured value 1) so far! 1"
When I'm sensitive to IQ, I measure 25 and 1.''Q
71111 constant value 1' 1. ': replaced, measured value summer)
If 71111 constant value Q is smaller than , use Sugenobu 26 to finish with 1. Cru.

すなわら、第4図はqj点ひ′4′みの71111定鈷
宋で測定値を更新するか、そのままにしておくかを決め
、中点ひ4″みの最大価をいつも表ji、、4るよ’J
 (、−、Lkものである。
In other words, in Figure 4, we decide whether to update the measured value or leave it as is at the 71111 constant force at point qj, and always express the maximum value at midpoint 4''. , 4yo'J
(,-,Lk).

次に、第33図によりバイアスひ4乃を測定Jる場合の
゛)ロー千1・−1の・例を第45図に小」、第[)1
べl(l;1 !Iゾ3(1〜38の8−〕の472ブ
(′(I寺1戊さね一区′才、す、CP [19を制御
Jるこ(!: +: 、i−リΔ・ ζ” El 2’
il”リウ/り4の、iIl数値り−114−,7J−
、! :113−(% (+) ’J  F fll’
l ?、 :I  1’ 2換−J’ 4゜7.1−1
/33,1てli、:+−1変(祷L7たカラ/り・1
の、;l数値を加37+ L、4ノノゾ3(5て加幻か
柊1(7たh)、どうかを判断する。加312か柊rし
でいれば、入ji  ・’、/ 丁+ (iて加p値−
゛−加p同数を演s7L、 、バイア4ひ4み4−1つ
出′Jる。そして、ス、7Iゾ丁(7てい−LJての7
1111定イσ″(の代りに今回の測定&fを表;J+
 =、する、l、うにする。
Next, in the case of measuring the bias HI4 from FIG.
Be l (l; 1 ! Izo 3 (8- of 1 to 38)) 472 b('(I temple 1 戊sane 1 ward 'sai, su, CP [19 control Jruko (!: +: , i−riΔ・ζ” El 2'
il"riu/ri4's iIl numerical value -114-,7J-
,! :113-(% (+) 'JF full'
l? , :I 1'2-J' 4゜7.1-1
/33,1teli, :+-1 change (prayer L7takara/ri・1
Add the ;l value to 37 + L, 4 no no zo 3 (5 to judge whether it is Kagen or Hiiragi 1 (7 to h). If it is Add 312 or Hiiragi r, enter ji ・', / Ding + (i + p value -
゛-Add the same number s7L, , By 4 Hi 4 Mi 4-1 Output 'J. And, Su, 7I Zocho (7tei-LJte no 7
1111 constant a σ'' (represent the current measurement &f; J+
=, to do, l, to do.

]川’Oか9′にI’ していないききは、スーンノブ
?3)3から’、 5 戸’/ 38に移り、加算が終
r′4る才てス)ノゾ31−へ−C(15を繰り退す。
] River 'O or 9'I'I'm not listening to you, Soon Nobu? 3) From 3', 5'/38, the addition ends r'4) Nozo 31-to-C (carry back 15).

Jなわち、第5図はバイアスひりみを測定りる)、・ひ
に、新j2い測定値を更新していくJ、うに(また0の
である。
In other words, in Fig. 5, the bias shrinkage is measured), and the new j2 measurement value is updated (also 0).

第1図の(17来回路で111点ひずみとペイ“〕′ス
ひ1a”tを測定Jるためには、第1図では図小を省略
し−(′いるかIv!j111 f、< IJ)換え回
路か必要になる。これにに・1し、第1(図の実施例回
路−C−1:を喘t’、 l l、J 、:、・【”、
 1.1111倉イ1.−シ を CI’  U  4
+  1− )川 λ る i、:  Ll−C−J、
 <、l川:fi’+ を苛1戊 を17τ)甲1、“
Jる(−吉か一1′きる。
In order to measure the 111-point distortion and pay in the circuit shown in Fig. 1, the small part is omitted in Fig. 1 and -('Iv!j111 f, < IJ ) A switching circuit is required.For this, add 1 to this and convert the first circuit (Embodiment circuit-C-1 in the figure) to
1.1111 warehouse 1. - CI' U 4
+ 1-) River λru i,: Ll-C-J,
<, l river: fi'+ 17τ) 1, “
Jru (-kichikaichi 1' is over.

すIの31、うに1.二の発明によれ+、r、(□1パ
1こ回路1J゛比へて回路描1.+(シを筒中に−Jる
::、 、l、かてきるJ、 Jもζ5′、中、、l(
ひJ・”ム一・・fノ′!、ひ4パLイー′fンj−j
 +7.711’l zl’・jることかてきるつ才た
、中点ひif’ 、うの1lli )c tl:果ろ・
hイア4ひ1みf直に変換(−−(+、1 ルノテ、(
T(トi (’)i’′l−じを測定゛するごきもてき
る。
Su I 31, sea urchin 1. According to the second invention +, r, (□ 1 circuit 1 J゛ ratio, circuit drawing 1. Medium,,l(
HiJ・”Muichi...fノ′!、Hi4paLee′fnj−j
+7.711'l zl'・j, middle point hi if', uno 1lli) c tl: Goro・
hia4hi1mifconvert directly (--(+, 1 runnote, (
I feel like measuring T(toi(')i''l-).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は6t−来回路の−・例、 第2図は;111図の動イ′1説明川洩1[ニ図、第3
 r<1はこの発Ill目こよる実施例の構成図、第4
図は第33図により中点ひ1みを潤′、Jテ4る1、、
j合の)【盲−ヂv−)の−・イ切り 第5図は第3図に、1、リバイアスひ−L+、’:Iを
測定する場合のフ1−ブヤ−トの・例。 1・  人力喘r12・・・り11ノクイ11ぢを加え
る喘r13  デー1回路、4 1ノウツタ、)i:+
 −1=変換回路、6・・ カウンタ、’/ −−’/
 11.77ノ【+7ゾ、8・ ラッチ回路、1(・C
I’ U 。 1()  −ノツチ回路、11・・ 反転回路、121
i) tIll(、i 弓を加える喘fハ21〜2 (
i   ・7 +1−−1?−1の1.7ソゾ、31〜
31(−7【1−千Vlの41−ブ。 代理人 jt、 El! l  小俣欽司39 第1図 う 第2図 1−o       5 13図 第 4  Pつ
Figure 1 is an example of the 6t-coming circuit; Figure 2 is;
r<1 is the configuration diagram of the fourth embodiment of this invention.
The figure shows the middle point Hi1mi according to Figure 33.
Figure 5 shows an example of the graph when measuring 1, Libias H-L+,':I. 1. Human power r12... R11 Noki 11 Di is added R13 Day 1 circuit, 4 1 Noitsuta,) i:+
-1=conversion circuit, 6... counter, '/--'/
11.77 [+7 zo, 8. Latch circuit, 1 (・C
I'U. 1() - Notch circuit, 11... Inversion circuit, 121
i) tIll(,i Adding a bow fHa21~2 (
i・7 +1−−1? -1's 1.7 sozo, 31~
31 (-7 [1-1,000 Vl of 41-bu. Agent jt, El! l Kinji Omata 39 Figure 1 U Figure 2 1-o 5 Figure 13 Figure 4 P

Claims (1)

【特許請求の範囲】[Claims] 1.入力信号とクロック信号を入力とするゲート回路と
、 あらかしめ人力信号の)、(”J’ <p’tをノノウ
ントする。]、□、    うに設’>r; L・前記
フート回路の出力を″°ン7 ) Jるツノ・ンンタと
、 1)11記カウ/りの出力を人力とするC l’ Uと
を備え、 人力信弓の111点ひずみまたはバイアスひ1みをi’
1lll定するこ七を11r徴とするひずみ測定回路。
1. A gate circuit that receives an input signal and a clock signal, and a human input signal), ("J'<p't is not counted.], □, Uniset'>r; L. The output of the foot circuit is ``°n7) Equipped with C l' U which uses human power to output the output of 11 CAU/RI, and i'
A strain measurement circuit with 11r characteristics.
JP14301782A 1982-08-18 1982-08-18 Distortion measuring circuit Pending JPS5932873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14301782A JPS5932873A (en) 1982-08-18 1982-08-18 Distortion measuring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14301782A JPS5932873A (en) 1982-08-18 1982-08-18 Distortion measuring circuit

Publications (1)

Publication Number Publication Date
JPS5932873A true JPS5932873A (en) 1984-02-22

Family

ID=15328992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14301782A Pending JPS5932873A (en) 1982-08-18 1982-08-18 Distortion measuring circuit

Country Status (1)

Country Link
JP (1) JPS5932873A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5558645A (en) * 1978-10-24 1980-05-01 Siemens Ag Diginal signal phase jitter detector circuit
JPS55110454A (en) * 1979-02-17 1980-08-25 Advantest Corp Jitter measuring unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5558645A (en) * 1978-10-24 1980-05-01 Siemens Ag Diginal signal phase jitter detector circuit
JPS55110454A (en) * 1979-02-17 1980-08-25 Advantest Corp Jitter measuring unit

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