JPS5932261A - Power supply circuit - Google Patents

Power supply circuit

Info

Publication number
JPS5932261A
JPS5932261A JP14313382A JP14313382A JPS5932261A JP S5932261 A JPS5932261 A JP S5932261A JP 14313382 A JP14313382 A JP 14313382A JP 14313382 A JP14313382 A JP 14313382A JP S5932261 A JPS5932261 A JP S5932261A
Authority
JP
Japan
Prior art keywords
voltage
silicon
controlled rectifier
power supply
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14313382A
Other languages
Japanese (ja)
Other versions
JPS6322755B2 (en
Inventor
Tsutomu Watanabe
力 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14313382A priority Critical patent/JPS5932261A/en
Publication of JPS5932261A publication Critical patent/JPS5932261A/en
Publication of JPS6322755B2 publication Critical patent/JPS6322755B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/18Generation of supply voltages, in combination with electron beam deflecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)
  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To extend the operational range of a power supply voltage, by applying start pulse to a gate electrode of a silicon controlled rectifier element, in the power supply circuit using the silicon controlled rectifier element. CONSTITUTION:A DC input voltage B1 is led to a DC power supply input terminal when a power supply switch 39 is turned on. When the divided and decreased voltage is higher than a switching voltage of a silicon bidirectional switching element 44', the switching element 44' turns on, the silicon controlled rectifier element 13 turns on, a DC output voltage B2 is increased and starts a horizontal output circuit 14 and the like at the rated voltage. Then, since an output of a start pulse supply circuit 26 is held to a value sufficiently lower than the gate voltage of the rectifier element 13, there exists no effect to the silicon controlled rectifier element 13.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、テレビジョン受像機等に使用されるシリコン
制御整流素子を使用した電源回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a power supply circuit using silicon-controlled rectifying elements used in television receivers and the like.

従来例の構成とその問題点 従来、この種の亀除回v1゛Tは第1図のように構成さ
れている。交流電源入力端子(1)より4つのダイオー
ド(2) (3) (4) (5)とコンデンサ(6)
とから成る整流平滑回路(7)を介1ッて直流電蝕入力
端子(8)に被制御直流入力電圧Bl〔非安定化直流人
力tl圧〕を供給し、この直流人力m圧B1をチョーク
トランク((りの1次巻線θQ1水平出カドランス0υ
の3次巻線θカを介してシリコン制御整流素子θ4のア
ノードに印加し、このシリコン制御整流素子θ、lのカ
ソードに導出される直流出力電圧B2を水平出力回路θ
美に印加し”Cいる。
Conventional structure and its problems Conventionally, this type of tortoise removal circuit v1'T has been structured as shown in FIG. Four diodes (2) (3) (4) (5) and a capacitor (6) from the AC power input terminal (1)
A controlled DC input voltage Bl [unstabilized DC human power tl pressure] is supplied to the DC galvanic input terminal (8) through a rectifier and smoothing circuit (7) consisting of ((Primary winding θQ1 horizontal output drance 0υ
The DC output voltage B2 is applied to the anode of the silicon-controlled rectifying element θ4 through the tertiary winding θ of the horizontal output circuit θ
It adds to the beauty.

ここで水平出力回路041は水平用カドランス(1υに
加えて、水平出力トランジスタQQ、タンパ−タイオー
ドθQ1共振コンデンサOη、異常パルス吸収用のダイ
オード0榎、抵抗OQ1 コンデンサa)、水平偏向コ
イルc!vおよび5字補正用コンデンサ(イ)がら構成
されている。また、(ハ)はシリコン制御整流素子時の
始動パルス供給回路で、定1u圧ダイオード(イ)のア
ノードにダイオード1411のアノードを接続して構成
されており、定fl(圧タイオード144I+のカソー
ドが直流電源入力端子(3)に接続され、ダイオード〔
υツカソードはシリコン制御整流素子(1,1のゲート
m極@1こ接続されている。ゲートiti、極(ロ)は
抵抗りを介シてシリコン制御整流素子(1罎のカソード
に接続さtlている。また、シリコン制御整流素子0)
のカソード、すなわちfLE 紳出力端子(ハ)はコン
デンサ汐1)を介して接地されると共に抵抗ell+を
介して直流m源入力端子(8月こ接続さ)1でいる。チ
ョーク1−ランス(9)の2次巻線0zの一端はタイ用
−ド關を介しで接地さイ1、他端は亀源出力端r醤に接
続さ11ている。電源出力端子四に導出される直流出方
?電圧B2は、抵抗l341.定1Uルダイオード(至
)、コンデンサ弼によって降圧かつ安定化されてnL源
供給端子C(カから誤差検出位相制御回路bsに供給さ
れる1、このように構成される定電圧電源回路において
、電源スィッチ■1)を閉成して整流平滑回路(7)に
人力交5IE電圧を供給しているときには、直流電源入
力端子(8)に整流平滑された被制御直流入力電圧B、
が導出され、この被制御部流人カフπ圧B、がパルスト
ランス(9)の1次巻線0(倉、水平出力l−ランス0
υの3次巻線θ2、およびシリコン制御11BI JR
流崇子llj:’eを介して制御され、電源出力端子シ
瑛に電圧安定化さ11だ直流、出力電圧B2が導出さ第
1、この直流出力″18. )−1:n2が水平出力回
路041に供給されると1(に1j(1抗Mを介して降
圧さ!1だのち誤差検出6ン相制θ(1回路(ハ)にも
(Ji、紹さ11る。
Here, the horizontal output circuit 041 includes a horizontal quadrence (in addition to 1υ, a horizontal output transistor QQ, a tamper diode θQ1, a resonant capacitor Oη, a diode for absorbing abnormal pulses, a resistor OQ1, a capacitor a), a horizontal deflection coil c! It consists of V and a 5-character correction capacitor (A). In addition, (c) is a starting pulse supply circuit when using a silicon-controlled rectifier, which is constructed by connecting the anode of a diode 1411 to the anode of a constant 1u voltage diode (a), and the cathode of a constant fl (voltage diode 144I+) Connected to the DC power input terminal (3) and connected to the diode [
The υ cathode is connected to the gate m pole of the silicon controlled rectifier (1,1. In addition, silicon controlled rectifying element 0)
The cathode of fLE, ie, the output terminal (c) of fLE, is grounded via a capacitor (1) and connected to the DC m source input terminal (connected to 1) via a resistor (ell+). One end of the secondary winding 0z of the choke 1 lance (9) is connected to ground 1 through a tie gate, and the other end is connected to the source output terminal 11. Direct current led to power output terminal 4? Voltage B2 is applied to resistor l341. The voltage is stepped down and stabilized by a constant 1U diode (to) and a capacitor (2), and is supplied from the nL source supply terminal (C) to the error detection phase control circuit (BS). When the switch 1) is closed and the human power alternating current 5IE voltage is supplied to the rectifying and smoothing circuit (7), the rectified and smoothed controlled DC input voltage B is input to the DC power input terminal (8).
is derived, and this controlled part flowing person cuff π pressure B is the primary winding 0 (kura, horizontal output l-lance 0) of the pulse transformer (9).
Tertiary winding θ2 of υ and silicon control 11BI JR
The voltage is stabilized at the power supply output terminal 11 DC, the output voltage B2 is derived from this DC output '18. ) -1:n2 is the horizontal output circuit When supplied to 041, the voltage is stepped down through the resistor M to 1 (1), and then to the error detection 6 phase phase θ (1 circuit (c)) (Ji, introduced 11).

電汁スイツヂい・))を投入すると、先ず、始動パルス
供給回h1;1ψ鰺が作動してシリコン制御整流素子0
.1のゲート眠(窃(イ)に始動パルスが供給される。
When the electric juice switch is turned on, first, the starting pulse supply circuit h1;1ψ is operated and the silicon controlled rectifier
.. A starting pulse is supplied to the first gate.

これによっでシリコン制御本′E流素子0やがトリガー
されてターンオンし、−1源入力端子(8)よりチョー
クトランス(0)の巻線(l()、水平出カドランスθ
υの8次巻線Oaを介してコンデンサG11lが充電さ
イ1ろ。コンデンサ軸がある電圧まで充tFされると、
水平出力回路(J4が水平偏向動作を開始し、また誤差
検出位相制御回路勢も動作準備完了となり、水平出力回
路09が完全に動作を開始する。
This triggers the silicon control element 0 and turns it on, and connects the -1 source input terminal (8) to the winding (l()) of the choke transformer (0) and the horizontal output quadrature θ.
Capacitor G11l is charged via the 8th winding Oa of υ. When the capacitor shaft is charged to a certain voltage,
The horizontal output circuit (J4) starts the horizontal deflection operation, the error detection phase control circuits also become ready for operation, and the horizontal output circuit 09 starts to operate completely.

以上説明の従来回路では、と(″流112市回bv、(
7)とシリコン制御整流素子θ罎のゲート屯極翰間fこ
始動パルスfIt給回路c7(νを設り、電源スイッチ
(3僧を投入すると直流亀踪人力y席子(8)Iこ被測
(+lI直/>if:入力端子B。
In the conventional circuit explained above, and (''flow 112 city times bv, (
7) and the gate of the silicon-controlled rectifying element θ, set up the starting pulse fIt supply circuit c7 (ν), and when the power switch (3) is turned on, the direct current is turned off and the human power y seat (8) I is measured. (+lI direct/>if: input terminal B.

が導出され、シリコン制伺1整汎素子0.染のカソード
に導出される直流出力電圧を1へ7、定電1■−ダイオ
ード(40)のツェナー1u圧をElとすると、13.
−B、ンEzとなれば定電圧ダイオード四及びダイオー
ド(4I)が導通して始動パルス供給回路Wか作動し、
シリコンζ1,11和(I IIK、流木、子01がタ
ーンオンして直流出力電圧B。
is derived, and the silicon constraint 1 generalizing element 0. If the DC output voltage derived to the cathode of the dye is 1 to 7, and the Zener 1u pressure of the constant voltage 1 - diode (40) is El, then 13.
-B, when Ez is reached, constant voltage diode 4 and diode (4I) become conductive, and the starting pulse supply circuit W operates.
Silicon ζ1,11 sum (I IIK, driftwood, child 01 turns on and DC output voltage B.

が」二昇して定格(11’(となり水平出力回路(14
)等を起動する。
The horizontal output circuit (14'
) etc.

しかしながら、この種の従来回路は、定7Ci圧ダイオ
ード鴫のツェナー1u圧ILlにより作動する構成0)
ため、7a源m圧が定格値よりも高くなった場合、B、
−El、 > 132    ・・・・・・・・・ ω
といった関係になると、誤差検出位相制御回路(至)の
動作には関係なくシリコン制御整流素子03はターンオ
ンしてしまう。そのためツェナー「J圧EZは高い値に
選ぶ必要がある9、一方、眠Z1中中、圧が定格値より
も低くなった場合、発振スタートの開始I+、?圧は、 Bl  132 、、> El    ・・・・・・・
  (のといった関係を満足しなければならず、ツJ−
ナー電圧1i2を高い値に選ぶと寵汁畢しトが定1【召
a“1よりも低くなった所では発振スタートしない3−
いった問題が発生ずる。このように?7.′来1iil
 fI!1”+では定IHj、珪タイオード(4I#の
ツェナーfil圧Iら、1こよる制約で、1tLlII
′JN電圧の使用範囲が狭いといった欠点がJ)った。
However, this type of conventional circuit operates with a constant 7 Ci voltage diode Zener 1 u voltage ILl.
Therefore, if the 7a source m pressure becomes higher than the rated value, B,
−El, > 132 ・・・・・・・・・ω
In such a relationship, the silicon-controlled rectifying element 03 is turned on regardless of the operation of the error detection phase control circuit (to). Therefore, it is necessary to select a high value for Zener's J pressure EZ9. On the other hand, if the pressure becomes lower than the rated value during sleep Z1, the starting I+,? pressure for oscillation start is Bl 132 , > El・・・・・・・・・
The relationship such as () must be satisfied, and
If the ner voltage 1i2 is selected to a high value, the oscillation will not start when the voltage is lower than 1.
A problem will occur. in this way? 7. 'Last 1iil
fI! At 1"+, constant IHj, silicon diode (4I# Zener fil pressure I, etc., 1tLlII
The drawback was that the usage range of the JN voltage was narrow.

発明の目的 本発明は上記従来の欠点を解消するもので、■)。purpose of invention The present invention solves the above-mentioned conventional drawbacks.

源電圧の使用範囲が広いものを提供゛することteL4
的とする。
To provide a product with a wide usable range of source voltage teL4
target

発明の構成 本発明の電源回路は、直流電源入力端子に導出された被
制御直流入力電圧をシリコン制御整tIlF、素子を用
いて安定化するように構成すZlと共に、シリコン制御
整流素子の始動パルス併結回路として、被制御直流入力
電圧を分割抵抗で直接降圧し、その分割抵抗の中点を一
端が接地されたシリコン双方向スイッチング素子の他t
ム11に電流阻止用抵抗を介して接続し、1−→ンジス
タのエミッタを分割抵抗の中点に接続しI)NP l・
ランジスタのベースをシリコン双方向スイッチング素子
の他端に接続して構成し、トランジスタのコレクタより
ダ・rオードをl1irj方向に接続して011記シリ
コン制御JP、流;)子のゲートf[f極に、始動パル
スを供給rること4・特徴とする。
Structure of the Invention The power supply circuit of the present invention is configured to stabilize the controlled DC input voltage derived to the DC power input terminal using a silicon-controlled rectifier tIIF, Zl, and a starting pulse of the silicon-controlled rectifier. As a coupling circuit, the controlled DC input voltage is directly stepped down by a dividing resistor, and the midpoint of the dividing resistor is connected to a silicon bidirectional switching element with one end grounded.
I) NP l・
The base of the transistor is connected to the other end of the silicon bidirectional switching element, and the diode is connected from the collector of the transistor in the l1irj direction. 4. It is characterized by supplying a starting pulse to.

実施例の説明 以下、本発明の一実施例を第2図と第8 [y/l t
r基づいて説明する。tAお、1441図と同様のもの
には同一・符弓を(Jけでその説明を省く。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 2 and 8.
The explanation will be based on r. tA, the same symbol is used for items similar to those in Figure 1441 (I will omit the explanation with a J key).

本実施例の’/71帥回路の始動パルス供給回路(2(
すは次のように4p’+ L′v1されでいる。
The starting pulse supply circuit (2(
The sum is 4p'+L'v1 as follows.

第2図においで、整流平滑−1路(7)の出力gシiの
直流屯湘入力端子(80こ導出さ11だ被制御部111
シ入力屯圧B、を、分割抵抗142及び(転)にて分割
降圧し、分子;す抵抗@り及び(4漫の中点より市、流
阻由用抵抗(ii・をnして、一端が接地されたシリコ
ン双方向スイッチング素子〔以下、SBSと称す〕四の
他端に接続する。
In Fig. 2, the output g of the rectifying and smoothing circuit (7) is connected to the DC input terminal (80, which is derived from 11).
The input pressure B, is divided and stepped down by the dividing resistor 142 and (transition), and the numerator; One end is connected to the other end of a silicon bidirectional switching element (hereinafter referred to as SBS) which is grounded.

また、分割抵抗1<2及び03の中点にはPN、I’ 
)ランジスタ+41’9のエミッタが接続され、PNP
 )ランジスタ囮のベースは電流、阻止用抵抗041と
5BS(461との交点に接続され、PNPトランジス
タ14fQのコレクタよりダイオードi4′fIを順方
向に接続し、ダイオード@力のカソードをシリコン制御
整流素子03のゲート?lE 4Th勾に接続し、始動
パルス供給回路(ハ)を構成している。
Also, at the midpoint of dividing resistors 1<2 and 03, PN, I'
) The emitter of transistor +41'9 is connected, PNP
) The base of the transistor decoy is connected to the intersection of the current and blocking resistors 041 and 5BS (461), and the diode i4'fI is connected in the forward direction from the collector of the PNP transistor 14fQ, and the cathode of the diode @ is connected to the silicon-controlled rectifier element. It is connected to the gate ?1E4Th of 03, and constitutes a starting pulse supply circuit (c).

このように構成したため、電源スイッチ絆:)を投入す
ると、整流平滑回路(7)を介して直流電源入力端子(
8)に直流入力電圧B1が導出さtl、分割抵抗@4及
び〔4によって分割降圧されたm圧B3が5I3S H
[9のスイッチング電圧VSよりも高くなるとtll流
、阻止用抵抗@旬を介してSBS knはオン状態とな
り、PNPトランジスタ四のベース電流が流lするため
、PNPトランジスタ顛はオン状態となり、ダイオード
147Iを介してシリコン制御整流素子θ葎のゲート電
極に)に電流が流れ、シリコン制御整流素子03がター
ンオンして直流出力電圧B2が上昇して定格値となり水
平出力回路04等を起動する。また、SBS f41は
第3図の特性に示すように、一旦オンした後はオン電圧
Vtまで急速に下かつてオンI’lj LE V□を保
持しつづける特性を持った素子である。このような特性
をもった素子が必要な理由は、シリコン制御整流素子0
1のゲート電圧V6規格に対して5BS(9)のスイッ
チング電圧VSは十分に高い電圧が必要であるが、一旦
シリコン制御整流素子0;1がターンオンした後は誤差
検出位相制御回路(ハ)よりのゲートパルスによってシ
リコン制御整流素子a1を制御するので始動パルス供給
回路(ハ)からの影響をなくしておくためである。シリ
コン制御整流素子03のゲート電圧は最低3ボルトでJ
)す、SBS 曲のスイッチング電圧VSは約8ボルト
、オン電圧VTは1.4ボルトである。II+は保持Y
a流である。
With this configuration, when the power switch Kizuna:) is turned on, the DC power input terminal (
8) DC input voltage B1 is derived tl, m voltage B3 divided and stepped down by dividing resistor @4 and [4 is 5I3S H
[When it becomes higher than the switching voltage VS of 9, SBS kn is turned on through the blocking resistor @shun, and the base current of PNP transistor 4 flows, so the PNP transistor 2 is turned on, and the diode 147I is turned on. A current flows to the gate electrode of the silicon-controlled rectifier 03 through the gate electrode of the silicon-controlled rectifier 03, and the silicon-controlled rectifier 03 is turned on, causing the DC output voltage B2 to rise to the rated value and activate the horizontal output circuit 04 and the like. Further, as shown in the characteristics of FIG. 3, the SBS f41 is an element having a characteristic that once it is turned on, it rapidly decreases to the on-voltage Vt and continues to maintain the on-state I'lj LE V□. The reason why an element with such characteristics is necessary is that the silicon-controlled rectifying element 0
The switching voltage VS of 5BS (9) needs to be a sufficiently high voltage for the gate voltage V6 standard of 1, but once the silicon controlled rectifier 0;1 is turned on, the error detection phase control circuit (c) This is to eliminate the influence from the starting pulse supply circuit (c) since the silicon-controlled rectifying element a1 is controlled by the gate pulse. The gate voltage of silicon controlled rectifier 03 is J at a minimum of 3 volts.
), SBS The switching voltage VS of the song is about 8 volts, and the on-voltage VT is 1.4 volts. II+ is retained Y
This is the A style.

このため、シリコン制御整流素子a3がターンオンした
後、始動パルス供給回路−の出力はシリコン制御整流素
子αJのゲート電圧VCより十分に低い値に保持される
ため、二度とシリコン制御整流素子的に影響を与えるこ
とはない。
Therefore, after the silicon-controlled rectifier a3 is turned on, the output of the starting pulse supply circuit is held at a value sufficiently lower than the gate voltage VC of the silicon-controlled rectifier αJ, so that it will never affect the silicon-controlled rectifier again. I won't give anything.

発明の効果 以上のように本発明によれば次の効果を得ることができ
る。
Effects of the Invention As described above, according to the present invention, the following effects can be obtained.

本発明の電源回路における始動パルス供給回路は、シリ
コン双方向スイッチング素子の特性により作動するため
、従来のツェナー電圧によるものの欠点であった電源電
圧の使用範囲が狭くて電源電圧の規制を受けると云った
ことなく、広範囲にわたって常に良好な始動パルス供給
動作を行うことができ、確実、かつ安定に水平出力回路
等の起動をなし得るものである。
Since the starting pulse supply circuit in the power supply circuit of the present invention operates based on the characteristics of a silicon bidirectional switching element, it has a narrow usable range of power supply voltage and is subject to power supply voltage regulations, which was a drawback of the conventional Zener voltage. It is possible to always perform a good starting pulse supply operation over a wide range without any trouble, and to start the horizontal output circuit etc. reliably and stably.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電源回路図、第2図は本発明の電源回路
の一実施例の回路図、第3図はシリコン双方向スイッチ
ング素子の静特性図である。 (8)・・・直流td源大入力端子Q・・シリコン制御
整流素子、例・・・始動パルス供給回路、(財)・・・
ゲー) ![極、@2@器・・・分割抵抗、@勺・・・
電流阻止用抵抗、hri・・シリコン双方向スイッチン
グ素子、囮・・・PNP トランジスタ、1471・・
・ダイオード 代理人  森 本 義 弘 第1図 第J図
FIG. 1 is a conventional power supply circuit diagram, FIG. 2 is a circuit diagram of an embodiment of the power supply circuit of the present invention, and FIG. 3 is a static characteristic diagram of a silicon bidirectional switching element. (8)...DC TD source large input terminal Q...Silicon controlled rectifier, example...Starting pulse supply circuit, Foundation...
Game)! [pole, @2@unit...divided resistor, @tai...
Current blocking resistor, hri... silicon bidirectional switching element, decoy... PNP transistor, 1471...
・Diode agent Yoshihiro Morimoto Figure 1 Figure J

Claims (1)

【特許請求の範囲】[Claims] 1、 直流m源入力端子lζ加えられた被制御直流入力
電圧をシリコン制御整流素子を用いて安定化して出力す
るように構成すると共に、niミノシリコン制御整流素
子の始動パルス供給回路として、011記被制御直流人
力m圧を分割抵抗で直接降圧し、その分割抵抗の中点を
一端が接地されたシリコン双方向スイッチング素子の他
端iこmb’+f、 I!II止用抵杭用抵抗て接続し
、トランジスタのエミッタを1111記分割抵抗の中点
に接続しnIJ記トランジスタのベースを前記シリコン
双方向スイッチング素子の+jl記他端に接続して構成
し、81記トランジスタのコレクタより夕“イオードを
順方向に接続して0ロ記シリコン制御整流素子のゲート
電極に始動パルスを供給するようにしたYu汎1回路。
1. The control DC input voltage applied to the DC m source input terminal lζ is configured to be stabilized and output using a silicon controlled rectifier, and as a starting pulse supply circuit for the ni minosilicon controlled rectifier, the circuit described in 011 is used. The controlled DC human pressure m is directly stepped down by a dividing resistor, and the middle point of the dividing resistor is connected to the other end of a silicon bidirectional switching element whose one end is grounded icomb'+f, I! 81, the emitter of the transistor is connected to the midpoint of the dividing resistor 1111, and the base of the transistor nIJ is connected to the other end of the silicon bidirectional switching element +jl; A Yu general 1 circuit in which a starting pulse is supplied to the gate electrode of the silicon-controlled rectifier by connecting the diode in the forward direction from the collector of the transistor.
JP14313382A 1982-08-17 1982-08-17 Power supply circuit Granted JPS5932261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14313382A JPS5932261A (en) 1982-08-17 1982-08-17 Power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14313382A JPS5932261A (en) 1982-08-17 1982-08-17 Power supply circuit

Publications (2)

Publication Number Publication Date
JPS5932261A true JPS5932261A (en) 1984-02-21
JPS6322755B2 JPS6322755B2 (en) 1988-05-13

Family

ID=15331680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14313382A Granted JPS5932261A (en) 1982-08-17 1982-08-17 Power supply circuit

Country Status (1)

Country Link
JP (1) JPS5932261A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866525A (en) * 1988-11-01 1989-09-12 Thomson Consumer Electronics, Inc. Television apparatus power supply

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476153A (en) * 1990-07-18 1992-03-10 Sekisui Chem Co Ltd Tiling window decorative material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866525A (en) * 1988-11-01 1989-09-12 Thomson Consumer Electronics, Inc. Television apparatus power supply

Also Published As

Publication number Publication date
JPS6322755B2 (en) 1988-05-13

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