JPS5932141A - Manufacture of electronic device - Google Patents

Manufacture of electronic device

Info

Publication number
JPS5932141A
JPS5932141A JP57141149A JP14114982A JPS5932141A JP S5932141 A JPS5932141 A JP S5932141A JP 57141149 A JP57141149 A JP 57141149A JP 14114982 A JP14114982 A JP 14114982A JP S5932141 A JPS5932141 A JP S5932141A
Authority
JP
Japan
Prior art keywords
pellets
substrate
melting point
pellet
low melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57141149A
Other languages
Japanese (ja)
Inventor
Atsushi Saiki
斉木　篤
Yukiyoshi Harada
原田　征喜
Yoshinori Oketa
桶田　吉紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57141149A priority Critical patent/JPS5932141A/en
Publication of JPS5932141A publication Critical patent/JPS5932141A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Abstract

PURPOSE:To protect an electronic device from a damage by plating an electronic part on a low melting point material layer, heating the part and burying it in the layer, thereby facilitating the handling of the part. CONSTITUTION:IC pellets 2-4 are aligned on a polytetrafluoroethylene plate 1 in a matrix shape, heated at 190-220 deg.C for 10-60min so as to soften the plate, pressed by the own weight of the pellets or as required and buried. Then, the surface is covered with polyimide resin 5, a window is opened, and aluminum wirings 6-10 are deposited. Then, an LSI covered with an insulator can be readily assembled. When the pellets are treated by burying them in a low melting point material in this manner, they can be more readily handed as compared with a sole pellet, and the support can protect the surfaces of the pellets.

Description

【発明の詳細な説明】 本発明は、ｍ子装置の製造方法に関し、骨に）電子部品
の埋めこみ方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a m-child device, and to a method for implanting electronic components (in bone).

ｆｌＩ子部品、脣に集積回路、大規模集積回路等の半導
体ベレットは、極めて不埒＜、かつう丁いため、ハンド
リングが困難でらシ、作業がしにくく、かつ組立、実装
の段階でベレット表面に有害な損傷葡与えることがしば
しば発生した。ベレット自体が不埒くかつ極めてう丁い
ものでろる以上、こｔｔ２メ１′１けることは仲々出米
ない。Semiconductor pellets for FLI child parts, integrated circuits, large-scale integrated circuits, etc. are extremely unsightly and precise, making them difficult to handle and work with, and causing damage to the pellet surface during assembly and mounting. Harmful damage to the grapes often occurred. Since the beret itself is unscrupulous and extremely unscrupulous, there is no way it can be used.

これ【解決する方法として、ベレン）　ｙｘ曲の物に埋
めこみ、こｎｙ＜支持物として作業を進めｆｔは、ベレ
ット単体よりもハンドリングがし易く、かつこの支持物
がベレットの表面に４１ｉ偽からすることが分った。This [as a solution, Belen] embed it in the object of the yx song, and proceed with the work as a support.The ft is easier to handle than the pellet itself, and this support makes it possible to prevent the surface of the pellet from 41i false. I found out.

本発明の目的は、電子部品のノ・ンドリンクケ容易にし
た電子装置の新規な組立方法ケ提供することで′ｔり夛
、更に曲の目的をま電子書５１〜品ケ４０傷から守る方
法會提供することにある。An object of the present invention is to provide a new method for assembling an electronic device that facilitates the unlinking of electronic components, and also protects the purpose of the song from damage. It is about providing.

以下、本発明の詳ｈ（１１に実施例に基づいて説明忙す
る。Hereinafter, the present invention will be explained in detail based on examples in Section 11.

第１図に示すように、低融点相オ、１、例えば約１９０
℃の融点ｔ４１するポリテトラフルオロエチレンからな
る基板１を用−擢し、その’７％　１ｉＴに債数個の半
導体ベレット２．３．４のｐＨき電子部品を載置する。As shown in FIG.
A substrate 1 made of polytetrafluoroethylene having a melting point of t41° C. is used, and several semiconductor pellets with a pH of 2.3.4 are placed on the substrate 1 at a temperature of 7% 1iT.

これらの半導体ベレットは例えば、ノリコンウェーハに
通常の不純物拡散処理等の半導体製造プロセスによって
、所定の桿屯型の一！Ｉ’専体ｔｆ１域及びＰＭ接合が
形成場れている単体トランジスタベレント又は、半導体
集槓回ｒ１１ベレットであυ・電極又は配線が必要な主
表面が上側になるよう載置芒れる。第５図は、このよう
に半導体ベレン］・が格子状（マトリックス状）に配置
された状、明ｒ示すための平面図である。然る後、この
基板１？約１９０℃乃至２２０℃（型置しくは基板の融
点又はそれ以上の温度）にて１０分乃至６０分間加熱す
ることによって、上記低融点材料金軟化せしめ、その中
に上記半導体ベレット上部め込む１．この時半導体ベレ
ット自体の自重によって、軟化芒れた基板内に半導体ベ
レットの底面及び側面が埋め込１れるが、必要であ１ｔ
ば、ベレット上部より適当女ウェイトをかけるようにし
てもよい。このようにして第２図に示すように、はぼ平
坦な平面に袂数のベレット？埋め込むことができる。For example, these semiconductor pellets are formed into a predetermined cylindrical shape by applying a semiconductor manufacturing process such as a normal impurity diffusion treatment to a Noricon wafer. A single transistor beamlet or a semiconductor integrated circuit r11 beamlet in which the I' dedicated tf1 region and PM junction are formed is placed so that the main surface where electrodes or wiring are required is on the upper side. FIG. 5 is a plan view to clearly show how the semiconductor belenium is arranged in a lattice shape (matrix shape) in this way. After that, this board 1? By heating at about 190° C. to 220° C. (temperature equal to or higher than the melting point of the mold or substrate) for 10 to 60 minutes, the low melting point material is softened, and the upper part of the semiconductor pellet is inserted into it. ．． At this time, due to the weight of the semiconductor pellet itself, the bottom and side surfaces of the semiconductor pellet are buried in the softened substrate.
For example, an appropriate female weight may be applied from the top of the bellet. In this way, as shown in Figure 2, a number of bellets can be placed on a flat plane. Can be embedded.

然る後、第３図に示すよう適切な絶縁被膜例えば、ポリ
イミド樹脂被膜５　ｆ　、コーディングによって基板底
面及びベレット上面に形成し、所望の開孔部全般け、ア
ルミニウム等の導１１材料の蒸着技術によってＷＬ極又
は配線層６，７，８，９．１０盆形成することによって
、半導体材料訝面が絶縁物によって包囲さｎた大規模半
導体電子装置ｒ得ることができる。なお、半導体ベレッ
トに個々に分離することが必要な場合には、第４図（゛
こ示すように、各ベレットの所定の半導体領域に蒸着、
メッキ、半ＬＨディップ等の手段により電極１．１．１
２゜１３．１４．１５．１６を形成した後、破線１７゜
１８．１９のとうしに基板全切断（タイシング又はスク
ライブ）することによって［！Ｉ々のベレットに分離し
でもより０このように分ＡＩ　８　ｆｔたベレットは第
１１図に示すように、配線基板２６上の導電層２７．２
８に実装することができる。このようにすれば、極めて
小避くて、）・ンドリングしにくい半導体ベレットの如
き電子部品であつでも、基板１が支持体として作用せし
めることによって、組立、実装のノ・ンドリンクかしや
丁くなり、特にベレット上部に有害な損傷金与えること
なく処理することができる。又基板として透明体ヶ用い
ることによって実装、組立の際には上部より接続位置関
係＼接続状態を確認しながら行なうことができる。Thereafter, as shown in FIG. 3, a suitable insulating coating, such as a polyimide resin coating 5f, is formed on the bottom surface of the substrate and the top surface of the pellet by coating, and a conductive material such as aluminum is deposited over the entire desired opening area using a vapor deposition technique. By forming WL poles or wiring layers 6, 7, 8, 9, and 10 according to the present invention, it is possible to obtain a large-scale semiconductor electronic device in which the bottom surface of the semiconductor material is surrounded by an insulator. In addition, if it is necessary to separate the semiconductor pellets individually, as shown in FIG.
Electrode 1.1.1 by means of plating, half-LH dip, etc.
After forming 2°13.14.15.16, the entire board is cut (tied or scribed) along the dashed line 17°18.19 [! Even if the pellets are separated into individual pellets, the pellets with an AI of 8 ft can be separated into conductive layers 27.2 on the wiring board 26, as shown in FIG.
8 can be implemented. In this way, even if the electronic component is extremely small and difficult to handle, such as a semiconductor pellet, the board 1 can act as a support, making it easy to assemble and mount the electronic component, such as a semiconductor pellet. The gold can be processed without causing harmful damage, especially to the upper part of the pellet. Furthermore, by using a transparent body as the substrate, mounting and assembly can be carried out while checking the connection positional relationship/connection state from above.

上記実施例では、基板１として平坦な衆面ゲ七するもの
ｔ用いで説明したか、第６図・・に示すように、予めベ
レン）？２のせるべき箇所にくぼみ？ｆ−設け、正確な
位置に配置できるようにしてもよい。In the above embodiment, the substrate 1 was explained using a flat, convex surface, as shown in FIG. Is there a dent in the place where 2 should be placed? f- may be provided so that it can be placed at an accurate position.

又、上記実施例では、絶縁膜ｊ！４５にペレント埋め込
み後に、被着することで説明したが、第７図に示すよう
に、基板２２上にペレツ）１−載置した後、ポリイミド
樹脂等の絶縁被膜？形成しておき、加熱処理することに
よって第８図に示すようにベレント全埋込込んでもよい
。Moreover, in the above embodiment, the insulating film j! 45, the pellets are placed on the substrate 22 and then coated with an insulating coating such as polyimide resin. It is also possible to completely embed the berent as shown in FIG. 8 by forming it and heat-treating it.

なお、絶縁被膜としてポリイミド樹脂を用いた場合には
、表面に凹凸があっても極めて平坦な表面に仕上げるこ
とができるので、特に本発明の組立方法では４１効であ
る。Note that when polyimide resin is used as the insulating coating, it is possible to finish the surface to be extremely flat even if the surface is uneven, so the assembly method of the present invention is particularly effective.

第９図及び第１０□□□は、更に池の変形例金示すもの
で、先に述べた各種実施例において用いた基板の代セに
、比較的低融点（例えば３００℃）を有する絶縁基板（
フンン樹脂、例えばテフロンＰＦＡ、テフロンＦＴＰＫ
等）２４の上に、比較的低融点（例えば１８０℃）の絶
縁材料層（テフゼル等）２５に′Ｉｇｒ定の厚さに設け
たものｔ使用しても、本発明の実施が可能である。この
場合、熱による基板自体の変形を極めて小石くすること
ができるので好都合である。FIGS. 9 and 10 □□□ further show a modification of the pond, in which an insulating substrate having a relatively low melting point (for example, 300°C) is used as a substitute for the substrate used in the various embodiments described above. (
Fun resin, such as Teflon PFA, Teflon FTPK
It is also possible to carry out the present invention even if an insulating material layer 25 having a relatively low melting point (for example, 180° C.) (Tefzel, etc.) is provided on top of the layer 24 with a constant thickness. . In this case, it is advantageous because the deformation of the substrate itself due to heat can be minimized.

更に第３図の絶縁ｊ漠５及び第７図の絶縁膜２３として
は、ポリイミド樹脂に限らず、その能の絶縁拐料例えば
、環化ポリブタジェン（ト１本合成ゴム製）やドライフ
ィルム（日立化成製）で知られる耐熱感光性樹脂等音用
いることも有効でるる。Furthermore, the insulation layer 5 in FIG. 3 and the insulation film 23 in FIG. It is also effective to use a heat-resistant photosensitive resin (made by Kasei Co., Ltd.).

その場合には、硬化湯度を基板１のポリテトラフルオロ
エチレンとほぼ近似した値に合わせることができるので
、製造プロセス上極めてのぞましい。In this case, the hardening temperature can be adjusted to a value almost similar to that of the polytetrafluoroethylene of the substrate 1, which is extremely desirable in terms of the manufacturing process.

又、基板としては円形形状のもの會用いてもよいが、第
５図に示すように四角形のものケ用いることによって、
周辺部の無駄缶なくし、拐料効出【艮く使用することが
可能である。Although a circular substrate may be used as the substrate, by using a rectangular substrate as shown in FIG.
It eliminates wasted cans around the area and is effective for cleaning.

更に、上記実施例では、加熱方法’（ｚ／苛定していな
いが、ベレット載置部葡局部的に加熱Ｔることによって
基板の変形を極力おさえる手段も有効である。Furthermore, although the heating method '(z/) is not used in the above embodiment, it is also effective to locally heat the pellet mounting portion to suppress deformation of the substrate as much as possible.

又、第１２図は、本発明の一実施例によシ段造嘔れた４
個の集積回路チップｒ絶縁基板１内に埋め込み、その！
そ面に設けられたポリイミド樹脂等の絶縁被膜５の開口
部を通して各集イ貨回路チップ間の配線層６　、７　、
８が形成きれ、それらの表面ケ更に絶縁膜２９で被刊ネ
れ、外Ｂｂリード線接続用ポンディングパッド部３０．
３１が露出された超大規模ｔｈ積回路の平面概略図孕示
すものであシ、第１３図は同図のＡ−Ａ’線に沿ったｔ
ｕｆｔ面概略図會示すものである。Further, FIG. 12 shows a stage 4 constructed according to an embodiment of the present invention.
Embedded in the insulating substrate 1, the integrated circuit chip r, the!
The wiring layers 6 , 7 , between each integrated circuit chip are passed through the openings of the insulating coating 5 made of polyimide resin or the like provided on its surface.
8 are completely formed, their surfaces are further covered with an insulating film 29, and a bonding pad portion 30 for connecting the outer Bb lead wire is formed.
13 is a plan view schematic diagram of a super large-scale th product circuit with 31 exposed, and FIG.
A schematic diagram of the UFT surface is shown.

なお、上記説明では、半導体ベレットｒ埋め込んだ半導
体装置の製造方法？中心に説明したが、コンデンサや抵
抗等の電子部品を埋め【へんで市、子装置ｉｔ會製造す
る際にも適用可能である１゜更に父、低融点材料として
絶縁物に限らず、導屯体孕用いてもよいことは云う葦で
もない。In addition, in the above description, the method for manufacturing a semiconductor device embedded with a semiconductor pellet r? Although the explanation mainly focuses on filling electronic components such as capacitors and resistors, it can also be applied when manufacturing subsidiary IT companies. There is nothing wrong with saying that it is okay to use it for pregnancy.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図、第３図、第４図、第６図、第７図、第
８図、第９図、第１０図、第１１図及び第１３図は本発
明に係る電子装置のＪＲ造方法【説明するための各〜ｒ
面図であり、 第５図及び第１２図は電子装置の各平ＩＣ旧図を示１．
２１．２２．２４−・・基板、２．３．４−・・半導体
ベレット（デツプ）、５．２３．２９・・絶縁被膜、６
，７．８，９．１．０・・・配７１尿又は引出し峰イで
！用導°１ＦＣ層。1, 2, 3, 4, 6, 7, 8, 9, 10, 11, and 13 are electronic devices according to the present invention. JR construction method [Each to explain
FIG. 5 and FIG. 12 show old views of each flat IC of an electronic device.
21.22.24--Substrate, 2.3.4--Semiconductor pellet (depth), 5.23.29--Insulating coating, 6
, 7.8, 9.1.0...71 urine or drawer mine! Conductive °1FC layer.

Claims (1)

【特許請求の範囲】[Claims] ■、低融点材料層表面に電子部凸金載置し、加熱処理ｒ
施こ丁ことによって、前記電子部品葡前記低融点月料層
内に埋めこむこと荀特徴とする電子装置の製造方法。■ Place the electronic part on the surface of the low melting point material layer and heat it.
A method of manufacturing an electronic device, characterized in that the electronic component is embedded in the low melting point layer by cutting.
JP57141149A 1982-08-16 1982-08-16 Manufacture of electronic device Pending JPS5932141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57141149A JPS5932141A (en) 1982-08-16 1982-08-16 Manufacture of electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57141149A JPS5932141A (en) 1982-08-16 1982-08-16 Manufacture of electronic device

Publications (1)

Publication Number Publication Date
JPS5932141A true JPS5932141A (en) 1984-02-21

Family

ID=15285280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57141149A Pending JPS5932141A (en) 1982-08-16 1982-08-16 Manufacture of electronic device

Country Status (1)

Country Link
JP (1) JPS5932141A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1152464A2 (en) * 2000-04-28 2001-11-07 Sony Corporation Chip size package semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1152464A2 (en) * 2000-04-28 2001-11-07 Sony Corporation Chip size package semiconductor device and method of manufacturing the same
EP1152464A3 (en) * 2000-04-28 2006-02-22 Sony Corporation Chip size package semiconductor device and method of manufacturing the same

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